Abstract: A method and device for generating a waveform according to programmable duty cycle control bits from a divided frequency reference signal. The device may include: a timing circuit that inputs a CLOCK signal having a 50% duty cycle to a divider, whose output varies over a plurality of divide-by-n settings; and a waveform generator. The waveform generator may, after a last low clock pulse is counted for a current evaluative cycle and before a beginning of a next evaluative cycle, shift a prior duty cycle waveform by ½ of a CLOCK cycle, to provide an incremented duty cycle for the waveform. Alternatively, the waveform generator may increment a gating signal from an adder, which determines an onset of an inoperative or low portion of the programmed duty cycle.

Abstract: A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width as sociated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.

Abstract: A digital-to-analog converter (DAC) includes a resistor leg that is switchably connected to a first voltage reference via an n-channel MOSFET and to a second voltage reference via a p-channel MOSFET, and a generator circuit. The generator circuit further includes a first sub-circuit for generating a drive voltage (Vgn) and a second sub-circuit for a) offsetting the first drive voltage by an offset voltage to generate a second drive voltage, and b) supplying the second drive voltage to a gate of one of the first NMOS and the first PMOS.

Abstract: A duty cycle adjustment circuit includes a clock signal input node; a clock signal output node; a control voltage generation circuit coupled to the clock signal input node; and a first inverter configured to receive an inverter input signal comprising a sum of an input clock signal received at the clock signal input node and a control voltage received from the control voltage generation circuit, and to output an output clock signal at the clock signal output node, wherein variation of the control voltage is configured to vary a duty cycle of the output clock signal.

Abstract: A pulse width modulation (PWM) system can include at least a first pulse width modulation circuit that generates a first pulse width modulated signal in synchronism with a first clock signal; a source circuit that provides a second pulse width modulated signal that is phase shifted with respect to the first pulse width modulated signal; and output logic that logically combines the first and second pulse width modulated signals to generate a pulse width modulated output signal.

Abstract: An adjusting circuit of duty cycle includes an edge detecting circuit, a flip-flop connected to the edge detecting circuit, a feedback control circuit connected to the flip-flop and a charge pump circuit connected to the feedback control circuit. The edge detecting circuit detects an edge of an inputted clock signal. The flip-flop sets an outputting terminal thereof at a first level according to a clock signal outputted by the edge detecting circuit. The charge pump circuit controls a duration of the first level outputted the outputting terminal of the flip-flop by charging and discharging a capacitor. The flip-flop sets the outputting terminal thereof at a second level contrary to the first level according to a clock signal outputted by the feedback control circuit. An adjusting method of duty cycle is also disclosed. The adjusting circuit of duty cycle has a simple structure, a stable performance and a fast speed.

Abstract: Provided are a delay locked loop (DLL) that may can be included in a data processing device and may include a duty correction circuit, and a duty correction method of such a DLL. The duty correction method includes aligning a second transition of an output clock at a first transition of a clock for duty correction, sampling the clock for duty correction at the first transition of the output clock to detect an error of a duty cycle, and performing duty correction using a skewed gate chain according to the detected error of a duty cycle.

Abstract: Circuits and methods for generating a pulse are provided. The generating can comprise receiving at least one trigger input signal with a pulse generating circuit; generating a voltage pulse having a duration less than the avalanche time of a transistor in response to at least a portion of the at least one trigger input signal with the pulse generating circuit; transmitting the voltage pulse from the pulse generating circuit to a terminal of the transistor, the transistor constructed and arranged to be operable in an avalanche mode; and outputting an avalanche pulse from at least one terminal of the transistor in response to the voltage pulse. In some embodiments, the pulse can be transmitted with an antenna in a radar system, and a return pulse can be received and processed.

Abstract: A circuit for filtering narrow pulse and compensating wide pulse, including a signal shaping circuit, a filter circuit, and a pulse width compensating circuit. The signal shaping circuit processes an input signal and transmits the input signal to the filter circuit. The filter circuit filters off narrow pulses of the input signal. The pulse width compensating circuit compensates the wide pulses of the input signal and outputs an output signal.

Abstract: A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.

Abstract: A duty-cycle correction circuit comprises a plurality of AC-coupled, independently-biased inverter stages connected in series. A periodic signal is applied to an input of the plurality of inverter stages. Each inverter stage comprises an inverter with a resistive element connected in feedback between its output and input nodes. Each inverter stage is AC-coupled to a prior stage via a capacitor. The AC-coupling allows the signal to pass between inverter stages, but DC-isolates each inverter stage from adjacent stages, allowing each stage to maintain an independent DC bias of the signal at that stage. By virtue of the feedback resistive element, each stage defines a transition point between high and low signal states. Due to non-zero rise and fall times of the periodic signal, the independent DC bias of each stage is operative to incrementally shift the transition point of the periodic signal at each stage towards a desired duty-cycle.

Abstract: A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal.

Abstract: A duty correction circuit includes a clock buffer configured to buffer an input clock and generate a buffer clock, a swing level conversion block configured to generate an internal clock, which transitions to levels of a sync voltage and a power supply voltage, in response to a voltage level of the buffer clock, a duty control block configured to generate duty information and frequency information by using a high pulse width and a low pulse width of the internal clock, and a current control block configured to control a time point, at which a logic value of the buffer clock transitions, in response to the duty information and the frequency information. The current control block includes a plurality of first current paths coupled in parallel to one another in order to control the time point at which the logic value of the buffer clock transitions.

Abstract: A circuit for correcting a duty-cycle comprises a duty-cycle adjuster for changing a duty-rate of an input clock signal according to a duty control signal; a duty-cycle detector for detecting a duty-rate of an output clock signal based on the input clock signal and the output clock signal from the duty-cycle adjuster; and an algorithm-based digital controller for performing an algorithm according to a duty-rate detection signal outputted from the duty-cycle detector to generate the duty control signal.

Abstract: A controller for a switch and a method of operating the same. In one embodiment, the controller is configured to measure a voltage of a control terminal of the switch and select a first mode of operation if the voltage of the control terminal is greater than a threshold voltage, and a second mode of operation if the voltage of the control terminal is less than the threshold voltage.

Abstract: Circuits and methods to limit an in-rush current of a load circuit such as a processor are disclosed. A charge pump is used as driver for switches with pulse modulation width (PWM) control on the duty cycle of a clock. A clock generator generates a ramp signal with variable slope and a reference voltage. The slope of the ramp signal is dependent on the in-rush current of the switch. No dedicated slew rate driver or an external capacitor is required. The main building blocks are: a charge pump used as driver connected to single supply domain, one external (or internal) switch device, a single capacitive feedback between the switch device and the PWM control, and a PWM control comprising a fix frequency voltage triangular pulse generator with variable slope proportional to the in-rush current measurement.

Abstract: The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

Abstract: The present invention provides a switching device and a method for preventing malfunction of the same. The switching device includes: a controller for outputting a plurality of digital control signals; a protecting unit connected to the controller for protecting all signals when the plurality of digital control signals outputted from the controller are simultaneously received at a state of ON; a gate driver connected to the protecting unit for generating a switch control signal by converting the control signal passed through the protecting unit; and a plurality of switches connected to the gate driver for individually performing ON•OFF operations according to each of the switching control signals.

Abstract: Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Abstract: A DC source generates a DC voltage between a positive electrode and a negative electrode. An inductive element and a parallel-connected switch-circuits unit are provided in a conductive path extending from the positive electrode to the negative electrode. The parallel-connected switch-circuits unit includes a plurality of switch circuits connected in parallel with one another. The switch circuit opens and closes the conductive path in accordance with a drive signal inputted from a drive circuit. The drive signal causes the plurality of switch circuits to successively perform an ON operation in which the conductive path is closed and then opened. A pulse voltage generation period in which a pulse voltage occurs in the inductive element continuously follows an ON period which is a duration from when the conductive path is closed to when the conductive path is opened.

Abstract: There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input pulse duration; duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration; delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; logically combining the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration; and outputting the output pulse signal at an output port.

Abstract: Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the duty cycle adjustor. First and second phase detectors have first inputs coupled to the duty cycle adjustor through an inverter and second inputs coupled to the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter.

Abstract: A method is provided. A noise shaped signal having a plurality of instants is generated with each instant being associated with at least one of a plurality of output levels. A next phase is selected for each instant, where each next phase is a circularly shifted phase based at least in part on a previous phase for the associated output level for its instant. A plurality of PWM signals is then generated using the phase for each instant, and an amplified signal is generated from the plurality of PWM signals.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Abstract: A duty correcting circuit includes a duty steerer circuit, a differential clock generator, and a charge pump circuit. The duty steerer circuit corrects a duty cycle of an input clock signal in response to a duty control signal and generates an output clock signal. The differential clock generator generates two internal clock signals having a phase difference of 180° from each other based on the output clock signal. The charge pump circuit performs a charge pump operation in a differential mode in response to the internal clock signals to generate a duty control signal.

Abstract: An apparatus for measuring time interval between two edges of a clock signal and includes an edge generator, a first multi-tap delay module, a second multi-tap delay module, and a multi-element phase detector. The edge generator produces a first edge at a first output node and a second selected edge at a second output node. First multi-tap delay module provides a first incremental delay at each tap to the first edge. Second multi-tap delay module provides a second incremental delay at each tap to the second selected edge. Each element of the multi-element phase detector has first and second input terminals. The first input terminal is coupled to a selected tap of the first multi-tap delay module and the second input terminal is coupled to a corresponding tap of the second multi-tap delay module. The output terminals of the multi-element phase detector provide the value of the time interval.

Abstract: A pulse signal generation circuit includes a transfer path configured to receives and transfer a first pulse signal, a pulse adjustment unit configured to adjust a pulse width of the first pulse signal by applying charges to the transfer path in response to a control signal, and a pulse output unit configured to output a second pulse signal of the adjusted pulse width in response to an output of the transfer path.

Abstract: A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal.

Abstract: A duty cycle correction (DCC) circuit includes a duty signal generating unit configured to compare a high duration of an output clock with a low duration of the output clock in a clock cycle to generate a duty signal, a counting unit configured to count and output a preliminary code after a duty cycle correction (DCC) operation starts, a duty code generating unit configured to generate a duty code by selectively inverting or transferring without inversion the preliminary code in response to an initial value of the duty signal, and a duty cycle correcting unit configured to output the output clock by driving an input clock to a pull-up driving capacity and a pull-down driving capacity which are determined in response to the initial value of the duty signal and the duty code.

Abstract: An integrated control circuit according to aspects of the present invention includes an oscillator, a capacitor, and a logic gate. The oscillator generates a periodic timing signal that cycles between a first logic state for a first time duration and a second logic state for a second time duration. The capacitor receives a charge current in response to the periodic timing signal transitioning to the first logic state, where a voltage on the capacitor increases for the first time duration to an initial value. The logic gate generates a periodic output signal having a duty ratio that is responsive to a time that it takes the capacitor to discharge from the initial value to a reference voltage. A period of the periodic output signal is the period of the periodic timing signal.

Abstract: A method for outputting an analog value at a PWM output of a driver for a power semiconductor. The method comprises converting the analog value to a PWM signal which has two signal levels and which is at a fixed PWM frequency. For an inactive state of a binary supplementary value the PWM signal is output at the PWM output. For an active value of the supplementary value the PWM signal is output together with a supplementary signal at the PWM output. The current signal level of the PWM signal and the respective other signal level are output alternately as a supplementary signal at a signal frequency greater than the PWM frequency.

Abstract: Methods and apparatuses are provided for duty cycle correction of high-speed clock circuits. The apparatus includes a duty cycle interpolator receiving a clock source for providing a duty cycle corrected clock signal. The duty cycle corrected clock signal is filtered and compared to a reference signal, the result of which is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to the duty cycle interpolator for adjusting the duty cycle of the clock signal to provide the duty cycle corrected clock signal. The method includes filtering a duty cycle corrected clock signal to provide a filtered signal and comparing the filtered signal to a reference signal, the result of is clocked into a shift register. The shift register provides complementary N-bit duty cycle correction signals to a duty cycle interpolator for adjusting the duty cycle of a clock signal.

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract: A bias potential generating circuit includes a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ?? conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed.

Abstract: A PWM output apparatus includes a calculating circuit configured to calculate an output width of a PWM output signal of a first signal and a second signal, which have phases different from each other, based on a command value of a PWM output. A comparing circuit compares the output width and a reference period which is set longer than a predetermined dead time period. A PWM output signal generating circuit outputs the PWM output signal to a dead time inserting block as a corrected PWM output signal, when a set/clear signal generating circuit outputs the set signal, and carries out a correction of setting the first signal of the PWM output signal to be inactive to output to the dead time inserting block as the corrected PWM output signal, when the set/clear circuit outputs the clear signal. The dead time inserting block corrects the corrected PWM output signal.

Abstract: A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.

Abstract: Within hard disk drives (HDDs), for example, a preamplifier or preamp is generally used to perform read and write operations with a magnetic head. Typically, for write operations, the preamplifier generates a current waveform that uses a DC current to polarize magnetic elements within the disk and overshoot components to compensate for frequency dependent attenuation in the interconnect between the head and preamp. Conventional pulse-shaping circuitry used for this application uses high voltage to accomplish this task. Here, however, pulse-shaping circuitry is provided which can generate a similar waveform using lower voltage (i.e., about 5V) for this application and others.

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: A method adjusts a pulse width of a signal. The method provides a fixed voltage input trigger pulse (34), of a certain pulse width, to a pulse width generator circuit (10) and provides an output pulse (52) from the pulse width generator circuit such that a pulse width of the output pulse is longer than the certain pulse width, without changing a voltage or frequency of the input trigger pulse. The method is used to drive an injector of a diesel reductant delivery system to inject fluid into an exhaust flow path.

Abstract: A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

Abstract: A signal control device controls the period of a three-phase signal used to control a three-phase high-voltage converter. An arithmetic unit of the signal control device determines a timing for changing the period for each phase so that the period of the signal for a V phase or a W phase is changed at the point when the phase difference between a U phase and the V or W phase reaches a prescribed phase difference after the period of the signal for the U phase has been changed. A control unit performs control such that the signal period for each phase is changed at the timing determined by the arithmetic unit.

Abstract: A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator. The method further comprise starting a system clock counter and counting pulses of the ring oscillator until the system clock counter reaches a programmed value. The method also comprises determining whether a number of counted ring oscillator pulses is between lower and upper count thresholds and changing the number of delay elements for the ring oscillator as a result of the number of counted ring oscillator pulses being less than the lower count threshold or greater than the upper count threshold.

Abstract: In one embodiment a dozer blade controller, which may comprise two-way, four-way, or six-way dozer blade position control such as, for example, a two-way control only for blade tilt. In one embodiment, a pulse width control is provided for use in a blade tilt electronic controller, which controls blade tilt independently of movement of the body of the bull dozer. And in another embodiment, a pulse width controller is operable to multiply and/or divide the width of a variable pulse by a preset multiplier factor or divider factor, e.g. by 100 or dividing by 100.

Abstract: A first capacitor is arranged such that the electric potential at a first terminal is fixed. A first discharging circuit discharges the first capacitor at a timing that corresponds to a cyclic synchronization signal received from an external circuit. A first comparator compares the voltage at a second terminal of the first capacitor with a predetermined threshold voltage, and generate a judgment signal that corresponds to the comparison result. A charging circuit generates a charging current the current value of which is adjusted according to the level of the judgment signal at a timing that corresponds to the synchronization signal, and supplies the charging current thus generated to the first capacitor.

Abstract: A “quasi-master-time-base” circuit is used to periodically resynchronize the individual PWM generators to a know reference signal. This quasi-master-time-base will be at the lowest frequency relative to all of the PWM output frequencies, wherein all of the PWM output frequencies are at the same frequency or at an integer multiple frequency(ies) of the quasi-master frequency. This “quasi-master-time-base” circuit allows for minor timing errors due to user PWM configuration errors and/or update errors, and still yields stable PWM signal outputs that remain synchronized to each other.

Abstract: A clock adjustment circuit includes: first and third switching elements to be in a conductive state when in-phase and reverse-phase clock signals in a high level are applied to input terminals, respectively; second and fourth switching elements whose input terminals are connected to output terminals of the first and third switching elements, respectively, which become in the conductive state when the in-phase and reverse-phase clock signals in a low level are applied to output terminal, respectively; first and second capacitor elements whose one terminal is connected to an output terminal of the first and third switching element, respectively; and a shift detection unit detecting potential difference between the output terminals of the first and third switching elements and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.

Abstract: A digital pulse width modulation (PWM) controller is used for controlling the operating voltage of an electrical load and includes a setting module, a storage module and a control module. The setting module generates control parameters corresponding to different preset load currents and load voltages of the electrical load. The storage module stores the control parameters and the prestored load current and load voltage. The control module is in electronic communication with the storage module, and detects current load voltage and current load current of the electrical load, and compares the current load voltage and load current with the prestored load voltage. Thus, the control module can output the control parameters which are necessary to stabilize the operating voltage of the electrical load, by comparison with stored data.