Abstract: According to an embodiment of a time to digital converter, the time difference between a signal of interest and a reference signal is measured by operating a digitally controlled oscillator at a first frequency during a first portion of the reference signal period and changing the operating frequency from the first frequency to a second frequency during the reference signal period as a function of the time difference between the signal of interest and the reference signal. The time to digital converter continuously counts how many signal transitions occur at an output of the digitally controlled oscillator during the reference signal period. The time difference between the signal of interest and the reference signal is estimated based on the number of signal transitions counted during the reference signal period.

Abstract: A new method for transmitter-receiver design that enhances the desired signal output from the receiver by whitening the total interference and noise input to the receiver and maximizing the output Signal to Interference plus Noise power Ratio (SINR) is presented. As a result of the whitening process, the receiver “sees” a desired signal in white noise, and the receiver structure is then optimized to maximize the receiver output at the desired decision making instant. Furthermore the new design scheme proposed here can be used for transmit signal energy and bandwidth tradeoff. As a result, transmit signal energy can be used to tradeoff for “premium” signal bandwidth without sacrificing the system performance level in terms of the output Signal to Interference plus Noise power Ratio (SINR).

Abstract: A semiconductor device includes a first switching device including a first electrode coupled with a first node, a second electrode coupled with a second node, and a first control electrode controlling connection between the first and second electrodes; a second switching device including a third electrode coupled with the second node, a fourth electrode coupled with the second node, and a second control electrode controlling the connection between the third electrode and the fourth electrode; and a first control circuit controlling a substrate voltage of the second switching device.

Abstract: A new method for transmitter-receiver design that enhances the desired signal output from the receiver while minimizing the total interference and noise output from the receiver at the desired decision making instant is presented. Further the new design scheme proposed here can be used for transmit signal energy and bandwidth tradeoff. As a result, transmit signal energy can be used to tradeoff for the “premium” signal bandwidth without sacrificing the system performance level in terms of the output Signal to Interference plus Noise power Ratio (SINR). The two designs—the one before and the one after the tradeoff—will result in two different transmitter-receiver pairs that have the same performance level. In many applications such as in telecommunications, since the available bandwidth is at premium, such a tradeoff will result in releasing otherwise unavailable bandwidth at the expense of additional signal energy.

Abstract: An apparatus and method for the analysis of a periodic signal. One embodiment provides signal values. Signs are assigned to the signal values. The signed signal values are summed to a first sum. At least one signal property is determined on the basis of the first sum.

Abstract: A system and method for generating alert signals in a detection system is described. The system compares data extracted from signals received via receive antenna beams with stored scenarios and determines whether to generate an alert signal based upon the results of the compare operation. The comparison of data extracted from received signals with stored scenarios can be accomplished by using one or more latches to process the extracted data from the received signals. In one embodiment, raw detections are pre-processed to generate so-called field of view (FOV) products. The FOV products are then provided to a tracker. In another embodiment, rather than pre-process the raw detections, the raw detections are instead provided directly to a tracker which processes the raw detections to provide products including, but not limited to, relative velocity and other parameters.

Abstract: Disclosed is an apparatus and method for estimating a start point of a frame in a wireless communication system. The method includes the steps of receiving a frame and estimating the start of the frame by searching for an interval or point of time during or at which a correlation between preambles is at its maximum. At this time, to in order to estimate the start of the frame, a cyclic prefix is used. Thus, a correlation between a cyclic prefix and the last interval of a symbol, which is the same as the cyclic prefix, is calculated and an interval or point of time having the maximum correlation is estimated as the start point of the cyclic prefix. Therefore, the start point of the frame can be accurately estimated based on the start point of the cyclic prefix.

Abstract: The present invention involves an electrical system in which an analog signal channel passes through various integrated circuit chips (ICs). The channel can carry one or more analog signals. Each IC can modify the signal(s) passing through it and pass it on to another IC or system component. The channel can be programmable. Each IC can include a comparator or a multiplexor to receive the channel signal from another IC or system component and to modify the received signal before transmitting it to another IC or system component. The comparator or the multiplexor can be programmable and can be selectively configured to compare the incoming signal from the channel with a variety of other signals and thresholds, or to simply act as a flow through gate and allow the signal to pass without any modification. The comparison can determine the output of the comparator.

Abstract: When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Abstract: A method is presented for packet detection and symbol boundary location using a two-step sign correlation procedure. When the correlation crosses a threshold, a packet detection signal is generated to initiate processing of downstream blocks, and a symbol boundary location signal is generated for use in aligning data during processing.

Abstract: Disclosed is a wireless communication apparatus and method for a multiple transmit and receive antenna system using multiple codes. In suggested detection algorithm, a successive interference cancellation (SIC) scheme is employed in both an antenna domain and a code domain by successively canceling multi-code interference (MCI). An effective transmit power allocation method suitable for the detection algorithm is suggested. Transmit power allocated to each code is calculated. The transmit power is determined as a simple ratio of power of a certain signal to power of a next code signal. Based on the calculated code transmit power, transmit power for each transmit antenna is allocated. Thus, information about transmit power calculated at a receive end is feedback to a transmit end through a feedback channel.

Abstract: A method of detecting a trigger event comprises receiving an input signal for analysis. The received input signal is used to generating first data corresponding to energy of a frequency content of the input signal as the input signal changes with time. At least part of the first data is then compared with second data, the second data corresponding to a predetermined time-varying spectrum indicative of the trigger event. A trigger signal is then generated in response to a change in a state of match between the at least part of first and the second data.

Abstract: A differential pair circuit includes a first transistor having a first control terminal, a first input terminal, and a first output terminal; a second transistor having a second control terminal, a second input terminal, and a second output terminal, a first buffer stage including a third transistor having a third control terminal, a third input terminal, and a third output terminal; and a second buffer stage including a fourth transistor having a fourth control terminal, a fourth input terminal, and a fourth output terminal. The first output terminal and the second output terminal are electrically connected; the third output terminal and the first control terminal are electrically connected; the fourth output terminal and the second control terminal are electrically connected; the first input terminal and the fourth input terminal are electrically connected; and the second input terminal and the third input terminal are electrically connected.

Abstract: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Abstract: A clock and data recovery unit for recovering a received serial data bit stream having: phase adjustment means for adjustment of a sampling time in the center of a unit interval of the received data bit stream, wherein the phase adjustment means comprises means for generating equidistant reference phase signals, a phase interpolation unit, an oversampling unit, a serial-to-parallel-conversion unit, a binary phase detection unit, and a loop filter; and data recognition means for recovery of the received data stream which includes a number of parallel data recognition FIR-Filters, wherein each data recognition FIR-Filter comprises a weighting unit, a summing unit, and a comparator unit.

Abstract: An apparatus comprising a comparator circuit, a reference circuit, a plurality of elements and a logic circuit. The comparator circuit may be configured to generate a difference signal in response to (i) a reference signal and (ii) a test signal. The reference circuit configured to generate the reference signal in response to a first control signal. The plurality of elements may each be configured to generate an intermediate test signal. One of the intermediate test signals may be presented as the test signal by activating one of the test elements, in response to a second control signal. The logic circuit may be configured to generate (i) the first control signal and (ii) the second control signal, each in response to the difference signal.

Abstract: A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Abstract: A clock detection and selection circuit (100) can include a first counter (102-0) that generates a first count value CNT1 according to a first clock signal CLK1 and a second counter (102-1) that generates a second count value CNT2 according to a second clock signal CLK2. First separation-detect logic (102-0) and second separation-detect logic (102-1) determine if a pre-specified difference exists between a first count value (CNT1/CNT1?) and second count value (CNT2/CNT2?). According to such determinations, separation information (INF—1 and INF—2) can be generated indicating which clock signal (CLK1 or CLK2) is faster. Selection logic (106) can select a faster of the clock signals (CLK1 or CLK2) if the separation information values confirm one another.

Abstract: A phase detector has a reference signal input for a reference signal and a detector input for a signal to be evaluated. A memory unit is connected to the detector input and stores a state of the signal to be evaluated at a storage instant. An evaluation unit is connected downstream of the storage unit and is designed in such a way that it can be used to compare the stored state of the signal with the state of the reference signal at an evaluation instant and to generate an evaluation result signal therefrom. The phase detector has a control unit for prescribing the storage instant and the evaluation instant, the control unit prescribing the storage instant first and then the evaluation instant. A detector output is connected to the evaluation unit and the evaluation result signal can be tapped off at the detector output.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Abstract: A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (?1a . . . (?na) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (?1a . . . ?na), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (?1u . . . ?nu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (?1a . . . ?na) depending on the sampling phases (?1u . . . ?nu) and said adjusting signal (AS).

Abstract: A radio communication system is comprised of: a transmitting system in which N transmission signals, frequency-converted to the same transmission frequency, are generated by N transmitters, N being an integer equal to or greater than 2, and the transmission signals are each applied to each one of N elements of an antenna for transmission; and a receiving system in which each transmitted signal is received by N-element antenna and the cross correlation coefficient between the transmitted signals received by the N-elements is minimized to thereby reconstruct each transmitted signal. The plural transmitted signals of the same frequency are received and the cross correlation coefficients of the received transmitted signals are minimized to thereby permit multiplexing of the transmission signal.

Abstract: An apparatus for and method of generating normalized soft decision information output from an inner decoder (i.e. equalizer) in a communications receiver. The invention is operative to normalize the soft decision information before it enters a soft outer decoder. The normalization is performed using a noise power estimate that is dynamically calculated in response to changing noise statistics on the channel. The normalized soft decision output is then applied to the soft outer decoder thus realizing maximum performance therefrom. The noise power estimate is derived from the training sequence and/or the data portion of the received signal. Both types of estimates are calculated. A binary or smoothly weighted average is calculated using both types of estimates. The weighting factor is determined based on one or more performance metrics, such as the Signal to Noise Ratio (SNR).

Abstract: A piezoelectric resonator is immersed in a liquid, an AC signal is applied, and a local maximum of the conductance is determined. A frequency change due to the viscosity effect is determined from two frequencies of three frequencies including a resonance frequency that is applied at that local maximum, and first and second half-value frequencies at which a half-value conductance of half that local maximum is given. The influence of the mass effect can be eliminated, so that an accurate measurement of the viscosity change is possible. Moreover, if the substance to be analyzed that is contained in the liquid adheres to a reaction film of the piezoelectric resonator, the mass of the piezoelectric resonator changes, and the second half-value frequency is measured. It is thus possible to derive only the influence of the mass effect, since the half-value frequencies are not influenced by the viscosity effect.

Abstract: A device for recognizing power sources and associated method are provided. The device for recognizing power sources comprises two voltage-dividing devices. Each of the voltage-dividing devices is coupled to receive native power, and outputs the part of the voltage of the native power. According to the method, an output end of one voltage-dividing device is coupled to a signal end of the controller, and an output end of the other voltage-dividing device is coupled to the other signal end of the controller. When the native power exists, both of the above-mentioned signal ends are in a high voltage level. On the other hand, when native power does not exists, both of the above-mentioned signal ends are at a low voltage level. The power source of the hardware device and the value of the native power can be exactly recognized according to the voltage levels of both signal ends.

Abstract: A structure and method for the improvement of interference isolation using distributed broadband technology. This structure uses signal processing across a distributed network in order to optimize the isolation of a signal of interest when noise, interference and crosstalk signal sources are present. The structure is designed so that a signal arrives at a node in the network via more than one path and is summed in a correlated or in-phase manner. Each signal path is designed so that the signal phase may be modulated to create the in-phase summing. Noise sources that arrive at the network node are added in an uncorrelated or out-of-phase manner. Therefore, the combination of the signal adding coherently and the interference adding with an uncorrelated phase improves the signal to interference ratio. This type of structure may be applied in an RF power amplifier application in order to provide an improved interference or crosstalk signal ratio.

Abstract: Clock switching circuitry includes a clock switching control circuit for temporarily storing a clock select signal, which is input from the outside for selecting one of a plurality of clock signals different in phase from each other. The clock switching control circuit then outputs the clock select signal in accordance with the change in the level of a timing signal that switches the clock signals. A clock output circuit outputs one of the clock signals selected in accordance with the clock select signal. A masking circuit generates the timing signal while masking it to a preselected level by taking account of changes in the levels of the clock signals.

Abstract: In a distance measuring apparatus 1 having a projector 10 that projects pulse light P outside and a light receiver 20 that receives the pulse light being reflected in the outside and performs photoelectric conversion, and outputting measurement data DL responsive to a time Tf from the transmission point of time to the reception point of time of the pulse light, the following are provided: determining means 311 for determining whether a received light waveform DP is correct or includes at least two incorrect waveforms based on an output signal SP of the light receiver 20; and warning data outputting means 312 for outputting warning data DE responsive to the result of the determination when the determining means 311 determines that the received light waveform DP is incorrect.

Abstract: Disclosed is a device that includes a built-in-self-test controller having a mechanism for providing an interface signal that indicates whether a dynamic voltage screen (DVS) test is being performed. The self-test controller is associated with a memory array that includes a clock having a clock speed. The memory array also includes a clock adjuster that receives the interface signal and reduces the clock speed when the interface signal indicates that a DVS test is being performed.

Abstract: A delay addressed data path register file is designed for use in a programmable processor making up a cell in a multi-processor or array signal processing system. The delay addressable register file is particularly useful in, inter alia, adaptive filters where the filter update latency is variable, interpolation filters where the interpolation factor needs to be programmable, and decimation filters where the decimation factor needs to be programmable. The programmability is achieved in an efficient manner, reducing the number of cycles required to perform this task. A single parameter, the “delay limit” value, is programmed at start-up, setting up an internal delay-line within the register file of the processor. Thus, any of the delayed registers can be addressed by specifying the delay index during run-time. The delay line advances one location, modulo “delay-limit”, when the processing loop starts a new iteration.

Abstract: A method for selectively assembling a molecular device on a substrate comprises contacting the first substrate with a solution containing molecular devices; impeding bonding of the molecular devices to the substrate such that application of a voltage potential to the substrate results in assembly of the molecular device on the substrate at a rate that is at least 1.5 times the rate of assembly of the molecular device on a voltage-neutral substrate; and applying a voltage potential to the substrate so as to cause the molecular devices to assemble on the substrate. More specifically, selective assembly can be obtained by providing a mixture comprising protected molecular devices in solution; removing protective groups from some of the molecular devices; activating the de-protected molecular devices; contacting the substrate with the solution; and allowing the activated devices to bond to the substrate such that the they assemble on the first substrate.

Abstract: A sensor has an emitting device for emitting radiation pulses repeatedly and a receiving device for receiving these pulses. The receiving device includes a converter such as a photoelectric converter to convert the received radiation pulses into electrical pulses. On the basis of a known waveform characteristic or characteristics of true electrical pulse it is judged if a pulse which appears on the output line of the converter is a true electrical pulse caused by receiving the radiation pulse emitted from the emitting device or a false electrical pulse caused by noise. The result of this judgment is outputted from an output device. The emitting device may serve to emit the pulses according to a specified bit pattern and the receiving device may serve to compare the pattern of received pulses with a standard bit pattern and to thereby distinguish between true and false electrical pulses.

Abstract: A waveform generating method is provided, which is capable of generating expressive musical tones. A plurality of partial waveforms are stored in a partial waveform memory. Property information on respective ones of the partial waveforms stored in the partial waveform memory is stored in a property information memory. The property information memory is retrived according to inputted sounding control information to read out a partial waveform having property information corresponding to the sounding control information. The readout partial waveform is processed according to the property information and the sounding control information, to generate a waveform corresponding to the sounding control information.

Abstract: A connection control circuit is provided to guarantee a high quality of port-to-port connection service by enabling to maintain the suspended state even when a disparity exists in the pulse widths of the envelope signals of the tone signals between the sender and receiver, exemplified by a receiver tone pulse width being wider than a sender tone pulse width. Connection control is achieved by providing a signal correction circuit between the receiver circuit of a port that receives incoming signals from an opposing port through a transmission line and a connection state managing machine that manages connection between the ports. The signal correction circuit corrects the tone pulse width of an envelope-signal generated from the incoming tone signal by broadening the pulse width so as to conform to a tone signal having the pulse width specified by own connection state managing machine.

Abstract: An integrated circuit is described which is distinguished by the fact that there is integrated in it an RF filter device which can prevent or restrict the propagation of high-frequency interference signals through lines carrying DC voltages or low-frequency voltages. As a result, interference with the operation of the integrated circuit and/or of other integrated circuits or of other components of the system containing the integrated circuit can be prevented in a very simple yet extremely effective manner.

Abstract: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to exceed a maximum power consumption value of the semiconductor integrated circuit device by considering the power consumption of each circuit block and by each state transition in each circuit block. The maximum power consumption value may be preset or adjustable after fabrication.

Abstract: An integrated CMOS semiconductor circuit comprises: an internal circuit composed of CMOS transistors including P- and N-channel transistors each having a gate electrode and source/drain regions formed on a semiconductor substrate, the internal circuit functioning in at least two states including an active state in which data is input and output, and a standby state in which a state of the internal circuit is maintained; an external circuit composed of any electrical element and provided with a power source; and a switch portion which is enable to apply, in the standby state in the internal circuit, a reverse bias between the source and the substrate of either one of the P- and N-channel transistors of the internal circuit by the power source of the external circuit.

Abstract: A time delay from a triggering event to switching of an output signal in a microelectronic device can be adjusted to compensate for various characteristics of the electronic device. The characteristics include temperature, voltage, and manufacturing process conditions. The time delay is adjusted using a variable delay circuit having multiple delay cells that are selectively coupled to control the time delay. The conditions of the electronic device are detected using a process sensor, which includes an oscillator having a frequency that is sensitive to variations in the conditions.

Abstract: A read-only sequence controller has a master circuit mounted on a housing and having a first presettable counter for producing an instruction pulse, and a slave circuit having a second presettable counter for setting a cycle, and a pules the generating circuit for producing a plurality of pulses at the cycle in response to the instruction pulse from the master circuit. An EPROM is provided for storing a machine operating program data and for producing a program data in response to the pulses fed from the slave circuit. There is provided a plurality of output relays operated in accordance with the program data fed from the EPROM, and a plurality of terminal connected to the relays. The output terminals are arranged in two rows at one of sides of the housing.

Abstract: A phase comparator apparatus compares a first input signal and a second input signal to output first or second compare output signal. The apparatus includes a detector circuit and a compare output generator circuit. The detector circuit detects the phase difference between the first and second signals to output a detection signal. The compare output generator circuit determines the phase deviation between the first and second input signals using the detection signal and the second input signal. The compare output generator circuit outputs the first compare output signal when the second input signal lags behind the first input signal and outputs the second compare output signal when the second input signal leads the first input signal.

Abstract: A selectable reference voltage circuit for a digital-to-analog converter (DAC) which includes an input terminal for receiving an external reference voltage, a voltage comparator having two inputs and an output, one input for receiving the reference voltage and the other for receiving a predetermined voltage, the comparator providing one of two possible output voltages based upon the relationship of the magnitudes of the reference voltage and the predetermined voltage. The circuit includes a multiplexer having a control input coupled to receive as an input signal the output of the comparator, and having two inputs for receiving input voltage signals, one for receiving the voltage on the reference voltage input terminal and the other for receiving an on-chip generated reference voltage, the multiplexer selecting as an output voltage one of the two input voltages determined by the input signal at its control input.

Abstract: There is disclosed an information processing apparatus, such as a printer, capable of selectively using plural control programs by utilizing an external memory, such as a program cartridge, containing additional programs. When a switching of control program is requested for example by a switch, the start address of the requested program is indirectly obtained by referring to a fixed address of the memory cartridge containing the requested program.

Abstract: A frequency discriminator circuit that includes a signal shaping and power splitting circuit (20) responsive to a sinusoidal RF input signal for providing first and second substantially identical squarewave outputs having the same frequency as the sinusoidal RF signal, a digital delay line (19) responsive to the first squarewave output for providing a delayed replica of the first squarewave output, an exclusive OR gate (21) responsive to the second squarewave output and the delayed replica of the first squarewave output, low pass filters (23, 25) for averaging each of the inverted and non-inverted outputs of the exclusive OR gate, and a differential amplifier (27) for subtracting the outputs of the low pass filters from each other and providing an output indicative of the frequency of the RF input signal.

Abstract: A system and method for estimating input phase for bit cells recovered from run length limited code where the bits cells have a nominal duration allows use of sampling rate as low as the nominal data rate in an all digital phase-locked loop. For the all digital phase-locked loop, a clock generates sample cells of a fixed duration. The sample cell phase contribution corresponding to a proportion of the fixed duration to the nominal duration is calculated and added to an accumulated phase value with each successive sample cell. For each sample cell, an input phase estimate is made from the accumulated phase value and timing information for any bit cell event occurring within the sample cell. Finally the input phase estimate information is used to adjust an accumulated phase value for the next sample cell.

Abstract: A plurality of address transition detecting circuits incorporated in a semiconductor memory device monitors address bits to see whether or not at least one address bits is changed in logic level for producing an address transition signal from the output signals of the respective address transition detecting circuits, and a plurality of charging transistors coupled in parallel between a power voltage line and a decoding line are respectively gated by the output signals of the address transition detecting circuits for charging the decoding line so that a decoding circuit quickly determines whether or not the stored address is matched with the address represented by the address bits for replacing a defective row of regular memory cells with a row of redundant memory cells.

Abstract: An integrated circuit testing device, including a small test signal generator for generating a small test signal having a small amplitude corresponding to a test signal supplied to an input terminal of a target integrated circuit to be tested; a test signal supply circuit for amplifying the small test signal generated from the small test signal generator to obtain the test signal having a predetermined power and timing, and for supplying the test signal to the input terminal of the target integrated circuit to be tested; and a controller for setting a rise time of the test signal and a fall time of the test signal at a predetermined time by adjusting the amount of power of the test signal supplied from the test signal supply circuit.

Abstract: An apparatus and method for determining a time that a system's main power was inactive includes a counter circuit (171) for accumulating transitions of a clock signal (149) while the system's main power (117) is inactive. Preferably, another circuit (159, 125) determines a periodicity of the clock signal (149) after the system's main power (117) transitions active. Then a computational circuit, preferably a microcontroller (129), determines the time (183) that the system's main power (117) was inactive dependent on a number of transitions of the clock signal (149) accumulated by the counter circuit (171) when the system's main power (119) was inactive and the determined periodicity of the clock signal (149) after the system's main power (117) transitions active. Preferably, this apparatus and method are used in a vehicle to determine how long a time that an engine is turned off and to modify an engine control strategy dependent on that determined time.

Abstract: A digital data propagation delay margin monitoring circuit that includes (a) a digital data propagation unit having a send flip-flop, a combinatorial delay, and a receive flip-flop; and (b) a margin detection circuit having a test flip-flop that receives the same input as the receive flip-flop and is configured to have a set up time margin or a hold time margin that is less than the set up margin or hold time margin of the receive flip-flop by a predetermined amount, depending upon which margin is being monitored. The outputs of the receive flip-flop and the test flip-flop are compared by a comparison circuit which provides an indication of when the outputs of the receive flip-flop and the test flip-flop are different, which indicates that the monitored margin of the receive flip-flop has been reduced to a predetermined margin or less.

Abstract: A circuit for detecting the transition of the state of logic signals at a plurality of input terminals is provided. The circuit has a transition detecting block connected to each input terminal which generates a pulse at the transition of a logic signal at the input terminal, an OR logic block connected to each transition detecting block for generating a combined logic signal from the transition detecting blocks, and a latch having SET and RESET input nodes and an output node. The SET input node is connected to the OR logic block so that the output node switches into a first logic state from a second logic state responsive to the combined logic signal on the SET input node. The circuit also has a delay unit connected to the OR logic block and to the RESET input node of the latch which precisely delays the combined logic signal to the RESET input node so that the output node of the latch switches back to the second logic state.