Abstract: A delay locked loop (DLL) that applies an amount of delay to an external clock signal to generate multiple delayed signals. One of the delayed signals is selected as an internal clock signal. The multiple delayed signals have different delays in relation to the external clock signal. If a change in operating condition of the DLL occurs, such as a change in the supply voltage during an operational mode of the memory device such as an ACTIVE, a READ or a REFRESH mode, the DLL immediately selects another delayed signal among the multiple delayed signals as a new internal clock signal to compensate for the change before a phase detector of the DLL detects the change.

Abstract: A circuit, for use in a delay locked loop, provides a phase-shifted output relative to a first signal. The circuit includes plural current sources, current source switches that are selectable to transmit varying amounts of current from the plural current sources, and input switches that receive current via the current source switches and provide the phase-shifted output. The output switches include a first switch for receiving the first signal and a second switch for receiving a second signal phase-shifted from the first signal. The phase-shifted output relative to the first signal is based on an amount of current that passes through each input switch.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to hold, at a selected time during the signal epoch of the respective sinusoidal signals, phase values of the sinusoidal signals. The respective phase values are coupled to an infinite track-and-hold circuit to generate replicas of the phase values. The phase values and the replica phase values are coupled to respective multiplexers that selectively couple the phase values to multipliers during a first time period and replica phase values during a second time period. The output of each multiplexer is coupled to a multiplier that receives one of the phase shifted continuous sinusoidal signals. The output of the multipliers are summed in a summing circuit to generate an output signal with a predetermined stable startup phase relative to the transition.

Abstract: The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to output data to a data output. In addition, the integrated circuit has a control unit generating the internal clock signal from the external clock signal. The control unit has a phase shift unit that, in the normal mode of operation, effects a phase shift of the internal clock signal generated by the control unit with respect to the external clock signal. In addition, the integrated circuit has a detector unit determining the capacitive load on the data output. The detector unit supplying the phase shift unit with a corresponding detector signal on the basis of which the phase shift is set.

Abstract: A phase interpolator that receives input clock phase and selection inputs that are distinct from the input clock phases. The phase interpolator generates an output clock phase based on the selection inputs. The phase interpolator includes selector devices which receive the input clock phases and receive the selection inputs, and includes cross-coupled switches which are connected to the selector devices and receive input clock phases therefrom. The selector devices select which input clock phases to provide to the cross-coupled switches based upon the selection inputs. The cross-coupled switches generate the output clock phase based upon the input clock phases which are received from the selector devices.

Abstract: A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

Abstract: A control method and system are used for signal transmission when a data signal is transmitted between two circuits on the basis of a reference clock in a system. The sending side circuit transmits a clock signal together with the data signal to a clock transmission line of the same course with a data transmission line for the data signal by using a sender side reference clock. The receiving side circuit adjusts phases of the clock signal and the data signal at input points of transmission lines respectively so as to be in accordance with a receiver side reference clock. Then the receiving side circuit reads out data from an adjusted data signal by using an adjusted clock obtained by above the aforementioned adjusting step. The adjustment is performed comparing a phase of an adjusted clock with a phase of the receiver side reference clock. The second adjustment involves generating a feedback clock signal including a phase difference between the above signals.

Abstract: Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively.

Abstract: The integrated circuit has a clock input for an external clock signal and an output unit controlled by an internal clock signal in a normal mode of operation to output data to a data output. In addition, the integrated circuit has a control unit generating the internal clock signal from the external clock signal. The control unit has a phase shift unit that, in the normal mode of operation, effects a phase shift of the internal clock signal generated by the control unit with respect to the external clock signal. In addition, the integrated circuit has a detector unit determining the capacitive load on the data output. The detector unit supplying the phase shift unit with a corresponding detector signal on the basis of which the phase shift is set.

Abstract: A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

Abstract: A synchronous integrated circuit clock circuit is disclosed. The clock circuit (200) receives a system clock (CLKX) and in response thereto, generates an internal clock (CLKI) that is shifted forward in phase with respect to the system clock signal (CLKX). The amount by which the internal clock (CLKI) is shifted remains relatively constant over a range of system clock (CLKX) frequencies. The clock circuit (200) includes a measuring section (202) that measures the period of the system clock (CLKX), a logic section (204) that determines a delay value based upon the duration of the system clock (CLKX) period, and a generation section (206), that provides the internal clock signal (CLKI).

Abstract: A phase shifter that may be used in a quadrature modulator or an image suppression mixer. The phase shifter includes a low pass filter that receives an input signal and generates a first carrier signal. A high pass filter also receives the input signal and generates a second carrier signal. A phase difference detection circuit connected to the high and low pass filters receives the first and second carrier signals and generates a control signal based on the phase difference between the carrier signals. The control signal is fed back to at least one of the low pass filter and the high pass filter to compensate for phase errors caused by parasitic capacitance. The phase shifter has a small circuit area and is very accurate, allowing it to be used in communications devices.

Abstract: The present invention relates to, more specifically, an electronic circuit apparatus having a main system portion and a subsystem portion connected to the main system portion. In the electronic circuit apparatus, at least either the main system or the subsystem comprises a clock source, a clock wire having an outgoing path and an incoming path, wherein a clock signal from the clock source is inputted from one end of the outgoing path, and at least one receiver connected to an optional position of the outgoing path, further connected to a position of the outgoing path adjacent to the optional position, for supplying a clock signal having an optional delay level relative to the clock signal from the clock source according to a delay level between each clock signal at the positions.

Abstract: A semiconductor integrated circuit device has a plurality of functional blocks. Each of the plurality of functional blocks comprises a DLL circuit for outputting a clock signal, at least one wiring portion for receiving the clock signal at one end thereof, and at least one load circuit for receiving the clock signal from the DLL circuit via the wiring portion. The DLL circuit receives a reference clock signal and a wiring portion and outputs the clock signal so that the phase difference between the reference clock signal and the second clock signal is a predetermined value. Thus, clock skew is reduced even if there is variation due to process.

Abstract: A frequency conversion or synthesis circuit including a double balance differential active ring mixer with a current shared active radio frequency (RF) input balun, suitable for use in an RF receiver. The circuit is configured to be coupled to a bias circuit for providing a relatively constant current and a buffer circuit for receiving a signal from a local oscillator (LO) source and generating differential LO signals.

Abstract: A phase lock loop circuit. The phase lock loop circuit includes first and second pass gates. The pass gates include signal inputs that receive first and second reference signals, respectively. The pass gates also have enable inputs. The phase lock loop also includes a loop filter that is coupled to the outputs of the first and second pass gates. A loop oscillator is coupled to the output of the loop filter. A strobe circuit is coupled to the output of the loop oscillator. The strobe circuit provides an input signal to the enable inputs of the first and second pass gates so as to sample the first and second reference signals. The loop filter uses the samples of the first and second reference signals to create a control signal that forces the loop oscillator to output a signal with a phase that is between the phases of the first and second reference signals.

Abstract: Apparatus and method for aligning signal transition edges in high-speed complementary metal-oxide-semiconductor (CMOS) integrated circuits and other electronic circuits, systems and devices. A transition edge alignment circuit in accordance with the invention includes first and second inverter chains, each having a plurality of series-connected inverters. A first signal, which may be a digital logic signal, is applied to an input of the first inverter chain. A second signal, which may be a clock signal used to latch the logic signal in an integrated circuit, is applied to an input of the second inverter chain. The inverter chains may be constructed such that the inverters of the second chain have a stronger drive capability than the corresponding inverters of the first chain. Capacitive coupling is provided between outputs of inverters of the first chain and outputs of corresponding inverters of the second chain.

Abstract: An active phase splitter comprises two or more phase shift circuits. Each phase shift circuit comprises a number of active devices and capacitors. For a single-pole active phase splitter, within each phase shift circuit, two active devices are configured as a cascode amplifier. The first active device is configured as a common source amplifier and the second active device is configured as a common gate amplifier. A capacitor is connected across the gate and drain of the first active device to generates the necessary pole-zero pair for the phase shift circuit. The cascode configuration results in the desired transfer function and provides transconversion of voltage input to current outputs. Active phase splitters with two or more poles can be built using the same inventive concept.

Abstract: A clock timing recovery circuit for recovering the clock timing from a baseband signal obtained by detection of a received signal. The clock timing is rapidly established using a clock signal which has been phase-shifted from the desired clock timing to sample the baseband signal, and by obtaining the optimum phase from the sampled signal obtained as a result. A clock-timing recovery circuit according to this invention does not require oversampling and provides easy optimization of circuit constants.

Abstract: An apparatus for electrical line communications using FM video modulation, includes FM video modulation circuits and an impedance matching coupler at each of two or more locations along a pair of lines. The impedance matching couplers provide impedance matching, utilizing an air-core preselected frequency bands, sufficient to allow low-loss transmission of frequency modulated video signals. The coupler further eliminates noise and is matched resistively to the characteristic impedance of the line at the preselected frequency bands. A transmitter, receiver and associated circuits may also be provided at each location along the lines. The FM video modulation circuits, in combination with phase linear coupling techniques, provide for hi-fidelity video transmission over existing electrical lines, such as residential AC power wiring. In addition, a coupler with solid state impedance matching is provided.

Abstract: The present invention provides a method of and an apparatus for producing an output signal which is, relative to a periodic input signal, delayed by a predetermined phase angle phi. Initially, the phase angle phi between 0 and 2.pi. is divided by 2.pi. and multiplied by a predetermined positive integer number Z, whereby an integer phase number F between 0 and Z in obtained after rounding. Then, timing-pulse are, beginning with zero, counted between a first and a second input pulse, and an integer relative phase number P is obtained from the number N of the timing-pulses by multiplying by the phase number F, dividing by Z and rounding. Following the second input signal, the timing pulses are, beginning with zero, counted until the relative phase number P in reached. At last, an output pulse is emitted upon reaching the relative phase number P.

Abstract: An object of the invention is to provide a variable delay circuit having a desired optional resolution.A variable delay section 24 is provided with paths A and B which carry signals input to an input terminal 21 to an output terminal 22, and a selection section for switching the paths A and B in accordance with a select signal. Ring oscillators 25 and 29 have oscillation periods which are x times and y times the delay time of the respective paths A and B. Phase comparison circuits 27 and 31 respectively compare, the phase of a first clock signal and the output from the ring oscillator 25, and the phase of a second clock signal and the output from the ring oscillator 29. Delay time control circuits 28 and 32 then respectively control the oscillation periods of the ring oscillators 25 and 29 so as to be equal to the respective periods of the first clock signal and the second clock signal, based on the phase comparison results, and control the delay times of the paths A and B.

Abstract: The timing signal output from a subject circuit is accurately skewed relative to a base clock signal period. A phase-locked loop ("PLL") and sample delay circuit are implemented with the subject circuit. The PLL receives the base clock signal and generates a local clock signal. The local clock signal is input to a sample delay circuit and the subject circuit. The sample circuit generates a delay approximating that of the subject circuit. The output of the sample delay circuit is fed back into the PLL. With the base clock as the PLL's reference signal and the delayed signal as the feedback signal, the local clock signal phase is forced to precede the base clock phase by the propagation delay of the sample delay circuit. In effect, the propagation delay is nulled out. For a PLL generating multiple output phases a zero phase goes to the sample delay circuit and an output with a phase corresponding to a desired skew goes to the subject circuit.

Abstract: A clock signal distributing system supplies clock signals exhibiting extremely matched phases as a standing wave without employing extra signals such as a reference signal and the like other than clock signal itself. The system compensates for a phase lag in clock signal sand attenuation in signal amplitude. As a result, clock signals exhibiting extremely matched phases are supplied up to the places to be distributed at the respective terminals without requiring equal-length wiring on, for example, a semiconductor chip. The clock signal distributing system is composed of an electromagnetic transmission path line which transmits periodic clock signals as a standing wave, an amplifier, and a phase advancing unit which advances phases of the periodic clock signals wherein a phase lag in transmission of clock signals and a phase lag in amplitude of the amplifier are corrected in the phase advancing direction by the phase advancing unit.

Abstract: A signal processing apparatus is provided for processing first and second periodic analog signals having the same period and having a fixed phase relationship therebetween. The apparatus includes an A/D converter for converting respective amplitudes of the first and second periodic analog signals into first and second digital signals. The apparatus also includes a phase digitizer for generating a signal from the first periodic analog signal, the generated signal having a period that is shorter than the period of the first periodic analog signal, and a high speed signal processing portion for generating from the generated signal a periodicity and first phase information of the first periodic analog signal. The apparatus further includes a another signal processor for producing second phase information of the first periodic analog signal from the first and second digital signals, and for correcting the periodicity on the basis of the first phase information and the second phase information.

Abstract: A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used.

Abstract: A clock deskewing apparatus uses either a series terminated single transmission line system or a Thevenin terminated dual transmission line system to deliver a clock signal to a load. A plurality of series terminated clock deskewing apparatuses are implemented, one for each load, so that the clock signal is delivered to all loads coupled to the clock signal simultaneously. Each series clock deskewing apparatus has a single termination resistor with the same impedance value as the transmission line that it is coupled to. Each Thevenin termination system has a voltage divider resistor network. A variable delay line within each series clock deskewing apparatus can be adjusted so that each load receives the clock signal at the same time. A programmable output driver impedance network can be used for the single line termination resistor of the series terminated clock deskewing system in order that the series terminated clock deskewing apparatus can be used with transmission lines having different line impedances.

Abstract: An incremental phase shifter for digital signals adapted to combine weighted amount of two quadrature square waves so as to generate a wave having a phase intermediate the respective phases of the two quadrature square wave signals. The generated wave is then processed in a limiting and integrating circuit so as to produce a square wave which is linearly related to the assigned weighted amounts of the two quadrate square waves.

Abstract: The present invention relates to a method for sampling an analog, periodic, measured signal, which is subject to a phase jitter. The misread signal is to be detected with a prior event. One measured value is recorded for each individual signal and each successive measured value recording is delayed by a time unit in which each measured value recording takes place in a fixed time grid with a prior event, and in which the point in time of the start of the signal is detected in the time grid and is stored, assigned to the recorded measured value.

Abstract: A data communication receiver (10) uses a decision feedback demodulator (32) to remove data from a received signal. Quadrature components of the received signal define a received phase. The received phase is rotated (46) by an amount predicted to compensate for phase and frequency errors. After this rotation, a decision circuit (52) determines the modulation phase for a current symbol. A phase rotator (64) compares the modulation phase with the received phase to generate a measured phase error for the symbol. This measured phase error and measured phase errors from past symbols are averaged in a combination circuit (80) to produce a phase estimate. The past measured phase errors are also processed to determine the amount of change in measured phase error that has occurred over a number of symbols. This processing yields a frequency estimate. A phase rotator (94) merges the frequency and phase estimates for use in compensating a current received phase.

Abstract: In a sampling phase controlling apparatus for controlling a phase of a clock signal supplied to a transmission system including a discriminating circuit for discriminating a received signal and an equalizer for removing an intersymbol interference component from the received signal, a first phase control circuit is provided to control the phase of the clock signal in accordance with accumulated intersymbol interference components, and a second phase control circuit is provided to control the phase of the clock signal in accordance with the accumulated intersymbol interference components and a differential value thereof. One of the first and second phase control circuits is selected by a selector circuit.

Abstract: A method of compensating a phase of a system clock for use in a system clock circuit for receiving an external clock to produce a system clock for an information processing system, in which the quantity of phase variation of the external clock supplied from a reference clock oscillator provided outside the system is detected; in accordance with the detected quantity of phase variation, the phase variation of the external clock supplied from the reference clock generator is compensated to supply the compensated external clock to the system clock circuit; whether or not a state of the external clock supplied from the reference clock oscillator provided outside the system is abnormal is detected; and in accordance with the detected state of the external clock, one of the external clock supplied from the reference clock oscillator and the compensated external clock is selected to supply the selected external clock to the system clock.

Abstract: A digital frequency generating device is comprised of a first digital frequency generator which generates a first output signal at a first frequency and a second digital frequency generator which generates a second output signal at a second frequency independent of the first frequency. Both the first and the second frequency generators run continuously and either can be connected to the generating device output by means of a multiplexer. Apparatus is provided to synchronize the two generators so that a continuous phase transition is maintained when the generating device output switches from the first output signal to the second output signal. This arrangement allows the device output to be shifted from a first frequency to a second frequency and then return to the first frequency output while maintaining the phase position of the first frequency output and is particularly useful in nuclear magnetic resonance applications.

Abstract: A bit clock regenerating circuit comprising an edge detector made up of two flip-flops for detecting edges of a binary signal and a gating circuit, a counter receiving an edge detected pulse from the edge detector as a load signal for setting an initial value, counting clock pulses with a given frequency, and generating a bit clock according to the result of the counting, and a ROM in which multiple conversion tables are formed to supply an initial value for the counter according to an output value of the counter, and a conversion table for determining regeneration conditions is selected according to a switching signal.

Abstract: A circuit for generating a pair of quadrature output signals from a pair of quadrature input signals in which the frequency of the output signals is double that of the input. The circuit consists of two dual phase shifters, two symmetrical multipliers and a phase controller. The circuit is fabricated by conventional integrated circuit processing technology. A method of generating frequency doubled quadrature output signals is disclosed.