Abstract: A method includes, in at least one aspect, selecting a first phase signal, where the first phase signal concurrently enables a first pair of switching elements; selecting a second phase signal, where the second phase signal concurrently enables a second pair of switching elements; and generating an interpolated phase signal by providing a connection between a switching element of the first pair of switching elements to an output node and providing a connection between a switching element of the second pair of switching elements to the output node.

Abstract: A method for providing an interpolated output signal includes, in at least one aspect, receiving a plurality of phase signals applying each phase signal of the plurality of phase signals to switching elements of a first set of switching elements receiving a plurality of select signals, applying an asserted select signal to a first switching element of a second set of switching elements to provide a connection between a first switching element of the first set of switching elements and a first output terminal, and applying the asserted select signal to a second switching element of the second set of switching elements to provide a connection between a second switching element of the first set of switching elements and a second output terminal.

Abstract: A phase interpolator is provided that, in one implementation, includes first and second interpolator modules, each having an output in communication with an output node. The first interpolator includes an input to receive a first plurality of input phase signals, and a selector to select one or more of the first plurality of input phase signals for interpolation at the output node of the phase interpolator. The second interpolator module includes an input to receive a second plurality of input phase signals, and a selector to select one or more of the second plurality of input phase signals for interpolation at the output node of the phase interpolator. Each of the selected ones of the first plurality of input signals and each of the selected ones of the second plurality of input signals are included in an interpolated output signal.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: In order to provide a more flexible adjustment of signal delay times in a circuit configuration containing a line device and a number of electronic components accessing it, it is proposed to add additional capacitances, which can be varied in a controllable manner. In addition, the capacitances are to formed in a region of the existing components.

Abstract: A phase shift circuit includes a CR phase shifter for receiving an input signal to output a pair of first signals having a 90.degree. phase difference therebetween, a pair of variable-gain amplifiers for receiving the first signals to output a pair of second signals, an adder for adding both the second signals to output a sum signal, a subtracter for outputting a difference signal between the second signals, and a phase error detector for detecting the phase difference between the outputs from the adder and the subtracter to output a pair of gain control signal based on the phase difference. The gain control signal is fed-back to the variable-gain amplifier to control the ratio between the gains of the variable-gain amplifiers.

Abstract: (1) A bit phase adjusting circuit receives input data Din and passes it to a first group of delay gates which are connected in series to generate a set of data available for selection, the set including the input data Din and the input Din delayed by different amounts. The bit phase adjusting circuit selects one of the data from this set and outputs it to a bit change detecting circuit having a second group of delay gates which are connected in series. (2) In the bit change detecting circuit, at a time controlled by a reference clock signal, it is judged whether or not the input and the output data of a pth-stage delay gate of the second delay gate group coincide with each other and whether or not the output data of the pth-stage delay gate and a (p+1)th-stage delay gate coincide with each other. A change point detecting signal is generated which shows whether or not a change point of the output data from the pth-stage delay gate is within a specified range before and after the judgement time.

Abstract: An object of the invention is to provide a coordinate input apparatus which phase-shifts an input signal in accordance with temperature and corrects a phase shift due to a change in temperature, thereby performing coordinate input. A phase shift unit of a temperature phase shift circuit is constituted by connecting two thermistors having the same temperature characteristics and two capacitors having the same capacitance to constitute a bridge circuit. An output (Eout) has a gain of 1 with respect to an input (Ein) and is phase-shifted by tan.sup.-1 [(-2.omega.CR)/.+-.(1-.omega.CR).sup.2)], where R represents a value which exponentially varies in accordance with temperature. For this reason, the output signal can be phase-shifted in accordance with a change in temperature.

Abstract: The method determines the phase difference in phase locked loops using clock signals (ts) generated in clock generators of communication equipment are synchronized to incoming reference clock signals (rts). The phase difference is determined by a rough phase difference and by a fine phase difference. The fine phase difference is represented by the plurality of delay elements (VE) of a delay line (VZL) that an incoming reference clock signal (rts) traverses up to the following clock signal (ts). A precise determination of the absolute delay time of a delay element (VE) is possible using the method, whereby components' tolerances cause considerable delay time differences of a delay element (VE) or, respectively, of the delay line (VZL). A considerable enhancement of the precision in determining the phase difference of cloak signals (ts) and reference clock signals (rts) and, thus, of the phase locked loops is achieved by the more precise determination of the absolute delay time of a delay element (VE).