Abstract: Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.

Abstract: Delays are produced in differential signals using a variable capacitance provided by MOS varactors coupled between the differential signals. The capacitance values of the MOS varactors is controlled by a bias voltage applied to the bodies of the varactors. Selective application of bias voltages to the MOS varactors may be employed to selectively delay one pair of differential signals with respect to another pair of differential signals so as to change the relative phases of the signals. A logic circuit may be used to control the application of bias voltage to the MOS varactors so that signal phases may be adjusted in a manner that is predictable and programmable. These methods may be implemented to compensate for phase offsets between in-phase and quadrature signals of a local oscillator.

Abstract: A digital delaying device for delaying an input signal includes a ring oscillator, a calibration unit, and at least one delay number calculation unit and delay channel. The ring oscillator includes loop-connected delay cells for outputting an oscillation clock. The calibration unit receives a reference clock and the oscillation clock and calculates a pulse number of the oscillation clock corresponding to each reference clock period. The pulse number serves as a period reference pulse number. The calculation unit receives the pulse number and a signal delay value, calculates a signal delay number corresponding to the signal delay value according to the pulse number, and outputs a selection signal. The delay channel includes a multiplexer and cascaded delay cells, which receives an input signal and generates delay signals with different delay timings. The multiplexer selects and outputs one of the delay signals as an output signal according to the selection signal.

Abstract: A delay circuit does not lead to excessive increase in the delay time even if the source voltage drops, and enables to control the delay time from increasing. The delay circuit is designed to delay a logic signal SIN having two logic levels consisting of a low level and a high level, such that the delay times are different for the high and low levels, and the circuit chooses either the low level or the high level and targets a logic level having a shorter delay time. That is, n-MOS transistors N11, N12 and p-MOS transistors P11, P12 are provided as MOS capacitors, so as to change from the off-state to the on-state during the transition period of a signal that appears on each node disposed on a delay path of logic signals. Such a circuit design enables to control source-voltage dependence of delay time so that, even if the source voltage drops, delay times are not increased excessively.

Abstract: A clock applying circuit for a synchronous memory is comprised of a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and for delivering the clock driving signal to the synchronous memory in synchronism with but delayed from the clock input signal, the delay being a small fraction of the clock period of the clock input signal.

Abstract: A delay circuit and related apparatus for providing a longer delay time, such that when a level of an input signal changes, a level of an output signal changes accordingly after the predetermined delay time. The delay circuit has a storage unit, a current generator, a voltage generator for providing a reference voltage, a differential amplifier, and a feedback control module. The current generator starts to provide a charging current to the storage unit when the input signal changes level, such that an output charging voltage of the storages unit is gradually charged to reach the reference voltage. The feedback control module is capable of dynamically decreasing the charging current provided to the storage unit as the charging voltage is approaching the reference voltage, and the amplifier will change the level of the output voltage when the charging voltage reaches the reference voltage.

Abstract: A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.

Abstract: The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without physically changing the control device. The device for controlling a setup/hold time of an input signal has transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the device for controlling a setup/hold time of an input signal can provide a technique which can optimize the setup/hold time at a small cost in comparison with a physical metal option control system.

Abstract: The invention relates to a digital signal delay device (101) for converting a signal (IN) into a corresponding delayed signal (OUT), comprising a plurality of signal delay elements (103a, 103b, 103c) connected in series, wherein, as a function of the desired delay of the delayed signal (OUT), the output signal of a particular signal delay element (103a, 103b, 103c) is used for generating the delayed signal (OUT), and wherein the signal delay elements (103a, 103b, 103c) each comprise one single inverter (105, 106, 107) only.

Abstract: An apparatus comprising a first delay circuit. The first delay circuit may be configured to present a data delayed signal having one of a plurality of delay times. The plurality of delay times may provide a user configurable setup/hold time.

Abstract: An array of circuitry forming row and column ring oscillators is provided to determine aberrant gates in an integrated circuit. Control logic is coupled to the rows and columns to enable a ring oscillator of either a row or a column to oscillate. Based on outputs of these oscillations, aberrant gates in an integrated circuit may be more readily studied.

Abstract: A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal that determines how many of the delay stages are enabled. By varying the select signal, the delay element imposes, a variable delay upon the input signal for testing and evaluation.

Abstract: A delay circuit including a delay section having two or more predetermined delay stages is disclosed. Each predetermined delay stage adds a predetermined delay time to an input signal. The delay circuit also includes selecting switch sections. At least one of the selecting switch sections includes: a buffer section for receiving a delayed input signal from one of the delay stages and a selecting section means directly connected to the buffer section for activating the buffer section to establish a delay path, wherein an output signal from the delay path has a desired delay time.

Abstract: A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.

Abstract: Clock processing logic and method for determining clock signal characteristics in reference voltage and temperature varying environments are described. A sample vector is characterized by bit locations corresponding to sequentially increasing delay values so that values stored in such bit locations indicate clock signal edges where value transitions occur. In one embodiment, edge detection logic and sensitivity adjustment logic are used in determining the clock period from such a sample vector. In another embodiment, an edge filter, sample accumulation logic, and clock period and jitter processing logic are used in determining an average clock period and clock jitter from a predefined number of such sample vectors.

Abstract: A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A voltage-controlled delay line (VCDL) comprises a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells. A duty-cycle correction section corrects the duty cycle of the clock output signal by providing opposite current outputs which are fed back to the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions. A control current input to the series of delay cells controls the amount of the delay. A voltage-to-current converter converts a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes. The method for using the VCDL to produce linear delay is also included. The VCDL can be used in a delay-locked loop (DLL).

Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.

Abstract: A delay compensation circuit that determines the effects of process, voltage, and temperature (PVT) conditions of a chip by measuring the effective delay time of delay components inside the chip. The delay compensation circuit includes a plurality of sampler modules, each of which receives a delayed clock signal from one of a series of delay cells within a tapped delay circuit. The delay compensation circuit generates an output value based on the total number of sampling modules that lock into a fixed input signal using the delayed clock signals. Since the delay time of each delay cell changes based on variations of PVT conditions, the output values generated by the delay compensation circuit are determinate of PVT conditions in the chip. These output values can be used to design components to compensate for variances in PVT conditions or to control a variable delay component based on detected PVT conditions.

Abstract: A delay circuit has an input node receives an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.

Abstract: A method and circuitry are provided for reducing duty cycle distortion in differential solid state delay lines. The differential solid state delay lines of the present invention include a plurality of delay line cells or stages connected in series. Because there may be asymmetry associated with the physical layout of each individual delay line cell or stage, it is advantageous to cross-connect every x stage of an n-stage delay line. Method, integrated circuit, electronic system and substrate embodiments including the differential solid state delay lines are also disclosed.

Abstract: A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.

Abstract: A variable delay circuit includes a first delay circuit having a plurality of first delay stages connected in cascade. The first delay circuit receives an input signal at the initial stage of the first delay stages. A second delay circuit has a plurality of second delay stages identical to the first delay stages. The second delay circuit is connected in cascade and receives a first timing signal at the initial stage of the second delay stages. A detecting circuit receives a second timing signal asynchronous to the first timing signal, and detects, of delayed timing signals outputted from each of the second delay stages, a delayed timing signal having a transition edge near a transition edge of the second timing signal. A selecting circuit selects a delayed signal outputted from the first delay stage corresponding to the second delay stage outputting the delayed timing signal detected by the detecting circuit.

Abstract: A delayed signal generation circuit includes a first delay circuit having a plurality of delay elements connected in series and delaying a reference signal applied thereto, a second delay circuit having a plurality of delay elements connected in series each of which sends out an output signal which is delayed with respect to an input signal applied to the second delay circuit, a detector unit, responsive to the reference signal, for detecting a number of delay elements of the first delay circuit which output an output signal that is delayed with respect to the reference signal after a lapse of a predetermined time interval, and a selection unit for selecting one delay element from the second delay circuit according to the number of delay elements of the first delay circuit, and for outputting the output signal from the selected delay element as a delayed signal.

Abstract: A novel measurement method is provided capable of measuring characteristics of semiconductor integrated circuit devices without incurring the influence of external measuring means. A prescribed delay time applied to an address supplied from a microprocessor 11 to a memory 12 during normal operation is increased and a critical time where data corresponding to the address can no longer be read in by the microprocessor 11 from the memory 12 via the latch circuit 14 correctly is obtained. The delay time with which the address is supplied to the latch circuit 14 is increased with the address being supplied in a short-circuited manner to the latch circuit 14 rather than being supplied to the memory 12 and a short-circuit critical delay time where the address can no longer be read in correctly is obtained. A time difference corresponding to a difference in critical delay times is then obtained as the memory access time of the semiconductor integrated circuit device 10.

Abstract: A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries.

Abstract: A Pulse Clock Delay (PCD) apparatus (208) includes a selectable plurality (Nd) of series-connected pulse transition delay units (209) from a total plurality (Nmax) of such units. Each unit provides an incremental transition delay interval DELTA t. The PCD may be connected to a first intermediate proximal node (n1a) and an adjacent electrically isolated second intermediate node (n1b) where the first and second intermediate nodes are in a shorter (215a, 215b) of two signal paths having respective proximal and spaced apart distal ends (212, 216) in an electrical network.

Abstract: An apparatus and method for generating a compensated percent-of-clock period delay signal are described. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal.

Abstract: A method (and structure) of generating a two step variable length delay, including passing an input clock signal through a plurality of serially-interconnected delay elements, each delay element having a delay time interval dtc, thereby generating a corresponding plurality delayed signals. A set of m (where m is an integer greater than 2) of the plurality of delayed signals is switably selected. The selected m delayed signals form a first to an mth coarse adjustment delay signals. An nth coarse adjustment delay signal leads an (n+1)th coarse adjustment delay signal in phase by a time interval dtc (n is an integer being 1 or more and (m−1) or less). From the first to mth coarse adjustment delay signals, 2m fine adjustment delay signals are generated, where a jth fine adjustment delay signal leads a (j+1)th fine adjustment delay signal in a phase by a time interval dtc′, where time interval dtc′ is finer than the time interval dtc.

Abstract: A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal that determines how many of the delay stages are enabled. By varying the select signal, the delay element imposes a variable delay upon the input signal for testing and evaluation.

Abstract: A delay circuit has an input node receives an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.

Abstract: A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

Abstract: A semiconductor integrated circuit includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.

Abstract: In the case where the amplitude of the input signal is large, the duty ratio of the signal output from the last stage is greatly changed as compared with the input signal. In the present invention, in order to solve this problem, there is provided a cascade connection type inverter circuit in which the inverters at the odd-number stage is fed back to the input circuit of the inverter at the first stage via an impedance element, the circuit being characterized in that a switching means is connected for supplying to an input circuit of the inverter at the first stage a compensation current for compensating a disparity between the logical threshold value of the inverter at the first stage and the central voltage of the input signal when the voltage generated between the output terminal of the inverter at the first stage and the input terminal thereof exceeds a predetermined threshold value level.

Abstract: A composite delay line includes a first and a second delay line connected to a multiplexer. The multiplexer has a first and a second input. The first delay line includes an input, an output and first control means for controlling delay. The second delay line includes an input, an output and second control means for controlling delay. The output of each delay line is connected to the input of the multiplexer. Control logic connected to the first control means selects a delay through the first delay line. Control logic connected to the second control means selects a delay through the second delay line. Control logic connected to the multiplexer selects between the output of the first delay line and the second delay line.

Abstract: A DLL (delay locked loop) circuit includes a signal propagation system and a delay control system. The signal propagation system includes a delay circuit which delays a reference clock signal based on a delay control signal to generate a delayed clock signal. The delay control system includes a sampling circuit, a phase comparing circuit and a delay control circuit. The sampling circuit outputs a first clock signal having a pulse corresponding to one of n (n is an integer more than 1) pulses of the delayed clock signal. The phase comparing circuit compares the first clock signal as a first comparison input signal and the reference clock signal as a second comparison input signal in phase to output a phase difference. The delay control circuit generates the delay control signal based on the phase difference from the phase comparing circuit to output to the delay circuit of the signal propagation system.

Abstract: A clock control circuit for reducing jitter has at least one averaging circuit for generating, and outputting from an output terminal, a signal having a time difference obtained by internally dividing a time difference between first and second signals input respectively from first and second input terminals. First and second clock signals are supplied respectively to the first and second input terminals of the timing averaging circuit, and a clock in which a time difference between pulses of the first and second clock signals is averaged is generated.

Abstract: A control signal generation circuit according to the present invention includes a plurality of control circuits supplying different internal control signals as outputs, respectively, and a common delay circuit. The common delay circuit includes a plurality of delay circuits for delaying a control signal serving as a reference. These delay circuits are connected in series and output signals of respective delay circuits can be taken out through taps provided corresponding thereto. Each of the plurality of control circuits sets a signal level of a corresponding internal control signal according to the change in a signal level of a corresponding tap.

Abstract: A system and method for eliminating pulse width variations in digital delay lines partitions a delay line into two substantially identical blocks of delay inverters, inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be made in the most efficient manner possible and the same identical layout can be used for the first and second blocks.

Abstract: A delay circuit using MOS transistors for use of load capacitance which produces a stable delay effect for variations in signal voltage is provided. A gate of a P-type MOS transistor for load capacitance and a gate of an N-type MOS transistor for load capacitance are connected to a signal line. A resistor and CMOS inverters are used to apply a boosted voltage higher than a supply voltage VDD to a source-drain of the P-type MOS transistor for load capacitance and a substrate voltage lower than a ground voltage to a source-drain of the N-type MOS transistor for load capacitance. As a result, a gate voltage range for allowing the MOS transistors for load capacitance to have a capacitance is extended, and a stable delay effect is assured for a widened variation of signal current flowing on the signal line.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.

Abstract: In the present invention a signal generator is described for use in measuring the effects of wire to wire coupling in integrated circuits. A signal is connected to a wire that is surrounded by reference wires. A set of latches are used to set up and initiate signals simultaneously on the reference wires and the signal wire. Using latch reset and preset in phase and out of phase signals are created on the reference and signal wires that are routed in parallel. Several stages can be concatenated together in series to produce a delay resulting from coupling that can be easily measure. The latches at the beginning of each stage are activated by an enable signal to keep the signals in the reference wires and the signal wire synchronized.

Abstract: In the present invention A signal generator is described for use in measuring the effects of wire to wire coupling in integrated circuits. A signal is connected to a wire that is surrounded by reference wires. A set of latches are used to set up and initiate signals simultaneously on the reference wires and the signal wire. Using latch reset and preset in phase and out of phase signals are created on the reference and signal wires that are routed in parallel. Several stages can be concatenated together in series to produce a delay resulting from coupling that can be easily measure. The latches at the beginning of each stage are activated by an enable signal to keep the signals in the reference wires and the signal wire synchronized.

Abstract: A delay circuit in accordance with the present invention includes: a first I2L inverter and a second I2L inverter connected in cascade with each other; and a capacitor interposed between a ground and a connecting point of the first and second inverters, wherein: the delay circuit further includes a current adjusting circuit having at least one third I2L inverter with a plurality of output terminals at least one of which is connected to an input terminal of the third I2L inverter; and the current adjusting circuit is connected to adjust a charge current of the capacitor. The configuration provides a delay circuit of simple circuit structure that accounts for a small area in an integrated circuit and that is capable of introducing any given delay and also provides a ring oscillator incorporating the delay circuit.

Abstract: In this clock control circuit, clock signal CLK from a receiver is supplied to a pulse generating circuit, and the pulse generating circuit generates forward pulse, which is clock signal CLK delayed as much time as A, and pulse s which is synchronized with dock signal CLK and has a pulse width of A. Consequently, as forward pulse becomes “H” while pulse s is “L” without generating pulse which width is narrower than A, the edge part of forward pulse is securely propagated by a forward-pulse delay line even if it is high frequency. Propagation of forward pulse stops at rising edge of pulse s, and rearward pulse is generated in a corresponding stage. This rearward pulse is propagated by a rearward-pulse delay line, and outputted from an output buffer.

Abstract: A novel method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations to allow minimal test time of electronic circuit components is presented. Shoot-through scan problems introduced by loading mismatches on the TAP master and slave clock signal lines are solved by scanning an appropriate value into a programmable register, which increases the delay from master clock signal TCKM off to slave clock signal TCKS on and from slave clock signal TCKS off to master clock signal TCKM on.

Abstract: A programmable delay element includes a current source field-effect transistor (FET), a switch device, a precharge device, and an inverter device. The current source FET gates a programmable, predetermined amount of current. The switch device, which is coupled to the current source FET, receives an input signal having a first and second voltage level. The precharge device precharges the node coupled to the drain of the current source FET when the input signal is at a second voltage level. The inverter device, which is also coupled to the drain of the current source FET, outputs a delayed signal when the input signal is at a first voltage level, the delay of the delayed signal defined by the programmable, predetermined amount of current. The inverter device generates an inverter switch point that is substantially independent of parametric sensitivities, such as temperature variations.

Abstract: A method, and associated apparatus, for eliminating pulse width variations in digital delay lines. The method includes partitioning the delay line into two substantially identical blocks of delay inverters and inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated, and the parasitic loading of the inverter between the blocks and the inverter on the output of the second block is the same. Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks.

Abstract: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.