Clock Or Pulse Waveform Generating Patents (Class 327/291)
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Patent number: 9276563Abstract: A clock driver and corresponding method are provided. The clock driver includes a multi-stage delay cell having logic circuitry and a plurality of serially connected delay elements. An input of the delay elements receives an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. An output of the delay elements connects to positive and negative pulse driving branches formed from the logic circuitry. The clock driver further includes a pulse generator forming positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification.Type: GrantFiled: June 13, 2014Date of Patent: March 1, 2016Assignee: International Business Machines CorporationInventors: Aditya Bansal, Thomas J. Bucelot, Alan J. Drake, Phillip J. Restle, David W. Shan, Mrigank Sharad
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Patent number: 9264046Abstract: The present disclosure provides for a clock distribution network for distributing clocking signals within a synchronous sequential logic circuit. The clock distribution network distributes the one or more clock signals by inductively and/or capacitively coupling a clocking signal from a primary distribution node to various secondary distribution nodes within the synchronous sequential logic circuit. The various secondary distribution nodes resonate at respective resonant frequencies to generate other clocking signals for use within the synchronous sequential logic circuit in response to receiving the clocking signal.Type: GrantFiled: February 19, 2015Date of Patent: February 16, 2016Assignee: Broadcom CorporationInventors: David Chang, Ajat Hukkoo
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Patent number: 9257994Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.Type: GrantFiled: March 22, 2012Date of Patent: February 9, 2016Inventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Nasser A. Kurd, Mohamed A. Abdelmoneum
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Patent number: 9252753Abstract: Various circuits are described, which sustain an oscillation using a combination of four primary inverters, four feedforward inverters, and four coupling resistors for outputting a quadrature output signal while avoiding contention between a primary inverter and a feedforward inverter. In one configuration, a circuit includes four primary inverters configured in a ring topology, four coupling resistors uniformly interposed in the ring among the four primary inverters, and four feedforward inverters forming four sub-feedback loops, respectively, each sub-feedback loop comprising two primary inverters, one coupling resistor, and one feedforward inverter. In a further embodiment, the circuit further comprises a voltage-to-current converter is for receiving a control voltage and outputting a supply current to the four primary inverters and the four feedforward inverters. A corresponding method is also provided.Type: GrantFiled: July 7, 2014Date of Patent: February 2, 2016Assignee: REALTEK SEMICONDUCTOR CORP.Inventor: Chia-Liang (Leon) Lin
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Patent number: 9246478Abstract: The present application suggests an electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signal. The device comprises a random number generator to generate a random number signal varying in time which represents a divisor fraction signal; a signal mixer to mix the timely varying random number signal and a clock divisor signal and to output a mixed divisor signal; and a fractional clock divider to generate an output clock signal from a source clock signal, wherein the output clock signal has a frequency fout(t), which is substantially equal to the frequency fsource of the source clock signal being a narrow-band clock signal divided by a divisor D(t) represented by the mixed divisor signal.Type: GrantFiled: March 13, 2014Date of Patent: January 26, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Thomas Henry Luedeke, Joseph Circello
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Patent number: 9229109Abstract: A three dimensional imaging camera comprises a system controller, pulsed laser transmitter, receiving optics, an infrared focal plane array light detector, and an image processor. The described invention is capable of developing a complete 3-D scene from a single point of view. The 3-D imaging camera utilizes a pulsed laser transmitter capable of illuminating an entire scene with a single high power flash of light. The 3-D imaging camera employs a system controller to trigger a pulse of high intensity light from the pulsed laser transmitter, and counts the time from the start of the transmitter light pulse. The light reflected from the illuminated scene impinges on a receiving optics and is detected by a focal plane array optical detector. An image processor applies image enhancing algorithms to improve the image quality and develop object data for subjects in the field of view of the flash ladar imaging camera.Type: GrantFiled: June 17, 2014Date of Patent: January 5, 2016Assignee: Advanced Scientific Concepts, Inc.Inventors: Roger Stettner, Howard Bailey, Brad Short, Laurent Heughebaert, Patrick Gilliland
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Patent number: 9213316Abstract: A circuit for detecting and correcting timing errors. A timing circuit includes an interpolator. The interpolator includes a fine counter, a coarse counter, and stop correction logic. The coarse counter is incremented by a rollover output of the fine counter to generate a coarse count value. The stop correction logic is coupled to the fine counter and the coarse counter. The stop correction logic divides each cycle of the rollover output into first, second, and third time intervals, and selects a coarse counter output value to represent a time interval measured by the coarse counter based on a one of the first, second, and third intervals in which a time measurement stop signal is detected.Type: GrantFiled: February 6, 2015Date of Patent: December 15, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Vikas Suma Vinay, Rajani Manchukonda
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Patent number: 9203382Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.Type: GrantFiled: February 3, 2015Date of Patent: December 1, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Matthew S. Berzins, Prashant U. Kenkare
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Patent number: 9171600Abstract: A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.Type: GrantFiled: March 7, 2014Date of Patent: October 27, 2015Inventors: Naoki Shimizu, Ji Hyae Bae
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Patent number: 9151851Abstract: A multiplexing circuit for a positron emission tomography (PET) detector includes a delay circuit and a multiplexer communicating with the delay circuit. The delay circuit configured to receive a plurality of timing pickoff (TPO) signals from a plurality of positron emission tomography (PET) detector units, add a delay time to at least one of the plurality of TPO signals, and transmit the TPO signals based on the delay time to the multiplexer, the multiplexer configured to a multiplex the TPO signals and output a single TPO signal from the plurality of TPO signals to a Time-to-Digital Convertor (TDC). A method of operating a multiplexer and a imaging system including a multiplexer are also provided.Type: GrantFiled: June 27, 2013Date of Patent: October 6, 2015Assignee: General Electric CompanyInventors: Mark David Fries, David Leo McDaniel
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Patent number: 9111623Abstract: A resistive memory sensing method includes sensing outputs of an offset-cancelling dual stage sensing circuit (OCDS-SC) by an NMOS offset-cancelling current latched sense amplifier circuit (NOC-CLSA). The NOC-CLSA is configured with a reduced input capacitance and a reduced offset voltage. Input transistors of the NOC-CLSA are coupled between latch circuitry and ground. A first phase output of the OCDS-SC is stored by the NOC-CLSA during a pre-charge step of the NOC-CLSA operation. A second phase output of the OCDS-SC is stored by the NOC-CLSA during an offset-cancelling step of the NOC-CLSA operation. By pipelining the OCDS-SC and NOC-CLSA, a sensing delay penalty of the OCDS-SC is overcome.Type: GrantFiled: February 12, 2014Date of Patent: August 18, 2015Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Taehui Na, Ji-su Kim, Jung Pill Kim, Seung Hyuk Kang
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Patent number: 9106233Abstract: Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.Type: GrantFiled: February 27, 2013Date of Patent: August 11, 2015Assignee: MARVELL ISRAEL (M.I.S.L) LTD.Inventor: Eitan Rosen
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Patent number: 9093989Abstract: A clock signal generator module arranged to generate at least one clock signal for at least one functional module is described. The clock signal generator module comprises a first clock source component associated with at least one functional module, at least one further clock source component associated with the at least one functional module, and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one functional module associated therewith.Type: GrantFiled: November 21, 2011Date of Patent: July 28, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Anton Rozen, Michael Priel, Yossi Shoshany
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Patent number: 9081517Abstract: A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices.Type: GrantFiled: August 31, 2011Date of Patent: July 14, 2015Assignee: Apple Inc.Inventors: Kleanthes Koniaris, Josh P. de Cesare, Timothy J. Millet, Jung Wook Cho, Erik Machnicki
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Patent number: 9058863Abstract: A reference frequency setting method of a memory storage apparatus including the following steps is provided. A setting code is read from a memory module or a storage unit by a first signal transmission path and stored into a register circuit. The setting code includes a first setting information. Whether the data having a specific frequency is inputted is detected. If not, the setting code stored in the register circuit is read, such that an oscillator circuit module of the memory storage apparatus generates a first reference frequency based on the first setting information. If yes, the setting code stored in the register circuit is updated by a second signal transmission path, and the updated setting code is read, such that the oscillator circuit module generates a second reference frequency based on a second setting information. The updated setting code includes the second setting information.Type: GrantFiled: April 26, 2013Date of Patent: June 16, 2015Assignee: PHISON ELECTRONICS CORP.Inventors: Chih-Ming Chen, An-Chung Chen
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Publication number: 20150145582Abstract: A circuit for generating a series of pulses in response to a first signal, the circuit comprising: a lossy integrator which receives a second signal as its input; and a comparator which: receives the output of the lossy integrator at one of its inputs; and receives the first signal at the other of its inputs. This circuit can be incorporated into, for example, audio-frequency amplifiers and regulated power supplies.Type: ApplicationFiled: April 30, 2013Publication date: May 28, 2015Applicant: INDICE SEMICONDUCTOR INC.Inventor: James Hamond
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Patent number: 9041451Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.Type: GrantFiled: December 13, 2012Date of Patent: May 26, 2015Assignee: Cyclos Semiconductor, Inc.Inventors: Marios C. Papaefthymiou, Alexander Ishii
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Patent number: 9030518Abstract: A clock signal generating circuit that generates a clock signal, the clock signal generating circuit including a clock signal generator configured to generate a reference clock signal; and a plurality of dividers to which the reference clock signal is to be input. A division ratio of at least one of the plurality of dividers varies based on division ratio data that defines the division ratio of the at least one of the plurality of dividers. The division ratio data represents a value that fluctuates around reference division ratio data with respect to time.Type: GrantFiled: February 26, 2014Date of Patent: May 12, 2015Assignee: Ricoh Company, Ltd.Inventor: Shintaro Kawamura
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Patent number: 9030246Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.Type: GrantFiled: October 3, 2014Date of Patent: May 12, 2015Assignee: Renesas Electronics CorporationInventors: Hideki Uchiki, Satoru Kishimoto
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Patent number: 9024671Abstract: Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator.Type: GrantFiled: December 20, 2013Date of Patent: May 5, 2015Assignee: Realtek Semiconductor Corp.Inventors: Chia-Liang Leon Lin, Joseph Gerchih Chou
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Patent number: 9024672Abstract: Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit.Type: GrantFiled: September 10, 2014Date of Patent: May 5, 2015Assignee: Canon Kabushiki KaishaInventor: Koji Kawamura
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Patent number: 9018999Abstract: A hardware/PLC logic combination which enables measurement of a plurality of analog voltage points (e.g., multiples of 8 points) on a single high speed PLC input without separate synchronization inputs or outputs. This is accomplished through the use of a multiplexer circuit [clock, binary counter, analog multiplexer, voltage to frequency converter], and a high speed counter function at the PLC. Synchronization between the PLC and circuit is through the detection of a fixed voltage on channel “one” of the circuit, which is set well above the typical range (e.g., 0-10V) of the remaining analog inputs.Type: GrantFiled: June 19, 2013Date of Patent: April 28, 2015Assignee: M&R Printing Equipment, Inc.Inventor: Keith R. Falk
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Patent number: 9018849Abstract: In one embodiment, method of signal processing can include: (i) determining a high level sampling pulse amount by counting a number of pulses of a first clock signal during a high level portion of a period of a first PWM; (ii) generating a first pulse signal based on a second clock signal and the high level sampling pulse amount; (iii) determining a low level sampling pulse amount by counting a number of pulses of the first clock signal during a low level portion of the period of the first PWM signal; (iv) generating a second pulse signal based on the second clock signal and the low level sampling pulse amount; and (v) generating a second PWM signal based on the first and second pulse signals.Type: GrantFiled: June 18, 2014Date of Patent: April 28, 2015Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.Inventors: Yunlong Han, Huiqiang Chen
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Patent number: 9018996Abstract: Circuits, architectures, a system and methods for providing quadrature output signals. The circuit generally includes a quadrature signal generator and a plurality of frequency dividers. The plurality of frequency dividers are each configured to receive a plurality of quadrature signal generator outputs at a first frequency and provide a plurality of outputs at a second frequency. The method generally includes providing a plurality of quadrature signals at a first frequency and dividing the first frequency of the quadrature signals by n, wherein n is an odd integer of at least 3, thereby providing a plurality of divided-by-n quadrature outputs at a second frequency, wherein the second frequency is about equal to the first frequency divided by n. The present disclosure further advantageously improves quadrature signal generation accuracy, reliability and/or performance.Type: GrantFiled: July 6, 2010Date of Patent: April 28, 2015Assignee: Marvell International Ltd.Inventor: Hossein Zarei
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Patent number: 9007114Abstract: A semiconductor device for stably generating a clock signal from a strobe signal includes a processor, a clock signal generation unit receiving a first strobe signal and a second strobe signal to generate the clock signal, and a data reception unit receiving at least one data signal to provide the received data signal to the processor. The clock signal generation unit may comprise a strobe comparator comparing a voltage of a first input terminal with that of a second input terminal to output logic high or logic low, a first switch selectively connecting one of a first and a second signal line to the first input terminal, a second switch selectively connecting one of the second signal line and a reference line to the second input terminal, and a voltage stabilizing circuit pulling up/down at least one of a voltage of the first and the second signal line.Type: GrantFiled: January 15, 2014Date of Patent: April 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Kyunghoi Koo
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Patent number: 9000823Abstract: An integrated circuit includes a clock source tier and at least two clock tree tiers disposed in a vertical stack with the clock source tier. The clock source tier includes a clock circuit, and each of the at least two clock tree tiers includes a clock tree circuit. The clock circuit is disposed in the clock source tier is coupled to the clock tree circuits disposed in the at least two clock tree tiers by at least one inter-layer via.Type: GrantFiled: September 12, 2013Date of Patent: April 7, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Mu-Shan Lin
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Patent number: 8994458Abstract: A method includes determining a control setting and selectively stopping oscillation of an oscillator after a time period. The oscillator is configured to remain in an active mode after the time period. The method further includes applying the control setting to the oscillator.Type: GrantFiled: November 8, 2011Date of Patent: March 31, 2015Assignee: QUALCOMM IncorporatedInventor: Martin Saint-Laurent
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Circuit and method of frequency jitter, and application thereof in switched-mode power supply (SMPS)
Patent number: 8994462Abstract: The present invention is to provide a frequency jitter circuit and a method for generating frequency jitter. The frequency jitter circuit, comprising: an oscillating circuit, configured to generate an oscillating frequency output signal; a decoding circuit, configured to be controlled by said oscillating frequency output signal for generating several pulse output signals; a delay circuit, through which said oscillating frequency output signal is passed for generating a frequency jitter output signal that is delayed a period of time compared to said oscillating frequency output signal. Application of the invention into switched-mode power supply might reduce EMI average noise in the switched-mode power supply, and smooth energy spectrum density.Type: GrantFiled: August 19, 2010Date of Patent: March 31, 2015Assignee: Hangzhou Silan Microelectronics Co., Ltd.Inventors: Weijiang Zhou, Yunlong Yao -
Patent number: 8994432Abstract: A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits.Type: GrantFiled: August 23, 2013Date of Patent: March 31, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Hoi Jin Lee
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Patent number: 8994433Abstract: A fully on-chip clock generator on an integrated circuit (“IC”) includes a frequency detector for receiving a reference current and providing a first voltage; an error integrator for receiving the first voltage from the frequency detector, comparing it with a reference voltage, and providing a control voltage; a voltage controlled oscillator (“VCO”) for receiving the control voltage from the error integrator, and providing an output clock; and a logic controller on the IC, coupled between the VCO and the frequency detector, and generating logic control signals for controlling the frequency detector. The fully on-chip clock generator requires no external crystal, but its power consumption is significantly lower than a relaxation oscillator that generates the same clock frequency.Type: GrantFiled: January 13, 2012Date of Patent: March 31, 2015Assignee: Analog Devices, Inc.Inventor: Yijing Lin
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Patent number: 8988126Abstract: An apparatus for controlling a latency in a synchronous semiconductor device. The apparatus includes a first counting block for counting a cycle of a first clock signal to thereby generate a first binary code; a second counting block for counting a cycle of a second clock signal to thereby generate a second binary code. The second clock signal is obtained by delaying the first clock signal by a predetermined delay amount, A code comparison block stores the second binary code in response to a command and compares the first binary code with the second binary code to thereby generate a latency control signal.Type: GrantFiled: August 4, 2005Date of Patent: March 24, 2015Assignee: Hynix Semiconductor, Inc.Inventors: Si-Hong Kim, Sang-Sic Yoon
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Patent number: 8982999Abstract: An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.Type: GrantFiled: September 30, 2012Date of Patent: March 17, 2015Assignee: Intel CorporationInventors: Kiriti Bhagavathula, Chunyu Zhang, Steven A. Peterson
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Patent number: 8975949Abstract: Inventive aspects include an integrated clock gater (ICG) circuit having clocked complimentary voltage switched logic (CICG) that delivers high performance while maintaining low power consumption characteristics. The CICG circuit provides a small enable setup time and a small clock-to-enabled-clock delay. A significant reduction in clock power consumption is achieved in both enabled and disabled modes, but particularly in the disabled mode. Complimentary latches work in tandem to latch different voltage levels at different nodes depending on the voltage level of the received clock signal and whether or not an enable signal is asserted. An inverter takes the voltage level from one of the nodes, inverts it, and outputs a gated clock signal. The gated clock signal may be active or quiescent depending on the various voltage levels. Time is “borrowed” from an evaluation window and added to a setup time to provide greater tolerances for receiving the enable signal.Type: GrantFiled: March 14, 2013Date of Patent: March 10, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Matthew S. Berzins, Prashant U. Kenkare
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Patent number: 8975936Abstract: An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.Type: GrantFiled: August 31, 2012Date of Patent: March 10, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Visvesh S. Sathe, Samuel D. Naffziger
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Patent number: 8970266Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.Type: GrantFiled: October 30, 2013Date of Patent: March 3, 2015Assignee: Renesas Electronics CorporationInventors: Kosuke Yayama, Takashi Nakamura
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Patent number: 8970267Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.Type: GrantFiled: September 2, 2010Date of Patent: March 3, 2015Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian
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Patent number: 8963603Abstract: A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.Type: GrantFiled: April 4, 2014Date of Patent: February 24, 2015Assignee: Realtek Semiconductor Corp.Inventors: Shih-Hsiun Huang, Shian-Ru Lin
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Patent number: 8963604Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.Type: GrantFiled: April 7, 2014Date of Patent: February 24, 2015Assignee: Micron Technology, Inc.Inventors: Eric Booth, Tyler J. Gomm, Kallol Mazumder, Scott E. Smith, John F. Schreck
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Patent number: 8963602Abstract: A pulse generator is disclosed. The pulse generator can include an ac source for providing an ac signal. A pulsed switch can be connected to an ac output of the ac source that is adapted or configured to generate a pulsed output from the ac signal and a non-linear frequency multiplier adapted or configured to shorten the pulses of the pulsed output. The pulsed switch can include a mixer.Type: GrantFiled: September 21, 2005Date of Patent: February 24, 2015Assignee: The University Court of the University of St. AndrewsInventors: David Robert Bolton, Graham Smith
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Patent number: 8963606Abstract: A clock control device is disclosed, which relates to a technology for reducing the amount of current consumption when a semiconductor device operates at a high speed. The clock control device includes: a chip-select-signal control block configured to generate a chip-select-control signal by latching a chip select signal, and output a fast chip select signal according to the chip-select-control signal; and a clock control block configured to drive a clock signal in response to the fast chip select signal when a command clock enable signal is activated, thereby generating a clock control signal, wherein the chip-select-signal control block latches the chip-select-control signal, and controls the chip-select-control signal to be toggled after the command clock enable signal is transitioned.Type: GrantFiled: November 13, 2013Date of Patent: February 24, 2015Assignee: SK Hynix Inc.Inventor: Bok Rim Ko
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Patent number: 8963605Abstract: Disclosed is a multi-phase clock signal generation circuit including two circuit blocks, each of which includes a cross-coupled structure and two delay units, and the delay units are adjustable. One circuit block (MD1) includes two NMOS transistors, two PMOS transistors, and two delay units, and the other circuit block (MD2) may include two NMOS transistors, two PMOS transistors, and two delay units. The circuit can generate clock signals with respective phases whose relationship is relatively independent of integration process, operating voltage and temperature, thereby allowing guaranteed efficiency for a multi-phase charge pump.Type: GrantFiled: November 30, 2011Date of Patent: February 24, 2015Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Weiwei Chen, Lan Chen, Shuang Long
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Patent number: 8963587Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.Type: GrantFiled: May 14, 2013Date of Patent: February 24, 2015Assignee: Apple Inc.Inventors: Erik P. Machnicki, Raman S. Thiara, Shane J. Keil, Timothy J. Millet
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Patent number: 8952740Abstract: A pulsed latching apparatus and a method for generating a pulse signal are provided. The pulsed latching apparatus consists of a pulsed latch and a pulse signal generator. A data input terminal of the pulsed latch receives input data, the pulsed latch latches the input data according to a pulse signal, and transmits the latched input data through the data output terminal to serve as output data. The pulse signal generator duplicates a data transmission delay between the data input terminal and the data output terminal of the pulsed latch to obtain a duplicated delay. The pulse signal generator receives a clock signal, and processes the clock signal according to the duplicated delay to generate the pulse signal.Type: GrantFiled: September 6, 2013Date of Patent: February 10, 2015Assignee: Industrial Technology Research InstituteInventor: Shien-Chun Luo
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Patent number: 8947145Abstract: A PWM signal generation circuit according to the present invention includes a duty setting unit (10) configured to generate a duty control signal designating a duty ratio corresponding to each period of a PWM signal on the basis of an initial duty setting signal, a target duty setting signal, a slope setting signal, and a clock signal, a period setting unit (20) configured to output a period setting value, and an output control unit (30) configured to generate the PWM signal having a period corresponding to the period setting value and having a duty ratio corresponding to a value of the duty control signal. The duty setting unit (10) increases the value of the initial duty ratio to the value of the target duty ratio each time the number of a clock pulse of the clock signal reaches the period setting value reaches the slope setting value.Type: GrantFiled: February 24, 2012Date of Patent: February 3, 2015Assignee: Renesas Electronics CorporationInventor: Yasuyuki Fujiwara
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Publication number: 20150008970Abstract: A period signal generation circuit includes a first buffer unit suitable for buffering a buffer signal and output an output signal; and a second buffer unit suitable for buffering the output signal and output a period signal, wherein each of the first and second buffer units includes a resistor element coupled between a body of a metal oxide semiconductor (MOS) transistor and a source.Type: ApplicationFiled: December 19, 2013Publication date: January 8, 2015Applicant: SK hynix Inc.Inventor: Man Keun KANG
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Patent number: 8928505Abstract: In one embodiment, an audio processing system includes a frequency control block that forms a system clock and a master audio clock. The frequency control block is configured to change a frequency of the system clock and change a relationship between the system clock and the master audio clock so that the frequency of the master audio clock remains substantially constant.Type: GrantFiled: September 4, 2013Date of Patent: January 6, 2015Assignee: Semiconductor Components Industries, LLCInventors: Ivo Leonardus Coenen, Paulo Jorge Duarte de Jesus
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Patent number: 8928385Abstract: A system-on-chip includes a clock controller configured to decrease an operating frequency of at least one function block based on a change in an operating state of the at least one function block from an active state to an idle state. In a method of operating a system-on-chip including at least one function block, an operating frequency of the at least one function block is decreased based on a change in an operating state of the at least one function block from an active state to an idle state. The decreased operating frequency is greater than zero.Type: GrantFiled: November 28, 2012Date of Patent: January 6, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Keun Kim, Sun Cheol Kwon, Si Young Kim, Jae Gon Lee, Jung Hun Heo
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Patent number: 8922264Abstract: Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.Type: GrantFiled: April 26, 2013Date of Patent: December 30, 2014Assignee: Altera CorporationInventors: Yan Chong, Warren Nordyke, Sean Shau-Tu Lu, Weiqi Ding
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Patent number: 8923444Abstract: A receiver for decoding a communication signal is disclosed. The receiver includes an input port and a filter. The input port receives the communication signal from a communication medium. The communication signal comprises a sequence of symbols. Each symbol of the symbol sequence is an analog pulse that has a leading edge of exponential shape. The exponential shape has an exponential growth parameter value that has been selected from values ?0 and ?1, which are distinct positive values. For each symbol of the symbol sequence, the exponential growth parameter value for the leading edge of the symbol has been selected based on a corresponding bit from a stream of information bits. The filter receives the communication signal from the input port and filters the communication signal to obtain an output signal. The transfer function of the filter has one or more zeros at ?0.Type: GrantFiled: June 30, 2014Date of Patent: December 30, 2014Assignee: Board of Regents, The University of Texas SystemInventor: Robert H. Flake
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Patent number: 8917129Abstract: An apparatus comprising a delay circuit and a control circuit. The delay circuit may be configured to generate a plurality of intermediate signals in response to (i) a clock signal and (ii) an adjustment signal. The control circuit may be configured to generate the adjustment signal and a plurality of output signals having a quarter-cycle interval in response to (i) the plurality of intermediate signals and (ii) the clock signal.Type: GrantFiled: June 12, 2013Date of Patent: December 23, 2014Assignee: Ambarella, Inc.Inventors: Guangjun He, Xiaojun Zhu