Abstract: Methods and apparatus are disclosed for predistorting an input signal to compensate for non-linear distortions introduced by an electronic device, for example, a power amplifier. The non-linear effects of a power amplifier can be modeled using different behavior models. Coefficients for one behavior model can be converted into coefficients for a different behavior model using a conversion function. A conversion circuit implementing the conversion function can be used in between a predistorter and an adaptation circuit that use different models.

Abstract: Described herein is an integrated circuit which comprises: a first buffer, with positive trans-conductance, to drive a first signal with first phase; and a second buffer, with negative trans-conductance, to drive a second signal with second phase, wherein the first buffer and the second buffer are cross-coupled to one another.

Abstract: A delay element delays an output signal Dt from an arithmetic circuit and outputs a delayed signal Dd. An XOR element compares the output signal Dt with the delayed signal Dd, and outputs an XORout signal with the signal value “0” when the signals match each other, and outputs an XORout signal with the signal value “1” when the signals do not match each other. In a flip-flop, when the signal value of the XORout signal at the rise of a clock of a clock signal CK is “0”, the output signal Dt is output from a flip-flop, and when the signal value of the XORout signal at the rise of the clock becomes “1” even once, a fixed value of the signal value “0” continues to be output.

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.

Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.

Abstract: The present invention relates to a pulse signal generation circuit for changing a pulse width of an input pulse signal and outputting an output pulse signal having the changed pulse width. In an aspect, the pulse signal generation circuit may include a control signal generator configured to generate at least one control signal according to a pulse width of a input pulse signal and a pulse signal generator configured to control a pulse width of an input pulse signal in response to a control signal and to generate an output pulse signal with the controlled pulse width. The control signal controls the pulse width of the output pulse signal.

Abstract: This disclosure provides examples of circuits, devices, systems, and methods for generating a reference clock signal and delaying a received clock signal based on the reference clock signal. In one implementation, a circuit includes a control block configured to generate a control signal. The circuit includes an oscillator configured to generate a reference clock signal. The oscillator includes a plurality of delay elements each configured to receive the control signal and to introduce a delay in the reference clock signal based on the control signal. The delay elements of the oscillator are arranged to generate the reference clock signal. The circuit further includes a delay block configured to receive a clock signal and to generate a delayed clock signal. The delay block includes one or more delay elements each configured to receive the control signal and to introduce a delay in the clock signal based on the control signal.

Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: A high voltage waveform is generated that is similar to a low voltage input waveform. The high voltage waveform is a series of pulses that are applied directly to the device. An error signal controls the frequency, magnitude, and duration of the pulses. A feedback signal derived from the high voltage waveform is compared with the input waveform to produce the error signal.

Abstract: Adjusting a Modulation and Coding Scheme (MCS) or more generally, Layer One parameters, for a data packet based on packet information and priority is disclosed. The packet information can typically be extracted from the packet's header. Considering packet-specific information enables cross-layer optimization that can include consideration of packet error rate (PER) constraints, delay constraints, relative importance of packets within a data stream, beamforming (e.g., off or on, implicit or explicit—longer distances are more likely to merit implicit beamforming) constraints, and aggregation as a function of MCS or channel condition (more aggregation is generally desirable for higher MCS or better channels), to name several examples. It is also possible to differentiate drop probability based on the importance of frames like anchor frames, etc.

Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.

Abstract: Disclosed is a proportional controller that utilizes a deflected metal cantilever that provides a progressive change in capacitance for a given deflection that is used to generate a proportional control signal. In addition, a efficient step-up converter 1500 is disclosed, which is capable of operating with a single alkaline cell. Further, a LED drive circuit is disclosed that has high efficiency and is capable of driving an infrared LED with a single alkaline cell.

Abstract: An arbitrary modulation frequency of a modulating signal is selected. The modulating signal is applied to an information-bearing signal, where such modulation is carried out through digital signal processing operations. The digitally modulated signal is resolution-reduced and the quantization noise introduced by such is shaped to locate a spectral null in the noise transfer function of the resolution reducing modulator at the modulation frequency. Thus, the modulation frequency can be selected independently of the clock frequency at which the resolution-reduced samples are converted to an analog signal.

Abstract: A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.

Abstract: A multi-phase clock generator may receive an input clock signal as an input. The clock generator may also receive an inverse of the input clock signal. The clock generator may produce a plurality of output clock signals having different phases. The phases of the output clock signals may be evenly spaced. The output clock signals may have a similar waveform to the input clock signal, with a frequency that is lower than the input clock signal by a division factor.

Abstract: An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases.

Abstract: A method and system are described for adaptively adjusting data communication of a rateless coding system, including adaptively estimating a symbol coding length, determining a symbol threshold, determining if the adaptively estimated symbol coding length is less than the symbol threshold, adjusting a transmission power level based on the second determining act and adaptively adjusting a modulation scheme based on the second determining act. Also described are a method and system for decoding communication of a rateless coding system, including receiving encoded symbols, determining if a length of the received encoded symbols is greater than a threshold number of encoded symbols and decoding the received encoded symbols if the length of the received encoded symbols is greater than the threshold number of encoded symbols.

Abstract: A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.

Abstract: A method and circuit for providing on-chip measurement of the delay between two signals includes first and second delay chains (241, 242) having different delay values connected to sampling latches (222-227) which each include a data input coupled between adjacent delay elements of the first delay chain and a clock input coupled between adjacent delay elements of the second delay chain, thereby capturing a high precision delay measurement for the signals.

Abstract: Described is an integrated circuit having a clock distribution network capable of transitioning from a non-resonant clock mode to a first resonant clock mode Transitions between clock modes or between various resonant clock frequencies are done gradually over a series of clock cycles. In example, when transitioning from a non-resonant clock mode to a first resonant clock mode, a strength of a clock sector driver is reduced over a series of clock cycles, and individual ones of a plurality of resonant switches associated with resonant circuits are modified in coordination with reducing the strength of the clock sector driver.

Abstract: A receiver includes an antenna interface, a frequency translation bandpass filter (FTBPF), a sample and hold module, and a down conversion module. The antenna interface is operable to receive a received wireless signal from an antenna structure and to isolate the received wireless signal from another wireless signal. The FTBPF is operable to filter the received wireless signal to produce an inbound wireless signal. The sample and hold module is operable to sample and hold the inbound wireless signal in accordance with an S&H clock signal to produce a frequency domain sample pulse train. The down conversion module is operable to convert the frequency domain sample pulse train into an inbound baseband signal.

Abstract: A clock signal capable of changing the frequency in a wide range and with high resolution is generated. An operational amplifier AMP1 is subject to feedback control so that the voltage of a positive input part equals that of a negative input part. The voltage of a circuit node fbck equals a reference voltage VREFI. A decoder DEC decodes control signals CNT7 and CNT6 and turns on one of transistors T2 to T5. This configuration provides feedback control so that the voltage of the circuit node fbck equals the reference voltage VREFI. This significantly reduces the on-resistances of the transistors T2 to T5 and prevents the degradation of the frequency accuracy.

Abstract: Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal. In any case, a deskewer, which comprises a pair of single-ended latches and either multiplexer(s) or logic gates, processes the first differential clock signal, the single-ended clock signal, and the control signal(s) in order to output a second differential clock signal that is different from the first differential clock signal in terms of delay and, optionally, frequency, but synchronously linked to it.

Abstract: An oscillation circuit includes a threshold voltage extraction module, a positive temperature coefficient voltage generation module, an addition module, a common-source amplifier module, a charge and discharge module, and a clock output terminal. The common-source amplifier module includes a first field effect transistor (FET) and a second FET. The addition module includes a first operational amplifier, a second operational amplifier, a third FET, a fourth FET, a fifth FET, a sixth FET, a first resistor, a second resistor, and a third resistor. The charge and discharge module includes a seventh FET, an eighth FET, a charge and discharge FET, a first switch, a second switch, a first comparator, a second comparator, a first nor gate and a second nor gate. An oscillation system is further provided. The oscillation circuit and the oscillation system of the present invention have simple structures and are easy to implement.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.

Abstract: Method, circuitry and device for spreading a clock signal in which the clock signal is received at an input of a variable delay line, the clock signal having been generated by a clock signal generator. In one embodiment, for each edge of the clock signal, the delay introduced by the variable delay line is set in accordance with a stored delay value. For each of a plurality of consecutive edges of the clock signal, the stored delay value is either incremented or decremented based on a randomly generated value for that edge. A spread version of the clock signal is output from the variable delay line, wherein each edge of the spread version of the clock signal is delayed by the respective delay that is set for that edge of the clock signal.

Abstract: A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator.

Abstract: The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.

Abstract: A clock generation circuit includes a system clock selection circuit that selects one of a first and a second clock signals with different frequencies from each other as a system clock signal according to a selection signal, a frequency division circuit that divides the system clock signal and generates a plurality of divided clock signals, and a communication clock selection circuit that selects a communication clock signal from the plurality of divided clock signals according to the selection signal and a division ratio setting signal, and switches to the selected communication clock signal in synchronization with a switching timing of the selection signal.

Abstract: A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.

Abstract: An electrical circuit and a procedure for tracking at least one input pulse width applied to the electrical circuit. The electrical circuit includes a threshold component (e.g., a comparator) arranged to provide an output pulse width based on whether an input to the threshold component exceeds a threshold. The circuit also includes a controller arranged to control the threshold of the threshold component, based on the at least one input pulse width applied to the electrical circuit, such that the output pulse width of the threshold component tracks the at least one input pulse width applied to the electrical circuit. The controller includes at least a switch, and the output pulse width tracks the at least one input pulse width by following or anticipating the pulse width. In one example embodiment the tracking is performed for a series of pulses of varied widths.

Abstract: A signal processing device includes a signal processing chip and a conducting path. The signal processing chip includes: a first port capable of receiving a first oscillating signal; a second port capable of outputting a second oscillating signal derived from the first oscillating signal; and a third port. The conducting path is external to the signal processing chip and coupled to the second port and the third port, and the conducting path is capable of transmitting the second oscillating signal outputted from the second port to the third port.

Abstract: A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.

Abstract: The present invention discloses a method for generating a low jitter clock, including: inserting a time delay in each low-speed clock period to finely adjust a high-speed clock, and then performing frequency division operation on the adjusted high-speed clock to obtain the required low-speed clock. The present invention also discloses an apparatus for generating the low jitter clock at the same time. By using the method and the apparatus, the jitter of the low-speed clock can be decreased. The implementation method is simple and convenient and the device cost is saved.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit, at least one inductor, at least one tunable resistance switch, and a capacitor network. The inductor, tunable resistance switch, and capacitor network are connected between the clock grid and a reference voltage. The at least one tunable resistance switch is programmable to dynamically switch the at least one inductor in or out of the clock distribution to effect at least one resonant mode of operation or a non-resonant mode of operation based on a frequency of the clock signal.

Abstract: Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference clock signal. Then, a second phase skew is measured between a delayed version of the first clock signal output by the memory when the memory completes a given read operation and the second clock signal. The memory access time is determined based on the first and second phase skews.

Abstract: A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees of the clock mesh network in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path of the design area. The method encapsulates the efficient implementation of the gated local trees and activity driven register clustering with timing slack awareness for clock mesh synthesis. With gated local tree and activity driven register clustering, the switching capacitance on the mesh network can be reduced by 22% with limited skew degradation. The method has two synthesis modes as low power mode and high performance mode to serve different design purposes.

Abstract: A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.

Abstract: A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal.

Abstract: An output circuit providing isolation between inputs and the output employs first and second opto-couplers for isolation. Pulse activation of the first opto-coupler turns on an output transistor and pulse activation of the second opto-coupler turns off the output transistor. An input stage of the output circuit is and light emitting devices of the first and second opto-couplers are powered by a first power source and an output stage of the output circuit is powered from an external power source. Power consumption by the input stage of output circuit occurs only during pulse activation of the first and second opto-couplers.

Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.

Abstract: A control circuit 10 includes an internal clock generating portion (12), which starts generating an internal clock signal (LCLK) required by a control portion (11) to perform action when a specific signal pattern appears in a trigger signal, continually generates the internal clock signal (LCLK) at least before the control portion (11) completes predetermined processing, and then stops generating the internal clock signal (LCLK); and the control portion (11), which uses the internal clock signal (LCLK) to perform the predetermined processing.

Abstract: The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.

Abstract: A method and apparatus for glitch-free switching of multiple phase clock have been disclosed where switching from one phase to another phase is done step-by-step to avoid generating a glitch.

Abstract: Apparatus for generating a truly random binary bit value in which the resistance of memristive devices serve as the analogue bit values. Resistance values and the randomness by which they are generated stems from the inherently non-uniform, irreproducible variations in the materials of which the system is composed.

Abstract: A layer-ID detector for multilayer 3D-IC, including a random generator to generate a random signal, a layer-ID designation mechanism circuit coupled to the random generator to generate a layer-ID designating signal, and a counter coupled to the layer-ID designating signal to output a layer-ID signal.