Abstract: A method and device are disclosed. In one embodiment the method includes driving a first clock domain reference signal on a first clock tree and driving a second clock domain reference signal on a second clock tree. The first tree routes the first signal from a PLL to a first clock domain drop off circuit and the second tree routes the second signal from the PLL to a second clock domain drop off circuit. A jitter produced from the second tree is less than a jitter produced from the first tree. The method continues by detecting any phase misalignment between the first signal and the second signal. The method also causes the first signal to be delayed so that it aligns with the second signal.

Abstract: The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations.

Abstract: A spread spectrum clock generator (SSCG) control and inspection circuit provides a system and method for inspecting and controlling an external SSCG, and for verifying the modulation profile waveform of an external SSCG. An electronic circuit is included that can check for the presence of an optimal SSCG modulation profile in product subsystems, and in attached modular systems, including electronic plug-in features such as internal network adapters and cartridges. In one mode of the invention, an electronic circuit ensures continued radiated emissions compliance for field replaceable units or consumable parts within a product, such as a printer, a scanner, or a combination (or all-in-one) printer/scanner. In another mode of the invention, an electronic circuit may also act as a secondary security device for consumable products, such as toner cartridges or ink jet cartridges. In yet another mode of the invention, an electronic circuit may also adjust the attached SSCG clock.

Abstract: The internal read signal generator according to the present invention includes: a first delay unit for delaying a clock signal in order to obtain a margin of a setup/hold time of an input signal; a signal transfer unit for transferring the input signal in synchronization with the delayed clock signal of the first delay unit; a second delay unit for delaying an output signal of the signal transfer unit; and an output unit for combining the input signal and an output signal of the second delay unit, wherein an amount of the delay of the second delay unit is determined in order that a rising edge of an output signal of the output unit has a period of the clock signal.

Abstract: The invention relates to a method for distributed, fault-tolerant clock pulse generation in hardware systems, wherein the system clock pulse is generated in distribution by a plurality of intercommunicating fault-tolerant clock pulse synchronization algorithms (TS-Algs), in which an arbitrary number of such TS-Algs exchange information between one another via a user-defined and permanent network (TS-Net) of clock pulse signals, susceptible to transient faults, and each TS-Alg is assigned to one or more functional units (Fu1, Fu2, . . . ), whose local clock pulses are generated by it, and further all local clock pulses are synchronized with respect to frequency in an assured manner, and a specified number of transient and/or permanent faults may occur in the TS-Algs or in the TS-Net, without adversely affecting the clock pulse generation and/or the synchronization accuracy, and the system clock pulse automatically achieves the maximum possible frequency. The invention further relates to such a hardware system.

Abstract: A duty cycle correction circuit may include an error corrector adapted to correct duty cycles of first differential analog clock signals input to a pair of input terminals based on duty cycle correction signals input to a pair of control terminals and to output second differential analog clock signals having corrected duty cycles through a pair of output terminals, an analog to digital buffer adapted to convert the second differential analog clock signals to differential digital clock signals, a duty error detector adapted to detect duty cycles of the differential digital clock signals and to output a N bit digital signal, and a duty error correction signal generator adapted to output differential control current signals having current gains controlled based on the second differential analog clock signals and the N bit digital signal to the pair of control terminals as the duty cycle correction signals.

Abstract: An optical scanning device is constituted without using any arc sin ? correction lens, while maintaining quality of an image.

Abstract: A circuit arrangement including a voltage supply device, which has an output, and that provides a variable supply voltage, a supply-voltage-controlled clock generator, which is coupled to the output of the voltage supply device, and that provides a system clock signal having a variable effective system clock frequency, a circuit section having a supply terminal, which is coupled to the output of the voltage supply device, and a clock input, which receives the system clock signal, and a regulating device that determines a supply-voltage-dependent supply current value and detects the extent to which the supply current value lies within a predetermined current value range, and which is coupled to the voltage supply device such that the supply voltage is regulated based on whether the supply current value lies within the predetermined current value range.

Abstract: A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

Abstract: A synchronization circuit includes a first level-shifting unit receiving an input reference signal having a first swing voltage and generating a first level change signal having a second swing voltage and a second level change signal having a third swing voltage, and a synchronization unit generating first and second output signals by synchronizing the first level change signal with the second level change signal.

Abstract: Apparatus (100) for communicating clock correction data between two or more clocked entities (102, 104) using a standardized clock correction unit or quanta. A source-native pre-scaler (302) can convert source-native clock correction values to scaled source-native clock correction values. The pre-scaler can perform this conversion by multiplying each source-native clock correction value by a factor N1. A source-native divider (308) can divide an adjusted source-native clock correction value by a value M1 to produce a standard quotient and a standard remainder. The standard quotient defines a standard clock correction value. Further, a source-native accumulator 306 can accumulate a sum comprised of the scaled source-native clock corrections and the standard remainder produced from the source-native divider. The sum can define the adjusted source-native clock correction value.

Abstract: An object is to provide a clock generating circuit that can suppress variation of an oscillation frequency from the clock generating circuit, which is due to a change in the output voltage according to a discharging characteristic of the battery, and effectively utilize the remaining power of the battery. A structure includes an output voltage detecting circuit for detecting an output voltage from a battery; a frequency-division number determining circuit for determining the number of frequency-division by a value of the output voltage detected by the output voltage detecting circuit; an oscillation circuit for outputting a reference clock signal depending on the output voltage; a counter circuit for counting a number of waves of the reference clock signal that depends on the number of frequency-division; and a frequency-dividing circuit that frequency-divides the reference clock signal depending on the number of waves counted by the counter circuit.

Abstract: According to some embodiments, a process, voltage, and temperature compensated clock generator is disclosed. The clock generator may be a charge-charge clock generator including a first load capacitive element and a second load capacitive element. A process, voltage, and temperature compensated current source is coupled to the charge-charge clock generator, and is used to charge the first load capacitive element and the second load capacitive element.

Abstract: An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal operates so that the control signal is maintained to complete a last cycle period after an inactivation timing of the oscillator enable signal.

Abstract: Converter systems are disclosed that use particular combinations of fixed and variable clock skewers to generate interleaved clock signals for the systems. These combinations have been found effective in accurately generating selectively-skewed clocks while simultaneously restricting the jitter that generally accompanies the skewing process.

Abstract: A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.

Abstract: An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

Abstract: A method and device for generating a clock signal, the method including measuring, using a first clock signal, a characteristic of a reference event in a received signal, determining, using the first clock signal, a variation of a characteristic of a second event in a received signal, correcting the measurement according to the variation of the characteristic of the second event, and generating a second clock signal using the first clock signal according to the corrected measurement.

Abstract: A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal

Abstract: The clock generator for semiconductor memory apparatus which includes: a first divider; a first delay unit; a second divider; a second delay unit; a duty-cycle corrector; a third divider; a third delay unit; a phase comparator; and a delay time setting unit. The clock generator for semiconductor memory apparatus exactly performs phase correction and duty cycle correction using frequency-divided clocks. Therefore, it is possible to generate reliable clocks and to improve the operational performance of a system using the clock generator.

Abstract: A control unit featuring clocked data transmission between a processor and at least one further circuit, the processor itself outputting the clock pulse. The processor monitors the clock pulse based on the output signals of at least two clock outputs.

Abstract: Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.

Abstract: Disclosed is a system and method for providing an oscillating signal of relatively precise frequency without using a signal provided by a crystal as a reference. Disclosed is a feedback oscillator circuit configured to output an oscillating signal having a frequency defined by a reference signal. The oscillating signal can be sent to one or more circuits including at least one frequency sensitive element. The frequency sensitive element produces an output signal which depends on the frequency of the oscillating signal. A controller controls the reference signal in order to cause an attribute of the output signal to have a value within a desired range.

Abstract: Disclosed herein is a clock supplying apparatus for supplying a clock to a digital circuit, including: a differential clock driver; a first clock line along which a first clock of a positive phase from the clock driver propagates; a second clock line along which a second clock of a reverse phase from the clock driver propagates; and a parallel resonance circuit of an inductor and a capacitor. The inductor of the parallel resonance circuit is connected at a first end to the first clock line and at a second end to the second clock line. The capacitor of the parallel resonance circuit is connected at a first electrode to the first clock line and at a second electrode to the second clock line.

Abstract: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal.

Abstract: A circuit, method, and system are disclosed. In one embodiment the circuit comprises a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency, a checker circuit to compare a count of clock signal oscillations observed per complete loop of the ring oscillator circuit to a reference count, and to set a flag signal if the clock signal oscillation count is above a high threshold amount or below a low threshold amount.

Abstract: Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some embodiments, a clock repeater and phase-error correcting circuit may include a polyphase network having a non-symmetrical frequency response selected to reduce static phase error from a multi-phase clock signal, and an output buffer to buffer and to amplify the phase-corrected multi-phase clock signal.

Abstract: A semiconductor device designing method of the present invention corresponds to a method for designing a clock synthesization type semiconductor device, which is comprised of: a rough CTS (clock tree synthesis) step for performing the CTS within an adjustable range in multiple phases; a timing check step for judging whether or not transmission/reception of data are carried out under normal condition based upon a propagation time of data and an arrival time of a clock signal between flip-flops; a detailed timing analyzing step for judging whether or not the transmission/reception of the data can be carried out under the normal condition by switching a phase of a clock signal, or by increasing/decreasing a buffer in a half way of the clock tree as to supply timing of the clock signal; and a re-allocating step of a CLK net, for allocating a phase of such a clock signal which does not cause a timing violation every flip-flop based upon the result of the detailed timing analyzing step.

Abstract: A method, apparatus, article of manufacture, and system, the method including, in some embodiments, providing a differential clock ganging structure to receive complementary differential clock signals, the differential clock ganging structure outputting clock ganging output signals, providing a source termination structure for each of the clock ganging output signals, and providing an inductance and capacitance compensation structure to receive an output of the source termination structure and to connect to a terminal interconnect for at least one of the clock ganging output signals.

Abstract: An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.

Abstract: The present invention relates to a clock signal distribution circuit for distributing the clock signal to circuits such as LSI integrated circuits, and, more specifically, provides a clock adjuster circuit, which performs phase difference adjustment of clock signals automatically. It is a circuit, which on driving a circuit element implemented on an LSI chip, supplies the clock signal, which is a reference for driving, is distributed subsequently from first distribution to lower-level distributions of a hierarchical structure, or from a fifth level distribution circuit “5” to every area on the LSI chip, for example. At that time, delay of the clock signal is detected by a phase difference detector circuit, the delay data is automatically written to a delay adjuster circuit built into each of the fifth level distribution circuits “5”. Using the delay data, the phase difference of the clock signals, is adjusted when the LSI chip is manufactured.

Abstract: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having a second frequency, synchronize the second signal with the first signal, and propagate the synchronized second signal to at least one other clock mesh of the apparatus.

Abstract: A control circuit for command signals of a clock generator includes a power supply end, an output end, a control end, a diode, a first resistor and a second resistor. The first resistor, the diode, and the second resistor are connected in series between the power supply end and the ground. The diode has an anode connected to the first resistor and a cathode connected to the second resistor. The control end is connected to a node between the diode and the second resistor; the output end is connected to a node between the diode and the first resistor. The output end outputs the command signals to the clock generator.

Abstract: A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor.

Abstract: A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, synchronously stop adding fill-in clock pulses, and track the request for data acquisition.

Abstract: Distributed traveling wave oscillator circuitry is disclosed. The oscillator circuitry includes a signal path, a plurality of active switching means, and a direction promoting means. The signal path is formed from a pair of adjacent conductors and exhibits endless electric or magnetic continuity. The signal path also includes a portion that creates a signal phase inversion which sets half-cycles of oscillation to be the time of a single traverse of the signal path by the signal. The plurality of active switching means is connected between the adjacent conductors of the signal path for setting rise and fall times of each said half-cycle of oscillation. The direction promoting means establishes the direction of the traveling wave on the signal path.

Abstract: In one embodiment, a distributed redundant control signal distribution system comprises a first control signal source co-located with a first set of control signal controlled circuit elements, at least one second control signal source co-located with a second set of control signal controlled circuit elements, at least one controller for providing control signals from the first control signal source to control both the first and second sets of controlled circuit elements, the controller operable for substituting signals from the second control signal source for signals from the first signal control source if the signals from the first control signal source become unavailable to either the first or second circuit elements.

Abstract: High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.

Abstract: A processor provides a configured clock rate setting for use by a peripheral set. The processor receives back from the peripheral set a feedback clock rate setting. The configured clock rate setting and the feedback clock rate setting are compared to detect over-clocking of the processor.

Abstract: A clock signal outputting method in which either a clock signal based on a signal from the outside or an alternative clock signal from a fixed oscillator is selected and outputted, wherein, when the clock signal is selected to be outputted, the fixed oscillator is put into non-operating state, and when any error occurs in the clock signal, the fixed oscillator is operated to output the alternative clock signal.

Abstract: The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.

Abstract: A timing generator capable of improving design efficiency by facilitating adaptation to change in design. The timing generator has work area 9 which outputs parameters in response to control data, and main core 12 to which the parameters are inputted. In the work area, V and H parameters are described. The main core consists of third comparator 11 for comparing a count value of V counter 10 with V parameter and outputting a first control pulse, first comparator 1 for comparing a count value of H counter 3 with H parameter and outputting a second control pulse, second comparator 4 for comparing a count value of high speed counter 8 with H parameter and outputting a third control pulse, first selector 2 for selecting the second control data or the third control data, and first JK flip flop 5 for generating a timing signal from output of the first selector.

Abstract: High resolution digital delay circuits and methods are provided. A multiplexer receives the outputs of first and second delay elements. At least the second delay element is adjustable using a digital control signal. The multiplexer and the first delay element form a first delay loop. The multiplexer, the first delay element and the second delay element form a second delay loop. A logic circuit monitors the number of times (M) that a signal cycles through the first loop. After M reaches a predetermined value (i.e., when the signal is delayed by a predetermined delay), the multiplexer receives a control signal that causes the second loop to close. A signal cycles through the second loop, which provides additional delay. Preferably, the signal cycles through the second loop only once. Generally, this causes the resolution of the delay circuit to be proportional to the minimum delay adjustment of the second delay element.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.

Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.