With Plural Paths In Network Patents (Class 327/293)
  • Patent number: 6737903
    Abstract: A semiconductor integrated circuit device includes internal circuits divided into blocks that are controlled block by block for activation. Each internal circuit receives a clock signal from a clock distribution network of a block including that internal circuit. The clock signal is supplied to the clock distribution network by buses of a tree structure and a clock drive control gate. The clock drive control gate stops, in response to an enable signal for controlling activation of internal circuits block by block, the clock signal from being supplied, when internal circuits of a corresponding block are inactivated.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: May 18, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Hiroaki Suzuki
  • Patent number: 6720815
    Abstract: In semiconductor integrated circuit devices containing a macro, a skew occurs between the clock pulse supplied to the latch in that mother circuit and the clock pulse supplied to the latch inside the macro. These clock skews obstruct the high frequency operation of the semiconductor integrated circuit device clock frequency so the semiconductor integrated circuit device cannot be operated at high speed.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 13, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Hiroyuki Mizuno
  • Patent number: 6703859
    Abstract: An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being generated and retaining a processing speed of the device. To this end, according to the present invention, there is provided a device including logic blocks for carrying out logical operation, lines for connecting the logic blocks, line-changing means for changing the state of lines connecting the logic blocks by programming, a clock net for supplying a clock signal to each of the logic blocks, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of the logic blocks can be stopped from being supplied with the clock signal.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: March 9, 2004
    Assignee: Fujitsu Limited
    Inventor: Norichika Kumamoto
  • Patent number: 6701507
    Abstract: A method for computing a position for a zero-skew driver insertion point in an area occupied by nodes driven by the driver is described. The zero-skew driver insertion point is the position in the area where the spread of the signal arrival times at the nodes driven by the driver is minimized. The method includes: expressing a function describing a distance from each of the nodes to the zero-skew driver insertion point, expressing the variance of the function, minimizing the variance of the function, and solving an equation representative of the minimization of the variance of the function to determine the position of the zero-skew driver insertion point. In one embodiment, the minimizing the variance of the function includes: taking a first derivative of the function with respect to the distance, and setting the first derivative of the function to zero.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: March 2, 2004
    Assignee: Sequence Design, Inc.
    Inventor: Adi Srinivasan
  • Publication number: 20040017242
    Abstract: A clock distribution network includes a plurality of clock drivers for outputting clock signals. At least one of the plurality of clock drivers has a driving capacity that is not equal to a driving capacity of at least another one of the plurality of clock drivers. The distribution network also includes a grid distribution network for distributing the clock signals output from the plurality of clock drivers.
    Type: Application
    Filed: April 28, 2003
    Publication date: January 29, 2004
    Inventor: Dong-Hyun Lee
  • Patent number: 6674315
    Abstract: Each of a plurality of clock generation units has a clock driver which generates a clock signal in accordance with a reference clock, and a supplying unit which supplies the reference clock to the clock driver. The supplying unit supplies the clock driver, in a case where another clock generation unit is already attached to a clock signal generation device at a time the clock generation unit to which the supplying unit belongs is attached to the clock signal generation device, with a clock signal generated by the clock driver of the another clock generation unit as the reference clock during a predetermined time. The clock driver makes a clock signal to be generated follow the supplied reference clock.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: January 6, 2004
    Assignee: NEC Corporation
    Inventor: Hiroshi Kamiya
  • Patent number: 6657474
    Abstract: In a clocking network with clock distribution in the gigahertz frequencies, low voltage swings are generated and applied instead of full voltage swings. The low voltage swing circuits are differential low voltage swing circuits. True and complement signals are transmitted in the global path, enabling cancellation of common mode noise picked up along the path from the generation point to the destination local ends, where the noise is subtracted from the signals. The low voltage swing circuits include a differential translator/driver, differential repeaters and differential receivers/translators to enable centrally generated low voltage swing clock signals to be distributed throughout the chip and to be faithfully converted to full voltage swing clock signals at the local ends.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: December 2, 2003
    Assignee: Intel Corporation
    Inventor: Hemmige D. Varadarajan
  • Patent number: 6653883
    Abstract: A clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. When the tree deskew circuit is deskewed for a multilevel clock tree, the temporary clock net of that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock tree deskew circuit adjusts the variable delay clock buffer signal of each pair toward the temporary clock buffer signal of the pair to reduce the skew between the two clock buffer signals.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 25, 2003
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6650161
    Abstract: A clock distribution network for an integrated circuit is disclosed. The network includes a plurality of inverters that distribute a clock signal. The inverters are powered by a power supply. The power supply is supplied to the inverters through a source follower transistor that has its gate connected to a regulated DC voltage. The source follower transistor operates in the saturation region.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: November 18, 2003
    Assignee: Intel Corporation
    Inventors: Thomas P. Thomas, Ian A. Young
  • Patent number: 6639442
    Abstract: An integrated circuit having at least two clock systems in which the appropriate clock signal, starting from a clock input, can be forwarded through clock trees to individual switching elements or switching blocks. In this arrangement, each clock tree has an associated controlled switch which, for selected operating states, can be used to apply a single common clock signal to the clock trees, where at least a first clock tree has a PLL unit connected upstream of it, and an output of this clock tree is connected to an input of the PLL unit in order to form a phase locked loop, and the switches are actuated in selected operating states such that the common clock signal is supplied to a last clock tree, and an output of this clock tree is connected to the other input of the PLL unit for the at least first clock tree.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: October 28, 2003
    Assignee: Siemens Aktiengesellschaft
    Inventors: Majid Ghameshlu, Karlheinz Krause
  • Patent number: 6630855
    Abstract: A phase alignment technique includes providing a clock signal to a first clock distribution spine and providing at least one additional clock distribution spine. One PLL (Phase Locked Loop) is provided for each additional clock distribution spine, each PLL having an REF input and an FBK input and an output. The REF input of each PLL is connected to the first clock distribution spine and the FBK input of each PLL is connected to its respective clock distribution spine and the output of each PLL is connected to its respective clock distribution spine to provide a clock signal thereto. Each PLL provides phase alignment between the clock signal on the first clock distribution spine and the clock signal outputted by the PLL to its respective clock distribution spine. The first clock distribution spine and each additional clock distribution spine and its respective PLL may be disposed on an integrated circuit die.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: October 7, 2003
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Ernest Knol
  • Patent number: 6605972
    Abstract: A method and apparatus are provided for recycling power in an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 12, 2003
    Assignee: LSI Logic Corporation
    Inventor: Bradley J. Wright
  • Patent number: 6583648
    Abstract: A method and apparatus provide power control for a multiple giga-hertz frequency integrated circuit. The method and apparatus include multiple levels of clock gating control circuitry and a clock distribution network to generate a low-skew system clock signal, and generate a gated clock signal, from the system clock signal, and distribute the gated clock signal to a plurality of local logic circuits in the integrated circuit.
    Type: Grant
    Filed: March 19, 2002
    Date of Patent: June 24, 2003
    Assignee: Intel Corporation
    Inventor: Zhong-Ning (George) Cai
  • Patent number: 6577167
    Abstract: A clock signal producing apparatus is composed of a detecting circuit and a clock signal outputting circuit. The detecting circuit detects edge timings of an input signal at which the input signal is inverted. The edge timings are quantized to a predetermined number of states. A clock signal outputting circuit outputs an outputted clock signal. A phase of the outputted clock signal is adjusted based on the edge timings.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: June 10, 2003
    Assignee: NEC Corporation
    Inventor: Masaaki Soda
  • Patent number: 6570429
    Abstract: A clock distribution tree for use with a semiconductor chip. The package for a semiconductor chip includes a clock distribution tree having a plurality of output terminals for connection to a plurality of input pads on a semiconductor chip. According to one embodiment, the semiconductor chip includes a clock receiving and conditioning circuit which is coupled to a clock input signal line. The clock receiving and conditioning circuit receives a clock signal, filters it, amplifies it and outputs it back to the package having a clock distribution tree thereon. The clock distribution tree thereafter distributes the clock signal to the appropriate locations of the semiconductor chip through clock output terminals coupled to clock input paths on the semiconductor chip.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: May 27, 2003
    Assignee: Cray Inc.
    Inventor: Stephen V. R. Hellriegel
  • Patent number: 6560752
    Abstract: An apparatus and method for buffer selection for use in buffer insertion is provided. An optimal buffer library generator module operates to reduce a general buffer library down to a optimal buffer library based on parameters that are input to the optimal buffer library generator module. Based on these parameters, the optimal buffer library generator module selects buffers from the general buffer library for inclusion in an optimal buffer library. In a preferred embodiment, the optimal buffer library is generated by generating a set of superior buffers and inverters and clustering the set of superior buffers. A single buffer is then selected from each cluster for inclusion in the optimal buffer library. The result is a smaller buffer library which will provide approximately the same performance during buffer insertion while reducing the amount of computing time and memory requirements.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: May 6, 2003
    Assignee: International Business Machines Corporation
    Inventors: Charles Jay Alpert, Rama Gopal Gandham, Jose Luis Pontes Correia Neves, Stephen Thomas Quay
  • Patent number: 6559701
    Abstract: A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: May 6, 2003
    Assignee: LSI Logic Corporation
    Inventor: Michael N. Dillon
  • Patent number: 6552589
    Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: April 22, 2003
    Assignee: International Business Machines Corporation
    Inventor: Robert Paul Masleid
  • Patent number: 6542017
    Abstract: The present invention relates to a clock generator circuit which comprises a clock generator subcircuit which is operable to generate two clock signals having approximately the same frequency for use in sampling an analog signal in a generally alternating fashion. The clock generator circuit further comprises a pre-phase clock generator subcircuit associated with the clock generator subcircuit which is operable to generate two pre-phase clock signals, wherein each are associated with a respective one of the two clock signals generated by the clock generator subcircuit. In the pre-phase clock generator circuit, a signal transition of each of the pre-phase clock signals occurs before a signal transition of the respective clock signal generated by the clock generator subcircuit; in addition, a timing of a falling edge of the pre-phase clock signals is dictated by a global clock signal.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: April 1, 2003
    Assignee: Texas Instruments Incorporated
    Inventor: Gabriele Manganaro
  • Patent number: 6538489
    Abstract: One clock is selected from a plurality of clocks by a selector through programming. Clock lines are connected to the outputs of clock buffers connected to the selector. Programmable connector elements are connected onto these lines, and flip-flops and regulation loads are connected thereto. The programmable connector elements are selected through programming. This construction can realize a clock distributing circuit in a programmable logic device, which can suppress an increase in skew and can reduce a clock line wiring area.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: March 25, 2003
    Assignee: NEC Corporation
    Inventor: Hirotaka Nakano
  • Patent number: 6525588
    Abstract: A clock controlling circuit and method for eliminating the delay difference in the entire clock propagation line. Circuit scale is reduced as compared to a case of using a PLL or DLL circuit. A timing averaging circuit 10 is fed with clocks from a position on a forward route 111 of a direction-reversed clock propagation path, adapted for being fed with input clocks at its one end, and from a position on a return route 112 corresponding to the position on the forward route 111. The timing difference between these clocks is averaged to output an averaged timing difference.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: February 25, 2003
    Assignee: NEC Corporation
    Inventor: Takanori Saeki
  • Patent number: 6522186
    Abstract: A hierarchical clock distribution system includes a global clock grid that distributes a clock signal to a plurality of regional clock grids. Each of the regional clock grids then distributes the signal to a plurality of corresponding loads. The regional clock grids utilize salphasic clocking techniques to distribute the clock signal to the corresponding loads. The global grid achieves low skew based on the periodicity of the clock signal, rather than the dominance of a standing wave. The electrical distance to termination within the regional clock grids is preferably kept low to avoid the occurrence of phase change regions on the regional grids. In one approach, the regional grids are each driven at multiple points in a symmetrical fashion to reduce the electrical distance to termination.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: February 18, 2003
    Assignee: Intel Corporation
    Inventors: Frank O'Mahony, Mark A. Anders, Krishnamurthy Soumyanath
  • Patent number: 6504415
    Abstract: In many electronic systems, it is common to communicate data from a transmitter in one device to a receiver in another. Accurate communications requires use of several matched clock signals. Mismatches in these clock signals cause transmitters to add “jitter” to transmitted data or receivers to be more intolerant of jitter in received signals, increasing the chances of mis-interpreting the data. Accordingly, the inventors devised an exemplary clock-distribution method which entails generating a base set of matched clock signals, deriving at least two separate sets of matched clock signals from the base set, and distributing one of the sets of clock signals to a set of matched components in a circuit and the other set of matched clock signals to a different set of components in the same circuit. The clock signals driving the matched components are isolated from mismatched aspects of the other components, and thus exhibit better matching.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: January 7, 2003
    Assignee: Xilinx, Inc.
    Inventors: Moises E. Robinson, Ahmed Younis
  • Patent number: 6498541
    Abstract: A station in a communication bus system is connected to a signal transmission line. The station contains a wave splitter coupled to the transmission line and a transmission section coupled to an input of the wave splitter for transmitting an outgoing wave signal to travel out over the transmission line from the wave splitter. The station contains a reception section coupled to an output of the wave splitter for receiving an incoming wave signal that travels into the wave splitter from the connector. The station has a control unit being arranged to operate in different control modes, according to the presence or absence of a further apparatus connected to the transmission line, dependent on whether the reception section does not detect or does detect a reflection of a wave transmitted by the transmission section, respectively.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: December 24, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Gerrit Willem Den Besten, Marcus Egbert Kole
  • Patent number: 6489805
    Abstract: A circuit comprising a clock generator and a state machine. The clock generator may be configured to generate an output clock signal in response to (i) a first enable signal and (ii) a second enable signal. The state machine may be configured to generate the second enable signal in response to a first and a second control signal.
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: December 3, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Johnie Au, Pidugu L. Narayana, Sangeeta Thakur
  • Patent number: 6466074
    Abstract: A clock splitter device for forming a clock/inverted clock signal pair. The input clock signal is sent through an initial buffer stage and applied to two parts of a second stage. The second stage includes a single stage buffer and constricted inverter to provide two inverted outputs. The transistor arrangement of these two parts provides an equal delay to the two signal paths. The outputs of these two parts are sent to identical output buffers. Because the two paths have identical transistor delays, and since the metal paths on the board are arranged to have identical delays, the two paths can very low skew therebetween.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: October 15, 2002
    Assignee: Intel Corporation
    Inventors: Kersi H. Vakil, William N. Roy, Jerry G. Jex
  • Patent number: 6456138
    Abstract: A clock splitter circuit for providing a single event upset (SEU) tolerant clock signal to latches in a space-based environment. The clock splitter circuit can include one or more event offset circuit delay circuits. The event offset delay receives a clock signal and generates a delayed clock signal. The event offset delay circuit can generate an inverted clock signal, a delayed inverted clock signal and a pair of intermediate clock signals. The delayed clock signal and inverted delayed clock signal can be delayed by the known duration of single event effects (SEE). The delayed and undelayed clock signals can be passed to an event blocking filter which can block any disturbance in the delayed and/or undelayed clock signals. A synchronizer can synchronize outputs of the event blocking filter prior to or coincident with being passed to corresponding inverting clock drivers. The synchronizers can also insure that the synchronized blocking filter outputs can not be low simultaneously.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: September 24, 2002
    Assignee: BAE Systems Information and Electronic Systems Integration, Inc.
    Inventors: Joseph W. Yoder, Abbas Kazemzader
  • Patent number: 6452435
    Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Timothy M. Skergan, Johnny J. LeBlanc
  • Patent number: 6433598
    Abstract: A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: August 13, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6426649
    Abstract: A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: July 30, 2002
    Assignee: QuickLogic Corporation
    Inventors: Robert Fu, David D. Eaton, Kevin K. Yee, Andrew K. Chan
  • Patent number: 6404259
    Abstract: The invention relates to a device for generating digital control signals having the following features: an oscillator (10), which has a digital output two storage means (20, 30) for storing the value of digitally coded variables, which each have a clock input (22, 31) connected to the digital output (11) of the oscillator (10), a data input (21, 32) and a data output (23, 33) an adder (40) which has two data inputs (41, 42), a data output (43) and a carry output (44), where the first data input (41) of the adder (40) is connected to the data output (23) of the first storage means (20), the second data input (42) of the adder (40) is connected to the data output (33) of the second storage means (30), the data output (43) of the adder (40) is connected to the data input (32) of the second storage means (30), and the carry output (44) of the adder (40) is connected to a pulse divider (50).
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: June 11, 2002
    Assignee: Patent-Treuhand-Gesellschaft fuer Elektrische Gluehlampen mbH
    Inventor: Olaf Busse
  • Patent number: 6396323
    Abstract: In semiconductor integrated circuit devices containing a macro, a skew occurs between the clock pulse supplied to the latch in that mother circuit and the clock pulse supplied to the latch inside the macro. These clock skews obstruct the high frequency operation of the semiconductor integrated circuit device clock frequency so the semiconductor integrated circuit device cannot be operated at high speed.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: May 28, 2002
    Assignee: Hitachi, Ltd.
    Inventor: Hiroyuki Mizuno
  • Patent number: 6384659
    Abstract: An IC (Integrated Circuit) including internal circuitry to which a multiphase clock is distributed includes 1/n clock, main wiring drivers each including a frequency divider for dividing the frequency of an input clock by n and a drive circuit for delivering the resulting 1/n clock to a corresponding 1/n clock main wiring. Normal clock, main wiring drivers each include a delay for delaying an input clock to thereby output a normal clock and a drive circuit for delivering the normal clock to a corresponding normal clock main wiring. A clock distributing circuit includes clock wirings for distributing a clock input via a clock input circuit and a plurality of repeat buffers for distributing the distributed clock to each of the 1/n clock and normal clock, main wiring drivers. The IC additionally includes a wiring wiring the outputs of the repeat buffers, a wiring wiring the outputs of 1/n clock, main wiring drivers, and wiring wiring the outputs of the normal clock, main wiring drivers.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: May 7, 2002
    Assignee: NEC Corporation
    Inventor: Hiroki Inohara
  • Patent number: 6380788
    Abstract: A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: April 30, 2002
    Assignee: Faraday Technology Corp.
    Inventors: Chen-Teng Fan, Jyh-Herng Wang, Yu-Wen Tsai, Peng-Chuan Huang
  • Patent number: 6362676
    Abstract: A clock splitter circuit for providing a Single Event Upset (SEU) tolerant clock signals to latches in a space-based environment. The splitter circuit includes an event offset delay. The event offset delay receives an undelayed clock signal and generates an undelayed inverted clock, a delayed clock signal and an inverted delayed clock signal. The delayed clock signal and the inverted delayed clock signal are delayed by the known duration of Single Event Effects (SEE) on logic. The delayed and undelayed clock signals are passed to a pair of event blocking filters which block any disturbance in the undelayed and/or undelayed clock signals. The event blocking filters each generate a pair of in-phase inverted output signals. The event blocking filters are designed such that both pairs of outputs may not be low simultaneously.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: March 26, 2002
    Assignee: BAE Systems Information and Electronic Systems Integration, Inc.
    Inventor: Joseph A. Hoffman
  • Patent number: 6353352
    Abstract: A clock tree topology distributes a clock signal from a single input terminal 400 to three terminals 421-423 with an equal phase delay. The topology includes four lines 401-404 connected together at a first end 450 with adjacent lines forming right angles. A second end of the line 404 forms the clock signal input terminal 400. A second end of the remaining lines 401-403 are connected to first ends of lines 411-413. Second ends of the lines 411-413 form the terminals 421-423. A right angle is formed between each of the lines 401-403 and the respective one of the lines 411-413 to which it connects.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: March 5, 2002
    Assignee: Vantis Corporation
    Inventor: Bradley A. Sharpe-Geisler
  • Patent number: 6340905
    Abstract: A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop, such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: January 22, 2002
    Assignee: LSI Logic Corporation
    Inventor: Richard T. Schultz
  • Patent number: 6333660
    Abstract: A semiconductor device for generating first and second internal clocks complementary with each other from an external clock and usable for both a system of a type using a complementary clock and a system of a type generating a 180° phase clock internally, is disclosed. A first clock input circuit (buffer) is supplied with a first external clock and outputs a first internal clock. A second clock input circuit (buffer) is supplied with a second external clock complementary with the first external clock and outputs a second clock. A ½ phase clock generating circuit generates a ½ phase shift signal 180° out of phase with the first internal clock. A second external clock state detection circuit judges whether the second external clock is input to the second clock input buffer.
    Type: Grant
    Filed: February 12, 2001
    Date of Patent: December 25, 2001
    Assignee: Fujitsu Limited
    Inventors: Masao Taguchi, Hiroyoshi Tomita, Yasurou Matsuzaki
  • Patent number: 6326830
    Abstract: An automatic clock calibration circuit includes a source of clock signals and an equal number of corresponding clock reference signals. Corresponding delay elements are connected between the source and the load driven by each of the clock signals. A phase frequency detector detects the phase differences between each clock signal, at the point at which it is applied to its load, and its corresponding clock reference signal. A microcontroller adjusts the delay of the delay elements according to the detected phase differences.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: December 4, 2001
    Assignee: Intel Corporation
    Inventors: Gary Brady, Roger R Rees, Jerry Moberly, Pete Nevard, Christopher P. Swider
  • Patent number: 6323714
    Abstract: A system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit within a local clock buffer within each of a number of circuit zones and applying a controllable delay at each of the local clock buffers in response to a phase comparison of clock signals from one or more adjacent clock zones. The system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and localized phase comparators. By adjusting each localized clock buffer delay unit in response to measured clock signal phase differences from adjacent circuit zones, clock skew problems can be minimized across various clock zones on a VLSI circuit.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: November 27, 2001
    Assignee: Hewlett-Packard Company
    Inventors: Samuel D Naffziger, Eugene Z Berta, Gerard M Blair, James Steven Wells
  • Publication number: 20010020859
    Abstract: A synchronous delay circuit apparatus include two sets of synchronous delay circuits 100, 101 each including a first delay circuit chain for period measurement in which input clocks propagate and a second delay circuit chain for period reproduction and delay detection circuits 5, 7 for detecting the propagation delay time caused in propagating clocks from an input node to an output node of a clock propagation path to issue a control signal for halting propagation of the input clock signals to the respective synchronous delay circuits. A delay circuit 6 is introduced in an input of at least one 7 of the delay detection circuits to differentiate a delay time detected in one delay detection circuit 7 from a delay time detected by the other delay detection circuit 5 to differentiate detected period from the delay detected in the other delay detection circuit 5.
    Type: Application
    Filed: March 5, 2001
    Publication date: September 13, 2001
    Inventor: Takanori Saeki
  • Patent number: 6288589
    Abstract: The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: September 11, 2001
    Assignee: Intrinsity, Inc.
    Inventors: Terence M. Potter, James S. Blomgren, Anthony M. Petro, Stephen C. Horne
  • Patent number: 6255884
    Abstract: A plurality of intermediate driving devices are included in stages between a clock generator and a bank of synchronous logic devices. The outputs of the intermediate devices in each stage are connected in parallel over a wide linear dimension. The timing delay of each circuit is then subject to a small variation depending on the irregularities associated with the device characteristics used in its construction. The outputs of the intermediate devices in each stage are tied together to restore regularity and uniformity to all clock generation circuit outputs.
    Type: Grant
    Filed: February 16, 2000
    Date of Patent: July 3, 2001
    Assignee: Pairgain Technologies, Inc.
    Inventor: Lanny L. Lewyn
  • Patent number: 6239628
    Abstract: A semiconductor integrated circuit device is dislosed for self-monitoring presence/absence of a data flow and transmitting the data on the basis of the result of the monitoring. The semiconductor integrated circuit device comprises a plurality of data paths each further comprising at least two logic-circuit blocks. One of the data paths have data-arrival detector for detecting arrival of data and components on the other data paths operate synchronously with those on the data path having the data-arrival detector.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: May 29, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Fumio Murabayashi, Tatsumi Yamauchi, Yutaka Kobayashi
  • Patent number: 6222410
    Abstract: A semiconductor circuit capable of keeping the leakage current to a minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to a maximum, wherein delay paths to which low threshold voltage gate elements are applied are restricted to delay paths in a range from a maximum delay value before a lowering of a threshold voltage (at a higher speed than this) to a new maximum delay value in a case where low threshold voltage gate elements are applied to this (at a lower speed than this), whereby a leakage current due to low threshold voltage transistors can be kept to the minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to the maximum, thereby solving the problem of an unrequired leakage current applied to a chip over a wide range.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: April 24, 2001
    Assignee: Sony Coorporation
    Inventor: Katsunori Seno
  • Patent number: 6215346
    Abstract: A clock pulse generator comprises N stages 1, 2, where N is greater than 3. Each ith stage comprises a transmission gate M3, M4; M9, M10 which is controlled by a control signal from the (i−1)th stage for passing a clock pulse from the clock input CK to the output Nn, Pp of the stage. A control signal generating circuits M5, M6; M11, M12 supplies a control signal to the (i+1)th stage and is inhibited from supplying further control signals in response to a control signal from the (i+2)th stage, where 1<i<(N−1).
    Type: Grant
    Filed: October 26, 1999
    Date of Patent: April 10, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Graham A. Cairns, Michael J. Brownlow
  • Patent number: 6211714
    Abstract: A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: April 3, 2001
    Assignees: Sun Microsystems, Inc.
    Inventor: Deog-Kyoon Jeong
  • Patent number: 6208189
    Abstract: A method and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream of an imaging system. The method includes the steps of delta-sigma modulating an input analog signal of the imaging system at a frequency above the Nyquist frequency of the input analog signal to generate a digital sample stream and changing a length of the sample stream to delay a portion of the sample stream while maintaining synchronism between a delta-sigma modulator and a demodulator of the system.
    Type: Grant
    Filed: July 20, 1999
    Date of Patent: March 27, 2001
    Assignees: The Regents of the University of Michigan, Q-Dot, Inc.
    Inventors: Steven R. Freeman, Matthew O'Donnell, Thomas E. Linnenbrink, Marc A. Morin, Marshall K. Quick, Charles S. Desilets
  • Patent number: 6204713
    Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Janice M. Adams, Keith M. Carrig, Roger P. Gregor, Daniel R. Menard
  • Patent number: 6204712
    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: March 20, 2001
    Assignee: Cisco Technology, Inc.
    Inventor: Sergio D. Camerlo