Abstract: A system for converting between parallel data and serial data is described. In the system, individual bits of the parallel data are latched into individual registers. Each register is coupled to a corresponding AND gate which is also connected to receive phased clock signals. The output terminals of the AND gates are connected to an OR gate. Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Abstract: A method and apparatus are provided for reducing distortion in a dynamically delayed digital sample stream of an imaging system. The method includes the steps of delta-sigma modulating an input analog signal of the imaging system at a frequency above the Nyquist frequency of the input analog signal to generate a digital sample stream and changing a length of the sample stream to delay a portion of the sample stream while maintaining synchronism between a delta-sigma modulator and a demodulator of the system.

Abstract: An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract: An integrated circuit includes a first adjustable delay unit to which a first clock signal is fed and a second adjustable delay unit to which a second clock signal is fed. A phase detector is connected to the input and to the output of the first delay unit. A control unit serves for correcting a phase difference obtained by the phase detector and controls the delay time of the first delay unit in a corresponding manner. The control unit additionally sets the delay time of the second delay unit to essentially the same value as that of the first delay unit. Furthermore, the output of the second delay unit is connected to the input of a third adjustable delay unit.

Abstract: A semiconductor integrated circuit is provided which has an internal core area in which a first set of transistors are regularly arranged, and a peripheral area in which a second set of transistors are arranged to constitute input/output circuits. In this semiconductor integrated circuit, the transistors arranged in the peripheral area include a plurality of transistors that are not used to constitute the input/output circuits, and these unused transistors constitute at least one driver for driving at least one of circuits constituted by the transistors arranged in the internal core area.

Abstract: In a synchronous semiconductor memory device including a memory cell array, a burst counter for generating an internal address signal in synchronization with an external clock signal and a decoder for reading out data from the memory cell array according to the internal address signal, an internal clock generation circuit generates an internal clock signal having a frequency equal to 1/2 of the frequency of the external clock signal in synchronization with the external clock signal, and a data output circuit outputs the data read out of the memory cell array in synchronization with both a rising edge and a falling edge of the internal clock signal.

Abstract: A semiconductor device includes a first circuit; a second circuit; and a plurality of data paths for transmitting a signal between the first circuit and the second circuit. Signal delay time periods when transmitting a signal through the plurality of data paths are substantially equal with each other.

Abstract: A comparator compares phases of an input data supplied from an input terminal and a synchronizing clock signal output by a variable counter, and outputting a comparison result signal indicative of any of a "lead", a "lag" and a "non-detection" of the edge of the input data with respect to the up edge of the synchronizing clock signal. A state detector circuit detects the numbers of "leads" and "lags" in comparison result signals output by the comparator, and outputting a state detected signal indicative of any of "the number of leads is larger", "the number of lags is larger" and "the number of leads is equal to the number of lags". A dividing ratio selection circuit outputs a dividing ratio signal indicative of any of a "dividing ratio smaller than a reference dividing ratio", a "dividing ratio greater than the reference dividing ratio" and the "reference dividing ratio", based on the comparison result signals output by the comparator and state detected signals output by the state detector circuit.

Abstract: A bus master controller comprising a plurality of logic modules, each module coupled to a separate bus driver circuit. The logic module operates using a "break-before-make" protocol derived from a finite state machine, delay element and exclusive-OR gate. The finite state machine generates a predetermined sequence that requires an "assert" signal to always be delayed with respect to a "de-assert" signal, thus eliminating the possibility that more than one set of bus drivers will be coupled to the bus at any one time.

Abstract: A timing circuit that utilizes the delay inherent in a clock tree to achieve a desired timing relationship between control or clock signals. The timing circuit is particularly applicable to high speed environments and to asynchronous logic, though it is also applicable to lower speed environments and synchronous logic. A method producing the desired control or clock signals is also disclosed.

Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

Abstract: A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.

Abstract: A global clock forming circuit for forming a global clock signal is set up on an LSI, and global clock signal is distributed on LSI by the double global clock distribution circuits cycled on the LSI in parallel with and in the inverse direction to one another. Based on the time point at the middle point of the transition point of each of the two clock signals transmitted by the global clock distribution circuit, the local clock signals are generated by the local clock generating circuits 4-(i+1), 4-(i+2), 4-j, 4-(k+1), 4-(l+1). The resulting local clock signals are distributed by the local clock distribution circuits 5-(i+1), 5-(i+2), 5-j, 5-(k+1), 5-(l+1). By this procedure, the clock signal distribution circuit can distribute low skew and high speed clock signals on a large scale integrated circuit.

Abstract: A delay circuit device having first and second delay circuits arrays so constructed that an output can be taken out from an arbitrary position of a signal transmission path, discriminating circuits receiving an output from two positions which divide the first delay circuit array into three portions, and three control circuits. The first and second delay circuit arrays are so arranged that the direction of signal transmission paths are opposite to each other. An output of the first delay circuit array is connected to an input of the second delay circuit array through the control circuits in the order from the position near to an input of the first delay circuit array and in the order from the position near to an output of the second delay circuit array. A first signal is supplied to the first delay circuit array, and whether or not the first signal is propagated to the output of the two positions is respectively latched in the discriminating circuits.

Abstract: A three-phase clock signal generation circuit for a source driver of TFT-LCDs. A clock signal generation circuit for LCD driver includes: a divider dividing an external main clock signal by two and generating a division clock signal; a three-phase clock signal generator receiving the division clock signal from the divider and sequentially generating first to third-phase clock signals; and a sampling mode selector receiving the first to third-phase clock signals and in response to an external mode selection signal, sequentially outputting the first to third-phase clock signals as three-phase clock signals or simultaneously outputting one of the first to third-phase clock signals as the three-phase clock signals. The three phase clock signal generator comprises first, second and third phase clock signal generators sequentially generating first, second and third clock signals with the division clock signal, respectively.

Abstract: A clock circuit is used in a semiconductor device having a control block and a macroblock in order to provide synchronous clocks. The clock circuit contains a clock source for generating the clocks; a clock tree, coupled between the clock source and the control block and the macroblock, for relaying the clocks to the control block and the macrobock; and programmable delays coupled between the clock source and the clock tree and between the clock tree and the control block and the macroblock in order to reduce overall clock skew.

Abstract: A synchronous delay circuit of multiplex configuration is disclosed that has a delay time that corresponds to the pulse separation immediately preceding input of the pulse signal. For the purpose of reducing dependence of the delay time differential between the delay signal and the external clock signal upon the external clock signal cycle, the multiplex synchronous delay circuit of this invention is provided with a plurality of synchronous delay circuits; a delay time differential than is smaller that the delay time of each gate section of the delay circuit bank that makes up each of these synchronous delay circuit is arranged at the input/output portion of the signal path of the synchronous delay circuits, and the outputs of these synchronous delay circuits are multiplexed by their logic output.

Abstract: A semiconductor memory device including an operation control circuit for selecting between a single data rate (SDR) mode and a double data rate (DDR) mode. The operation control circuit includes a mode selector for generating a master signal which selects between the SDR and the DDR mode. The operation control circuit also includes a shift register, a repeater, and a pulse generator. When the SDR mode is selected, the shift register generates an output clock signal which changes states every period of the input clock signal. When the DDR mode is selected, the repeater generates an output clock signal which changes states with every state change of the input clock signal. Productivity efficiency is enhanced and production costs are reduced by providing both the SDR and the DDR mode circuitry and the operation control circuit on a single chip.

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract: A pulse generating circuit which has a first and a second delay circuit selectively operable as a delay circuit or a resetting circuit. The delay circuits each has a discharge transistor and a charge transistor in order to fix the potential on its associated node rapidly when operating as a resetting circuit. Even when short pulses are continuously input as an input signal by accident, the circuitry surely outputs a single pulse transitioning at the same time as the first change in the input signal and having a desired duration since the last change in the input signal.

Abstract: A clock driver circuit includes a first and a second clock driver 15a and 15b. In each of these clock drivers, a plurality of main drivers 19(1) through 19(n) have their input nodes and output nodes connected respectively to a first and a second common line 18 and 21. The second common line 21 is connected to a plurality of clock signal supply lines 20(1) through 20(m) which in turn are connected to the clock input nodes of second macro cells 16 each requiring a clock signal. In a test mode, the clock signal supply lines 20a(1) through 20a(m) of the first clock driver 15a are connected respectively to the clock signal supply lines 20b(1) through 20b(m) of the second clock driver 15b by connection means 22. Thus, a clock driver circuit is provided which offers high driving ability with negligible clock skews in both normal mode and test mode.

Abstract: A method and apparatus for distributing clock signals in an integrated circuit is disclosed. In a preferred embodiment, the power grid of the integrated circuit is used to distribute a periodic timing signal, in addition to the power supply voltage, to local areas of the integrated circuit, the local areas having circuitry for extracting a local clock signal from the periodic timing signal. Instead of simply carrying a DC power supply signal, the power grid is provided with a waveform constituting the sum of the DC power supply signal and the periodic signal, and the power grid then supplies all areas of the integrated circuit with this waveform. Local circuits then tap the power grid as needed to extract the periodic signal, from which local clock signals are then generated. In another preferred embodiment, a periodic timing signal is provided in the form of electromagnetic radiation to local areas of the integrated circuit by means of an optical or radio frequency transmitter.

Abstract: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

Abstract: An LSIC includes a clock distributor circuit capable of decreasing the power consumption and suppressing the deviation of the power source potential and the transient current. The circuit includes a plurality of functional blocks including CPU. The CPU conducts a data accessing operation via address and data buses to peripheral blocks. There is also provided a clock supply unit to supply clock signals in which at least one of the clock signals has a phase different from those of the remaining clock signals and the clock signals do not accomplish the setting operation at the same time.

Abstract: The present invention is a clock generator circuit using semiconductor integrated circuits and which has an input logic circuit to which an external clock signal is supplied; a delaying element chain in which a plurality of delay elements connected to the input logic circuit are serially connected together; a plurality of delay element selectors connected to each of the plurality of delay elements, respectively; a loop closing circuit connected to the delay element connected to a specific delay element selector which to a state indicating a selected status and to the input logic circuit, for forming a closed loop between the delay element chain and the input logic circuit; and an external output connected to the input logic circuit.

Abstract: A high resolution clock circuit apparatus and a method of generating a high resolution clock output from a lower resolution clock input utilizes conventional technology. A standard clock generates a clock frequency which is divided by a flip-flop circuit and is applied to a low skew differential clock driver which distributes the clock into a plurality of separate outputs, each output is applied to a different length delay line. The output of each delay line is applied to a latching circuit, such as a low power octal ECL/TTL bidirectional translator. Each of the plurality of delay lines is sampled and a time word is latched when a time measurement is to be made. In this event, a control signal toggles from low to high which latches a digital word representing that subnanosecond interval of time. A shift register also receives the input clock frequency and includes a feedback loop and is applied to the latch circuit.

Abstract: A layout area includes a clock interconnection consisting of an upward interconnection and a downward interconnection. The upward interconnection extends from the output terminal of a clock buffer which receives an external clock signal to a turning point while passing along the vicinity of a plurality of flip-flops. The downward interconnection extends from the turning point to a free end, reversing along the upward interconnection. Clock branch circuits are provided in the vicinity of the flip-flops. The clock branch circuits have a function of letting a third clock signal make a transition when the sum of the time integral of a first clock signal on the upward interconnection and the time integral of a second clock signal on the downward interconnection has become equal to the time integral for one pulse of one of the first clock signal and the second clock signal.

Abstract: A method and an apparatus for optically clocking an integrated circuit in a semiconductor. In one embodiment, a laser is configured to emit infrared laser pulses at a desired clock frequency. The laser pulses are separated into a plurality of split laser pulses, each of which are focused through the back side of a C4 packaged integrated circuit die into P-N junctions distributed throughout the integrated circuit die. Each P-N junction locally generates a photocurrent in response to the split laser beams. Each of the photocurrents are locally converted into voltages and thus into local clock signals, which are used to clock the local area of the integrated circuit. With the presently described optical clocking technique, the local clock signals have extremely low clock skew. The presently described technique may be employed in integrated circuits system-wide, in multi-chip modules, or in an individual integrated circuit.

Abstract: A semiconductor integrated circuit device is provided which includes at least one first functional circuit block which receives an input signal and executes a logical operation to output an output signal as a result. At least one second functional circuit block is connected in parallel with the first functional circuit block. The second functional circuit block also responds to an input signal to execute a logical operation and output an output signal as a result. The first and second functional circuit blocks are connected to one another such that the second functional circuit block will operate synchronously with the first functional circuit block. More specifically, the first functional circuit block is arranged to control an output timing of the second functional circuit block.

Abstract: A multi-phase clock generator for receiving an external clock signal through a PLL and for generating a plurality of internal clock signals differing in phase from each other. The multi-phase clock generator includes two large gates whose outputs are the two internal clock signals, and two latch circuits for controlling the logic gate outputs. The output from the PLL is fed forward to the logic gates so that the rise of one internal clock signal is separated from a prior fall of the other internal clock signal by a period related to the frequency of the PLL output.

Abstract: A method of constructing a planar equal path length clock tree. Prior computer-generated methods of creating low-skew clock trees required that clock sinks be uniformly distributed throughout the circuit. Moreover, the tree produced would often be non-planar, thus increasing layout design complexity and cost. The present invention provides for a method of automatically producing a planar clock tree with equal path lengths from each clock sink to the clock source. A first branch wire is formed between the clock source and the clock sink that is a farthest distance from the clock source. Thereafter, the remaining uncoupled clock sinks are coupled to the clock tree according to a maximum rule and a minimum rule. Thus a planar equal path length clock tree is formed. The planar equal path length clock tree is transformed in to a rectilinear clock tree, including horizontal and vertical wires, by using a line search algorithm.

Abstract: An internal clock generating circuit for data output buffers of a synchronous DRAM device, which produces an internal clock with reference to either the positive edge or the negative edge of the system clock CLK by comparing the reference time t.sub.CLref(OH) for insuring a low level time tCL of the system clock CLK and output hold time t.sub.OH, and which can sufficiently insure the data output setup time t.sub.OS and data output hold time t.sub.OH regardless of the frequency of the system clock by making the generation points of the internal clock to be varied depending on the frequency of the system clock.

Abstract: A method and apparatus for analyzing each microinstruction in a microinstruction-based electronic circuit having a plurality of registers to determine which registers in a processing cycle are not involved in the processing cycle, and preventing those registers from being clocked during such processing cycle. Hence, inactive registers during a processing cycle do not consume power at the level of active registers, thus lowering overall power usage by any system employing such gated-clock registers.

Abstract: A power efficient implementation of a single-pulse generator requiring less chip area and fewer circuit devices.

Abstract: In a clock signal control circuit of a semiconductor device, a first clock signal is externally supplied to a first terminal of the semiconductor device in an external clock signal mode. In an external element using mode, a second clock signal is generated on said first terminal by a clocked inverter and a self-biasing resistor composed of a P-channel MOS transistor and N-channel MOS transistor, using elements externally connected between the first terminal and a second terminal of the semiconductor device. The clock signal on said second terminal in the external clock signal mode or the external element using mode is supplied to the internal circuit of the semiconductor device using a Schnmitt trigger type of logic gate. In the external clock signal mode, the clocked inverter and the self-biasing resistor are turned off such that the generation of the second clock signal is inhibited. Further, in a clock signal stop mode, the supply of the clock signal is inhibited.

Abstract: A single-phase clocking scheme for use in a VLSI chip having a plurality of localized logic blocks implemented thereon is presented. The present invention includes a first level global clock buffer for receiving an external global clock and producing a first level global clock. A plurality of second level clock buffers, one corresponding to each localized logic block, receive the first level global clock via protected equal length lines, and each produce a respective second level global clock. Each of the localized logic blocks include a plurality of third level clock buffers, wherein each third level clock buffer receives the second level global clock of its respective localized logic block, and each produces a third level local clock. The third level local clock buffers within each localized logic block generate different clocking schemes from each of the other third level local clock buffers contained within the same localized block.

Abstract: A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers and a plurality of external I/O clock generators, wherein the external I/O clock generators generate external I/O clocks signals using circuitry identical to the data drivers except for a slight increase in the channel length of the pre-driver and driver transistors. These transistors control the transition time of the external I/O clock output node. By outputting data signals in the I/O clock domain and using the external I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals transition before the transitions of the external I/O clock signals regardless of process induced signal variations.

Abstract: A clock generator circuit for providing a clock signal to a dual-edged D-type flip-flop, enabling the flip-flop to be dual edged, single edged, or to enable a user to provide clock edge selection, asynchronous clocking, clock enabling, or a mixture of different type clock signals. The clock generator circuit includes inputs receiving first and second enables signals and a clock signal. The clock generator circuit further includes circuitry to provides an output clock signal which transitions when a rising edge of a pulse of the clock signal is received when the first clock signal is enabled, or if a falling edge of a pulse of the clock signal is received when the second clock signal is enabled.

Abstract: A system for convening between parallel data and serial data is described. In the system (b 10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is convened into serial data.

Abstract: Several users emit their own selection signal and clock signal to their respective selection circuits. The selection circuits send selection criteria to all other selection circuits and the clock switching stage. The selection circuit sends an activity signal to a digital circuit based on the allocated user's selection signal, the selection criteria of all the other selection circuits and the selected clock signal.

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.

Abstract: A pulse generator for use in generating pulses at different locations within a circuit has a first circuit 501 for a time dependent operation after receipt of a first input pulse and a second circuit 502 for carrying out a time dependent operation after receipt of a second input pulse after the first input pulse. A third circuit 503 is responsive to each of the first and second circuits 501,502 reaching respective predetermined conditions so that an output pulse is produced by the third circuit 503 at a time dependent on the average durations of operation of the first and second circuits 501 and 502.

Abstract: A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.

Abstract: A system clock generating circuit for supplying a system clock to a microproeessor, includes a first oscillator for generating a main clock, and a second oscillator for generating a sub clock which is lower in frequency than the main clock. A twin-clock control circuit receives the main clock and the sub clock and is controlled by the microprocessor. When the microprocessor is in an ordinary operating condition, the twin-clock control circuit generates a (n)-phase system clock which is composed of (n) clocks for each one instruction cycle, where "n" is a positive even number. When the microprocessor is in an electric power saving mode, the twin-clock control circuit also generates a (n/m)-phase system clock which is composed of (n/m) clocks for each one instruction cycle, where "m" is a positive even number but is smaller than "n".

Abstract: A semiconductor integrated circuit device is equipped with a series of data handling stages, at least one of which includes a plurality of functional blocks arranged in parallel, a connecting means for connecting the functional blocks to functional blocks in a subsequent data handling stage, and a detection means for detecting data flow along a first connection in the connecting means. The detection means is included within a control means which controls data flow through at least one other connection in the connecting means based on the detection of data flow through the first connection in the connecting means.

Abstract: A quadrature oscillator is provided constructed of NOR gates in the manner of a non-linear circuit which is inherently unstable and which cycles sequentially through four distinct states at a rate determined by the constitution of the NOR gates. The quadrature oscillator includes first and second stages that each include first and second NOR gates. The output of the first NOR gate of the first stage is connected as an input to the second NOR gate of each of the first and second stages. The output of the second NOR gate of the first stage is connected as an input to the first NOR gate of each of the first and second stages. The output of the first NOR gate of the second stage is connected as an input to the first NOR gate of the first stage and the second NOR gate of the second stage. The output of the second NOR gate of the second stage is connected as and input to the second NOR gate of the first stage and the first NOR gate of the second stage.

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.

Abstract: A circuit arrangement for delaying a useful signal which is stored in the form of time-discrete signal samples in a row of storage devices at time intervals which are determined by a clock signal and is read therefrom after expiration of a selectable delay time. Each storage device is connectable, via a respective input circuit to a useful signal input and, via a respective output circuit, to a useful signal output.

Abstract: In an address transition detection summing circuit, the varying address signal pulse widths can result in output signals from the address transition detection summing circuit which can compromise the performance of the associated memory circuitry. A parallel signal delay path, activated by the leading edge of the address signal, is incorporated in the address transition detection summing circuit and a logic ANDing element so that not only is the signal resulting from the trailing edge of the address signal applied to the logic ANDing element, but the trailing edge signal from the parallel signal delay path must be applied to the logic ANDing element before the trailing edge of the output pulse from the address transition detection summing circuit is generated. In the manner, an address transition always results in an output signal pulse having a preselected minimum width.