Single Clock Output With Multiple Inputs Patents (Class 327/298)
  • Patent number: 10305492
    Abstract: The frequency of a clock signal is compared to a predetermined range. If the measured frequency is outside the range, a system controller determines if a current operating state of the overall system allows for the internal clock to be adjusted back into compliance. If the controller determines that the current system state allows for the change, then a control signal to the internal clock signal source is changed by the smallest increment available, either to increase or decrease the frequency. If the internal clock signal is out of the desired range, and the system controller does not decide to modify the frequency, the controller may increase the size of the range by decreasing the lower bound and/or increasing the upper bound.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 28, 2019
    Assignee: Raytheon Company
    Inventors: Andrew L. Martin, David W. Palmer
  • Patent number: 10127970
    Abstract: A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Fifield, Dale E. Pontius
  • Patent number: 10128811
    Abstract: The disclosure relates to a method for operating a selective switching device for signals, a related selective switching device, and a message transmission system having the selective switching device. An embodiment of the method includes the following steps, not necessarily in this order: determining a current temperature in the region of the selective switching device; determining a signal shift of the selective switching device due to the current temperature; adding the signal shift to an input signal of the selective switching device as to receive a compensated signal for which the signal shift due to the current temperature is compensated; and removing the signal shift from an output signal of the selective switching device as to receive a corrected signal for which the compensation is corrected.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 13, 2018
    Assignee: TESAT-SPACECOM GMBH & CO KG
    Inventor: Erich Auer
  • Patent number: 9977459
    Abstract: A clock generating circuit includes: a generating circuit, a reference circuit and an adjusting circuit. The generating circuit generates a clock signal. The reference circuit is coupled to the generating circuit, and generates a reference signal to the generating circuit according to the clock signal, wherein a frequency of the clock signal is varied according to the reference signal when the reference signal is received by the generating circuit. The adjusting circuit generates an adjusting signal and a trigger signal to the generating circuit, wherein the generating circuit refers to the trigger signal to decide whether to adjust the clock signal frequency according to the adjusting signal.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: May 22, 2018
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Chin-Tung Chan, Szu-Chun Tsao, Deng-Yao Shih
  • Patent number: 9584144
    Abstract: A clock generator includes: a first input to receive a global clock signal; a second input to receive a completion signal; a third input to receive differential outputs in a conversion cycle from a comparator; and a logic circuit configured to generate a control clock signal based at least in part on the global clock signal and the differential outputs, and to provide the control clock signal to the comparator for a next conversion cycle; and wherein the logic circuit is also configured to disable the control clock signal in response to the completion signal indicating a completion of required conversion cycles in a conversion phase.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: February 28, 2017
    Assignee: XILINX, INC.
    Inventors: Lei Zhou, Hiva Hedayati
  • Patent number: 9571070
    Abstract: A mobile communication device includes an analog clock and a digital clock circuit. The analog clock circuit is configured to generate an oscillating output. The digital clock circuit is configured to generate a digital clock output having a frequency that is substantially equal to the frequency of the oscillating output.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: February 14, 2017
    Assignee: BlackBerry Limited
    Inventors: Mark A. J. Carragher, John William Wynen
  • Patent number: 9438165
    Abstract: A method includes using a current source to provide a charging current to a capacitor of a resistor-capacitor (RC) tank of an RC oscillator. The method includes using a resistor of the current source as a resistor for the RC tank.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: September 6, 2016
    Assignee: Silicon Laboratories Inc.
    Inventors: Matthew R. Powell, Axel Thomsen, Nicholas M. Atkinson
  • Patent number: 9385696
    Abstract: Various aspects provide for generating a clock signal for a hold latch. A latch pulse generator generates a pulse clock signal based on a first clock signal associated with a first flip-flop component and a second clock signal associated with a second flip-flop component. A hold latch component receives the pulse clock signal generated by the latch pulse generator and generates a data signal that is transmitted to the second flip-flop component.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: July 5, 2016
    Assignee: APPLIED MICRO CIRCUITS CORPORATION
    Inventor: Arun Jangity
  • Patent number: 9360884
    Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: June 7, 2016
    Assignee: Altera Corporation
    Inventors: David Galloway, David Lewis, Ryan Fung, Valavan Manohararajah, Jeffrey Christopher Chromczak
  • Patent number: 9360883
    Abstract: A fully digital glitch-free clock multiplexer includes a monitoring circuit that automatically switches to a newly selected clock, after a defined time period, from a currently selected clock, when the currently selected clock is absent. A maximum time limit is calculated based on a min and max clock frequency ratio. The monitoring circuit operates only when the clock is being switched. This provides flexibility to software to switch the clock any time whether or not the current clock is present, and prevents the system from hanging in the absence of the clock.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Arun Kumar Barman, Vivek Sharma
  • Patent number: 9218030
    Abstract: A programming interface and method of operating a programming interface use a system clock input, an asynchronous reset input, and an interface control input. The method selectively controls multiplexed coupling of a source register to a destination register and the destination register to a buffer register. The multiplexed coupling of the destination register to the buffer register reduces the possibility of the buffer register being corrupted when an asynchronous reset signal is applied to the programming interface. Problems associated with meta-stable asynchronous crossing paths in asynchronous reset programming systems are therefore alleviated.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: December 22, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Arjun Pal Chowdhury, Neha Agarwal, Chandan Gupta, Ankush Sethi
  • Patent number: 9147463
    Abstract: A method for data acquisition in a memory system includes oversampling a data signal and a strobe signal with a multiphase clock having n phases to generate a series of data signals and a series of strobe signals representing a first data series and a first strobe series respectively, generating a second strobe series by edge detection of the first strobe series followed by retiming of the edge detected series, generating a third strobe series by edge adjustment of the second strobe series, wherein the edge adjustment ensures that there are no overlapping edges among the signals of the third strobe series, generating a sample selected series by linear shifting of each signal of the third strobe series by n/2, generating a second data series by retiming the first data series, generating a third data series by sample adjustment of the second data series, wherein the sample adjustment ensures that the third data series is in synchronization with a sampling window of the sample selected series, and determining a
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 29, 2015
    Assignee: MegaChips Corporation
    Inventors: Dinakar Venkata Sarraju, Purushotham Brahmavar Ramakrishna
  • Patent number: 9112489
    Abstract: A sequential logic circuit comprising a first latch component comprising a data input arranged to receive an input signal, a data output arranged to output a current logical state of the first latch component and a clock input arranged to receive a clock signal; the first latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a first logical state, and to comprise a latched state upon the clock signal received thereby comprising a second logical state, and a second latch component comprising a data input arranged to receive an input signal, a data output operably coupled to an output of the sequential logic circuit and arranged to output a current state of the second latch component and a clock input arranged to receive a clock signal; the second latch component being arranged to comprise a transparent state upon the clock signal received thereby comprising a second logical state, and to comprise a latched state upon the clock signal received thereby c
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: August 18, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Priel, Leonid Fleshel, Anton Rozen
  • Patent number: 9104609
    Abstract: The time in the chipset of backup resources is synchronized easily at the system time. An information processing apparatus including: an operational chipset which includes a first Real Time Clock (RTC); a backup chipset which includes a second RTC: a third RTC which times system time; a difference time calculation unit which calculates a difference time between a system time periodically notified of from the first RTC of the operational chipset and the system time which the third RTC times; a holding unit which holds the difference time; a calculation unit which calculates a temporary system time which is set to the second RTC of the backup chipset to which a chipset switching operated, based on the system time of the third RTC and the difference time at the time of the chipset switching; and a configuration unit which sets the temporary system time to the second RTC of the backup chipset.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: August 11, 2015
    Assignee: NEC CORPORATION
    Inventor: Hiroki Arai
  • Patent number: 9041451
    Abstract: A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Cyclos Semiconductor, Inc.
    Inventors: Marios C. Papaefthymiou, Alexander Ishii
  • Patent number: 9007115
    Abstract: An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: April 14, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hoon Choi
  • Publication number: 20150097516
    Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving providing a clock signal. As consistent with one or more embodiments herein, a sawtooth waveform signal is generated in a manner that facilitates low power operation. In some implementations, the sawtooth waveform signal is generated using an oscillator that operates without necessarily employing R-C circuits and/or without rail-to-rail voltage supply, such as via a nonlinear oscillator. The sawtooth waveform signal is used to generate a trapezoidal waveform signal, and a clock signal is generated using the trapeziodal waveform signal.
    Type: Application
    Filed: October 8, 2013
    Publication date: April 9, 2015
    Applicant: NXP B.V.
    Inventors: Chiahung Su, Madan Mohan Reddy Vemula
  • Publication number: 20150070068
    Abstract: An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock.
    Type: Application
    Filed: December 13, 2013
    Publication date: March 12, 2015
    Applicant: SK hynix Inc.
    Inventors: Jin-Woo LEE, Hyun-Chul CHO
  • Patent number: 8975972
    Abstract: An oscillator system includes a first oscillator, a second oscillator, and a changeover component. The first oscillator is configured to generate a first signal at a selected frequency. The second oscillator is configured to generate a second signal at about the selected frequency. The changeover component is configured to generate a changeover output signal according to the first signal and the second signal.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Michael Aichner, Mattias Welponer Bachmayer, Martin Flatscher
  • Publication number: 20150067209
    Abstract: A system and method for efficient detection of Low Frequency Periodic Signaling (LFPS) input signals. A receiver receives two input differential signals that are LFPS input signals. The receiver increases the common-mode voltage for each of the two input differential signals and determines two polarity opposite differences between the level shifted intermediate differential signals. The differences are used to generate two series of relatively narrow pulses by comparisons with a given threshold. A wide continuous pulse is asserted when an initial pulse among the two series of pulses is detected. The wide continuous pulse is deasserted when a final pulse among the two series of pulses is detected. While the wide continuous pulse is asserted, control logic is awakend and performs a Universal Serial Bus (USB) protocol for processing data on the input differential signals.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 5, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Xin Liu, Hai Nguyen
  • Publication number: 20150061628
    Abstract: A power converter and a clock module employed for providing a clock signal to the power converter. The power converter converts an input voltage to an output voltage based on at least the switching on and off of a main switch. The clock module monitors a deviation of the output voltage from its desired value and compares the deviation with a predetermined threshold window to provide a clock control signal. The clock module further regulates the clock signal in response to the clock control signal.
    Type: Application
    Filed: September 5, 2014
    Publication date: March 5, 2015
    Inventors: James Nguyen, Yike Li
  • Patent number: 8970277
    Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Koazechi, Tatsufumi Kurokawa
  • Patent number: 8970267
    Abstract: This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: March 3, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Abhijeet Ashok Chachad, Ramakrishnan Venkatasubramanian
  • Patent number: 8963603
    Abstract: A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: February 24, 2015
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shih-Hsiun Huang, Shian-Ru Lin
  • Patent number: 8963604
    Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Eric Booth, Tyler J. Gomm, Kallol Mazumder, Scott E. Smith, John F. Schreck
  • Patent number: 8957704
    Abstract: A digital phase selector circuit that switches an output clock between N input clock phases is described. The phase selector utilizes a special output mux and switches clock phases during a safe zone to avoid glitches. The phase selector is used in the feedback path of a PLL to implement functions such as spread spectrum or fractional reference clocks. An example with N=4 and an optimized latch mux is shown.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 17, 2015
    Assignee: Synopsys, Inc.
    Inventors: Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8937500
    Abstract: This document discusses, among other things, a delay circuit, in which a first register is written with a delay reference code, a second register is written with a delay factor, a control unit determines a corresponding delay ratio in a storage unit based on the delay factor in the second register, and sends the determined delay ratio to a first digital timing unit, the first digital timing unit determines a delay reference time based on the delay reference code in the first register, multiplies the delay reference time by the delay ratio to result in a desired delay time, and generates a delay.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 20, 2015
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ming Chuen Alvan Lam, Weiming Sun, Emma Wang, Peng Zhu
  • Publication number: 20150002203
    Abstract: An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.
    Type: Application
    Filed: September 18, 2014
    Publication date: January 1, 2015
    Inventor: Hoon CHOI
  • Patent number: 8917133
    Abstract: The clock generation method contains the following steps. In a pulse recognition step, an input pulse signal is first filtered to remove a shorter signal. Then, a width digitization calculation is conducted on the remaining pulse signal. Based on the width digitization calculation, a signal is recorded and a period of the recorded signal is determined. The value of the period is delivered to a gain module. In a step for verifying the input value to D/A converter, two values are input to a D/A converter from the gain module, and the output from the D/A converter is delivered to an oscillator. The gain module determines a desired input value from the gain module to the D/A converter. In a pulse generation step, the gain module inputs the desired input value to the D/A converter which in turn delivers to the oscillator for the generation of a corresponding clock.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: December 23, 2014
    Assignee: M31 Technology Corporation
    Inventors: Chih-Jou Lin, Yuan-Hsun Chang, Cheng-Ji Chang, Ting-Chun Huang, Yu-Sheng Yi
  • Patent number: 8917132
    Abstract: Apparatuses, methods, and delay circuits for delaying signals are described. An example apparatus includes a fine delay circuit configured to provide an output signal based on a ratio of a first input signal and a second input signal. The fine delay circuit including a phase mixer circuit including first signal drivers configured to receive the first input signal. The fine delay circuit further including second signal drivers configured to receive the second input signal, where at least two of the first signal drivers have different drive strengths and at least two of the second signal drivers have different drive strengths.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yantao Ma, Tyler Gomm
  • Patent number: 8912830
    Abstract: A method and apparatus for atomic frequency and voltage changes in the processor. In one embodiment of the invention, the atomic frequency and voltage changes in the processor is feasible due to the enabling technology of fully integrated voltage regulators (FIVR) that are integrated in the processor. FIVR allows independent configuration of each core in the processor and the configuration includes, but is not limited to, voltage setting, frequency setting, clock setting and other parameters that affects the power consumption of each core.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Shaun M. Conrad, Jeremy J. Shrall
  • Publication number: 20140361915
    Abstract: The invention concerns a circuit comprising: a first transistor (202) having a first main current node coupled to a first voltage signal (CNVDD), a control node coupled to a second voltage signal (CPVDD) and a second main current node coupled to an output node (206) of the circuit; a second transistor (204) having a first main current node coupled to a third voltage signal (CPGND), a control node coupled to a fourth voltage signal (CPGND) and a second main current node coupled to said output node of the circuit; and circuitry (210, 212) adapted to generate said first, second, third and fourth voltage signals based on a pair of differential input signals (CP, CN), wherein said first and second voltage signals are both referenced to a first supply voltage (VDD) and wherein said third and fourth voltage signals are both referenced to a second supply voltage (GND).
    Type: Application
    Filed: June 3, 2014
    Publication date: December 11, 2014
    Inventors: Stéphane LE TUAL, Pratap Narayan SINGH
  • Patent number: 8890596
    Abstract: A clock signal generating apparatus includes a first frequency generating circuit, a second frequency generating circuit, and an output circuit. The first frequency generating circuit is arranged to generate a first clock signal having a first oscillation frequency. The second frequency generating circuit is arranged to generate a second clock signal having a second oscillation frequency. The output circuit is arranged to receive the first and second clock signals. The output circuit is able to output one of the first and second clock signals as an output clock signal according to an oscillation frequency control setting provided by an external bounding pad included within the clock signal generating apparatus.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: November 18, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Xiao-Fei Chen
  • Patent number: 8890595
    Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: November 18, 2014
    Assignee: Fmax Technologies, Inc.
    Inventor: Iain Ross Mactaggart
  • Patent number: 8866525
    Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: October 21, 2014
    Assignee: Microchip Technology Incorporated
    Inventors: Bryan Kris, John Day, Alex Dumais, Stephen Bowling
  • Patent number: 8860468
    Abstract: A clock multiplexer includes first and second input stages for outputting first and second clock signals, respectively. The first and second input stages each include a flip-flop, a latch and a first logic gate. Reset terminals of the flip-flops receive a select signal based on which the first and second input stages output the first and second clock signals. A second logic gate is connected to the first and second input stages for selectively providing the first and second clock signals as an output clock signal.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amitesh Khandelwal, Gaurav Jain, Abhishek Mahajan
  • Publication number: 20140300400
    Abstract: A comparator used in a clock signal generation circuit has first and second input transistors coupled to input signals of the comparator. First and second hysteresis transistors are coupled between the input transistors and an output stage of the comparator, and apply hysteresis to a comparison of the input signals. First and second hysteresis control transistors are coupled between the input transistors and the hysteresis transistors to isolate the hysteresis transistors from the input transistors under control of a hysteresis enable signal.
    Type: Application
    Filed: February 26, 2014
    Publication date: October 9, 2014
    Inventors: Wenzhong Zhang, Chris C. Dao, Jehoda Refaeli, Yi Zhao
  • Patent number: 8854100
    Abstract: A clock driver for a resonant clock network includes a delay circuit that receives and supplies a delayed clock signal. A first transistor is coupled to receive a first pulse control signal and supply an output clock node of the clock driver. An asserted edge of the first control signal is responsive to the falling edge of the delayed clock signal. A second transistor is coupled to receive a second control signal and to supply the output clock node of the clock driver. An asserted edge of the second control signal is responsive to a rising edge of the delayed clock signal.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger, Srikanth Arekapudi
  • Patent number: 8847653
    Abstract: A dither control circuit includes a pseudo random number generator, which generates a pseudo random number sequence in response to a frequency-divided clock signal, and a dither circuit which dithers an input digital code by using at least one output bit of the pseudo random number sequence and outputs a dithered digital code corresponding to a result of the dithering. The dither circuit may output, as the dithered digital code, a digital code corresponding to a sum of or a difference between the input digital code and the input digital code based on the at least one output bit. The dithered digital code may be input to an accumulator which operates in-sync with the frequency-divided clock signal.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Phil Hong, Jenlung Liu, Nan Xing, Jae Jin Park
  • Publication number: 20140253204
    Abstract: A clock signal generator module arranged to generate at least one clock signal for at least one functional module is described. The clock signal generator module comprises a first clock source component associated with at least one functional module, at least one further clock source component associated with the at least one functional module, and at least one management unit arranged to controllably enable signal generation by the first and at least one further clock source components in accordance with at least one operating characteristic of the at least one functional module associated therewith.
    Type: Application
    Filed: November 21, 2011
    Publication date: September 11, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Yossi Shoshany
  • Patent number: 8810300
    Abstract: Embodiments provide systems and methods for dynamically regulating the clock frequency of an integrated circuit (IC) based on the IC supply voltage. By doing so, the clock frequency is no longer constrained by a worst-case voltage level, and a higher effective clock frequency can be supported, increasing the IC performance. Embodiments include a wave clocking system which uses a plurality of delay chains configured to match substantially the delays of respective logic paths of the IC. As the delays of the logic paths vary with supply voltage and temperature changes, the delay chains matched to the logic paths experience substantially similar changes and are used to regulate the clock frequency of the IC.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 19, 2014
    Assignee: Broadcom Corporation
    Inventor: Tim Sippel
  • Patent number: 8786348
    Abstract: A control circuit of a light-emitting element comprises a rectifying unit which full-wave rectifies an alternating current power supply, a clock generator which generates and outputs a clock signal (CLK), a first comparator which compares a comparison voltage (CS) corresponding to a current flowing to the light-emitting element and a reference voltage (REF), and a switching element which is set to an ON state in synchronization with the clock signal (CLK) and which is set to an OFF state when the comparison voltage (CS) becomes greater than the reference voltage (REF) at the first comparator, to switch the current flowing to the light-emitting element. In this structure, a period of the clock signal (CLK) generated in the clock generator is varied, to reduce or inhibit noise.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: July 22, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shuhei Kawai, Yoshio Fujimura
  • Patent number: 8779824
    Abstract: Clock signals are distributed on a chip by applying an oscillating magnetic field to the chip. Local clock generation circuits including magnetic field sensors are distributed around the chip and are coupled to local clocked circuitry on the chip. The magnetic field sensors may include clock magnetic tunnel junctions (MTJs) in which a magnetic orientation of the free layer is free to rotate in the free layer plane in response to the applied magnetic field. The MTJ resistance alternates between a high resistance value and a low resistance value as the free layer magnetization rotates. Clock generation circuitry coupled to the clock MTJs senses voltage oscillations caused by the alternating resistance of the clock MTJs. The clock generation circuitry includes amplifiers, which convert the sensed voltage into local clock signals.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: July 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wenqing Wu, Kendrick H. Yuen, David W. Hansquine, Robert P. Gilmore, Jeff A. Levin
  • Patent number: 8779825
    Abstract: A delay element delays an output signal Dt from an arithmetic circuit and outputs a delayed signal Dd. An XOR element compares the output signal Dt with the delayed signal Dd, and outputs an XORout signal with the signal value “0” when the signals match each other, and outputs an XORout signal with the signal value “1” when the signals do not match each other. In a flip-flop, when the signal value of the XORout signal at the rise of a clock of a clock signal CK is “0”, the output signal Dt is output from a flip-flop, and when the signal value of the XORout signal at the rise of the clock becomes “1” even once, a fixed value of the signal value “0” continues to be output.
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuneo Sato, Teruyoshi Yamaguchi
  • Patent number: 8773188
    Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: HaoQiong Chen, Wen Zhu
  • Publication number: 20140176217
    Abstract: A method includes providing a first local oscillator signal having a first duty cycle to a first mixer unit and providing a second local oscillator signal having a second duty cycle to a second mixer unit. At least one of the first duty cycle or the second duty cycle is greater than fifty percent. A frequency of the first local oscillator signal approximately equals a frequency of the second local oscillator signal. The method may also include generating a modulated output signal based on an output signal of the first mixer unit and based on an output signal of the second mixer unit.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: QUALCOMM, INCORPORATED
    Inventors: Saihua Lin, Roger Brockenbrough
  • Publication number: 20140176218
    Abstract: Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.
    Type: Application
    Filed: November 20, 2013
    Publication date: June 26, 2014
    Applicant: ON-BRIGHT ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Liqiang Zhu, Lieyi Fang
  • Patent number: 8760197
    Abstract: A system, method, and computer program product are provided for the switching of clock signals. A clock network switching system includes a first re-synchronization circuit coupled to a first input clock, and a second re-synchronization circuit coupled to a second input clock. There is also an input select decoder coupled to the first and second re-synchronization circuit that can dynamically select either the first or the second input clock to be active. When an input clock is selected to be active, the re-synchronization circuit associated with the selected input clock generates an output clock synchronized with the selected input clock where both a high pulse width and a low pulse width of the output clock are not less than those of the selected input clock.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: June 24, 2014
    Assignee: Broadcom Corporation
    Inventor: Iraj Motabar
  • Patent number: 8754697
    Abstract: A dual mode frequency synthesizer circuit including: a DDS or PLL (204) for receiving an input clock (202) and generating an output clock (206), in a high resolution mode; and an RF switch (210) having its output (208) coupled to the output of the DDS or PLL, a first input (216) for receiving a first injection low phase-noise clock (F1), a second input (218) for receiving a second injection low phase-noise clock (F2), and a control input (222) for selecting one of the first or second injection low phase-noise clocks for a low phase-noise mode.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: June 17, 2014
    Assignee: Raytheon Company
    Inventor: Michael Robert Patrizi
  • Publication number: 20140159792
    Abstract: A voltage generation circuit includes an oscillator configured to output a first period signal and a second period signal in response to a detection signal; a period signal select unit configured to receive the first and second period signals and output one of the first and second period signals as an additional period signal in response to a control signal; and a charge pump unit configured to charge-pump an input voltage in response to the first period signal and the additional period signal and generate a power supply voltage.
    Type: Application
    Filed: August 2, 2013
    Publication date: June 12, 2014
    Applicant: SK hynix Inc.
    Inventor: Hyun Sik KIM