Abstract: Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.

Abstract: A clock generating apparatus for use in an electronic device, such as a radio or other audio device, which generates a clock signal based on an AC input signal received, for example, from a wall outlet. The clock generating apparatus detects and monitors the frequency of the AC input signal and automatically adjusts the clock signal based on the detected frequency of the AC input signal.

Abstract: In a system in which a plurality of modules have different operational rates and a common clock controlling data delivery to the modules, the rate at which data is delivered to the system can be maximized using a return clock signal to prevent the loss of synchronization of the modules. A clocking error signal may be produced when the clock signal makes a transition to a logic state that may cause loss of synchronization between the modules.

Abstract: An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: Generation of multiple clocks having a synchronized phase relationship may reduce the size, complexity, power consumption, jitter and cost of circuitry while improving its functionality, performance, reliability and fault coverage. A multiple frequency clock generator may comprise an independent digital control oscillator (DCO) for generating a first clock and dependent DCOs for generating additional clocks that align at a common multiple frequency with the first clock with or without adjustment thereof. The independent and dependent DCOs may generate the first and additional clocks from a delay lock loop (DLL) by selecting a sequence of tap select signals. Tap select signals may be adjusted to maintain a desired phase and/or frequency of the first and additional clocks. Dependent DCOs may generate sequences of tap select signals based on the sequence of tap select signals generated by the independent DCO to incorporate adjustments, e.g., PLL error corrections.

Abstract: Methods and apparatuses provide a clocked digital device having dynamically adjustable operating characteristics. The digital device comprises a digital clock management (“DCM”) circuit in which the amount of delay between receipt of an active edge of a clock signal at the input of the DCM circuit and appearance of an active edge of another clock signal at the output of the DCM circuit depends on a phase adjustment signal applied to the DCM circuit's phase adjust input. A phase adjustment circuit provides the phase adjustment signal to the DCM circuit's phase adjust input for controlling the amount of the delay between the clock signal at the input of the DCM circuit and the clock signal at the output of the DCM circuit.

Abstract: A clock signal generating circuit includes a main clock buffering unit and a sub clock buffering unit. The main clock buffering unit is capable of generating both a differential clock signal pair and a single clock signal. The main clock buffering unit selectively outputs either the differential clock signal pair or the single clock signal depending upon the frequency of an external clock signal. The sub clock buffering unit receives the output of the main clock buffering unit and generates first and second clock signals. The operation of the sub clock buffering unit depends upon whether the differential clock signal pair or the single clock signal is output by the main clock buffering unit.

Abstract: The present invention is applicable to an electronic device including a master, a slave, a bus coupling the master and the slave and a clock generator for providing a system clock to the master and slave. The clock generator determines whether the received data is correct on a cycle-by-cycle basis. The clock generator suppresses an edge of a next clock cycle of the system clock signal if the data is not to be correct. The clock generator allows the edge of a next clock cycle of the system clock signal if the data is correct.

Abstract: A method of changing an operating performance point of an integrated circuit including detecting a need to change the operating performance point of the integrated circuit to a new operating performance point. The method also includes changing a voltage of the integrated circuit to correspond with the new operating performance point, changing a maximal receiver clock frequency value to correspond with the new operating performance point, exporting the maximal receiver clock frequency value to a distant integrated circuit, and receiving an acknowledgement of the changed maximal receiver clock frequency value from the distant integrated circuit.

Abstract: An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

Abstract: It is an object of the invention to provide a variable delay apparatus in which, even immediately after the delay amount of the variable delay apparatus is changed, a signal of a timing that is different from a set delay amount is not output. The variable delay apparatus of the invention includes: a variable delay block 108 having N (N is a natural number) delay elements 101a to 101n, and N selectors 102a to 102n; a variable delay block 109 having N delay elements 103a to 103n, and N selectors 104a to 104n; and a selector 107. After selection signals 105a to 105n and 106a to 106n are changed, and after an output timing of a delay amount set by the variable delay blocks 108, 109 is attained, the signal to be output is switched by the selector 107, thereby avoiding a situation where, immediately after the delay amount is changed, a signal of a timing that is different from the set delay amount is output as an output signal.

Abstract: A disclosed embodiment is a circuit for producing a core clock from a system clock so that a core clock cycle is independent of a duty cycle of the system clock. The circuit comprises a system clock receiving sub-circuit for generating a first rising edge of the core clock, a core clock falling edge generation sub-circuit responsive to every rising edge of the core clock, and a self-triggering sub-circuit to trigger a second rising edge of the core clock so as to cause the core clock cycle to be independent of the system clock duty cycle. In one embodiment, the first core clock rising edge may be triggered in response to an initial system clock rising edge. In another embodiment, the first core clock rising edge may be triggered in response to an initial system clock falling edge. The core clock frequency may be twice the frequency of the system clock.

Abstract: A clock signal generating arrangement for a communication device generates a system clock signal at an output for use as a timing reference. The clock signal generating arrangement comprises a reference clock generator for generating a reference clock signal, a main clock generator for generating a main clock signal having a greater accuracy than the reference clock signal, a clock adjust circuit coupled to the reference clock generator for generating a compensated reference clock signal to compensate for error in the reference clock signal and a clock signal selector coupled to the reference clock generator the main clock generator and the clock adjust circuit.

Abstract: Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14).

Abstract: A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.

Abstract: A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

Abstract: There is provided a jitter injection apparatus that generates an output signal having an injected jitter. The jitter injection apparatus includes a first oscillator that generates a first periodic signal, a second oscillator that generates a second periodic signal having a period different from that of the first periodic signal, and a switching section that switches which of the first periodic signal and the second periodic signal is output at every predetermined timing and outputs the switched periodic signal as the output signal.

Abstract: A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal.

Abstract: A clock control circuit comprises a control signal generating unit configured to generate a control signal disabled in a predetermined state while in an active mode, and a clock transferring unit configured to transfer an external clock in response to the control signal.

Abstract: A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

Abstract: A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse.

Abstract: Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°<X<180°). The phase amounts X of the n level shifters (LS0 to LS7) are equal to each other.

Abstract: A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations.

Abstract: Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components.

Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals±1).

Abstract: A multiphase clock circuit in which bit errors are propagated only for the duration of the clock cycle in which a bit error occurs. The circuit recovers automatically from bit errors and is capable of operating at high frequency with high clock precision. The multiphase clock circuit can generate a plurality of clock pulse streams, each pulse stream at the same clock frequency, with fixed phase relationships among the streams. The multiphase clock circuit includes a master clock signal of frequency fc which is applied to a divide by N frequency divider circuit for producing a base clock signal of fc/N. The base clock signal is sequentially applied to the data input of a series chain of N clocked data flip-flops (DFFs) each of which is simultaneously clocked by a clock signal of frequency fc to produce N clock signals of base frequency fc/N separated from each other by a constant time delay T=1/fc.

Abstract: A circuit configured to correct a duty cycle includes a clock dividing unit configured to delay an input clock signal by a specified delay amount and to generate a plurality of delayed clock signals, a clock selection unit configured to output any one among the plurality of delayed clock signals as a selected delayed clock signal in response to duty ratio information of the input clock signal, an edge control unit configured to generate a falling clock signal by controlling a falling edge of the selected delayed clock signal and to generate a rising clock signal by controlling a falling edge of the input clock signal based on information regarding a difference between lengths of a high duration and a low duration of the input clock signal, and a phase mixing unit for mixing phases of the falling clock signal and the rising clock signal and generating an output clock signal.

Abstract: A semiconductor memory device includes an aligning signal generator, a data aligning unit, a data transmitting controller and a data transmitter. The aligning signal generator receives a data strobe signal to output aligning signals. The data aligning unit aligns a plurality of data pieces input in succession in response to the aligning signals. The data transmitting controller generates a data transmitting signal synchronized with the transition of the aligning signal. The data transmitter transmits an aligned data output from the data aligning unit to a data storage area in response to the data transmitting signal. A method for driving the semiconductor memory device includes aligning data pieces input in succession as parallel data in response to a data strobe signal, generating a data transmitting signal corresponding to transition of the data strobe signal and transmitting the parallel data to a data storage area in response to the data transmitting signal.

Abstract: A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.

Abstract: Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14).

Abstract: An Externally Asynchronous-Internally Clocked (EAIC) system that generates an internal clock signal includes a clock signal control block. The clock signal control block includes a pull-up unit that is activated in response to an input signal used to generate an internal clock signal; a pull-down unit that is activated in response to the input signal used to generate an internal clock signal, and a bypass unit that is provided between the pull-up unit and the pull-down unit, and selectively provides a signal path to the pull-down unit if the pull-down unit is activated and a signal path from the pull-up unit if the pull-up unit is activated.

Abstract: In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively invert and swap the at least one PWM signal with a logic-inverted duty-cycle complement of the at least one PWM signal at discrete time intervals to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit.

Abstract: A spread spectrum clock generator for sequentially modulating a source clock of a fixed frequency with a predetermined frequency range, including: a plurality of first loading units configured to delay clock edges of the source clock by a delay time corresponding to the number of unit delay steps determined by delay step control signals, wherein each of the first loading units comprises a plurality of second loading units each of which is configured to vary a delay value of each unit delay step by changing an inner interconnection configuration thereof in response to unit delay step control signals.

Abstract: A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.

Abstract: The pulse generator comprises: a delay line arranged to receive a digital input signal and to produce a plurality of delay line output signals; first and second pulse generator blocks comprising logic circuitry arranged to generate a plurality of successive first output pulses in response to said different delay line output signals; and pulse combiner circuitry arranged to combine said first output pulses to produce second output pulses. The first pulse generator block is arranged to be responsive to rising edges of said input signal, and the second pulse generator blocks is responsive to falling edges of said input signal. Thus, both rising and falling edges of said input signal are used to create pulses. The device can be used in impulse radio transmitters and receivers.

Abstract: Disclosed is a data output controller that includes an enable signal controller, which generates a control signal having a predetermined pulse width in response to a DQ off signal and a write signal and generates a clock enable signal in response to a read signal and the control signal in synchronization with the control signal when the read signal is activated, and a clock generator that receives the enable signal and an internal clock signal and generates a data clock signal in synchronization with the internal clock signal during an activation period of the enable signal.

Abstract: A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.

Abstract: A memory clock signal is generated in response to a reference clock signal and a clock enable signal. The memory clock signal with a frequency identical to that of the reference clock signal is generated during the clock enable signal is in an enabled state; and the memory clock signal with a reduced frequency is generated when the clock enable signal is changed from the enabled state to a disabled state. The generation of a memory clock signal is adaptive so as to save power.

Abstract: A pulse generator includes a pulse command register and a digital differential analyzer (DDA). The pulse command register includes a first register, a second register, and an adder. The first register receives and stores a pulse command from a CPU in an operating cycle. The second register receives and stores the pulse command shifted from the first register when the first register receives a second pulse command from the CPU in the operating cycle. The adder sums the pulse commands of the first register and the second register and the result is transmitted to the DDA. The DDA determines whether a pulse is to be generated after calculation according to the result from the adder of the pulse command register.

Abstract: A programmable delay line includes a first oscillator that is enabled and generates a plurality of clock cycles of a clock signal in response to a transition of the input signal. A first programmable ripple counter is coupled to the first oscillator, counts with each successive clock cycle to a programmed count, and generates a first signal in response to reaching the programmed count. A control circuit is coupled to the first oscillator and to the first programmable ripple counter. The control circuit transitions the output signal and disables the first oscillator in response to the first signal.

Abstract: A pulse generator circuit. The pulse generator circuit includes a precharge circuit coupled to receive a clock signal alternating between a first logic level and a second logic level, a storage circuit having a storage node, wherein the precharge circuit is configured to precharge the storage node when the clock signal is at the first logic level, a logic circuit having an output, a first input node coupled to receive the clock signal, and a second input node coupled to the storage node and configured to produce a pulse at the second logic level responsive to the clock signal transitioning to the second logic level, and a discharge circuit configured to discharge the storage node at a predetermined delay time subsequent to the clock signal transitioning to the second logic level, wherein the output of the logic circuit transitions to the first logic level responsive to discharging the storage node.

Abstract: Methods and apparatuses for optimizing switching delay in integrated circuits are described. Combinational logic gates are modified with precharge circuitry and instantiated in order to reduce switching transitions of circuit elements in a signal path.

Abstract: The disclosure includes a latch structure and self-adjusting pulse generator using the latch. In an embodiment, the system includes a first latch and a pulse generator coupled to provide a timing signal to the first latch. The pulse generator includes a second latch that has characteristics matching the first latch.

Abstract: Techniques for scaling and switching clocks in a glitch-free manner are provided. For example, in one aspect of the present invention, a technique for switching a frequency associated with a master clock includes the following steps/operations. Two phase clocks are generated from a master clock, wherein the two phase clocks do not transition at substantially the same time. Then, one of the two phase clocks is used to create multiple frequencies by dividing the one phase clock, and the other phase clock is used to switch between the multiple frequencies of the one phase clock. Further, one of the two phase clocks may be in phase with the master clock and the other of the two phase clocks may be 180 degrees out of phase with the master clock such that they do not transition at the same time. Also, the two phase clocks may be non-overlapping.

Abstract: An interface circuit outputting a clock signal and data to a data register configured to serially read in the data synchronously with the clock signal, in response to a change of a control signal for outputting the clock signal and the data from one logic level to the other logic level, the interface circuit comprising a clock output circuit configured to: detect a logic level of the clock signal when the control signal changes from the one logic level to the other logic level; output the clock signal on an as-is basis to the data register, when detecting one logic level of the clock signal; and output the clock signal after having changed from the other logic level to the one logic level, to the data register, when detecting the other logic level of the clock signal.

Abstract: A digital signal multiplexor and multiplexing method are provided with which switching between different input signals is achieved without producing glitches in the output signal, even in the event of one or more of the input signals stopping and starting at unknown times.

Abstract: A clock control circuit includes a first signal generation block for outputting a first internal clock signal, which is enabled after delay of a first time from a rising edge of a first input clock signal and has a high level pulse width shorter by a second time than a high level pulse width of the first input clock signal, and a second signal generation block for outputting a second internal clock signal, which is enabled after delay of the first time from a rising edge of a second input clock signal and has a high level pulse width shorter by the second time than a high level pulse width of the second input clock signal.

Abstract: A clock generating apparatus has an integral ratio divider for, according to frequency-dividing parameters for generating a second clock signal including a second frequency by using a first clock signal including a first frequency, outputting the second clock signal, and a frequency-dividing parameter generating portion for comparing program clock reference inputted from outside with an STC value based on the second clock signal and outputting the frequency-dividing parameters so as to converge a discrepancy between the program clock reference and the STC value within a predetermined range, and wherein the frequency-dividing parameter generating portion generates new frequency-dividing parameters each time the program clock reference is inputted from outside.

Abstract: An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.