Abstract: A transmitter includes: an output driver that outputs differential signals to differential signal lines; first termination resistors and a first switch which are provided in series between a first reference voltage input terminal to which a reference voltage is inputted and the differential signal lines; a pulse generator that outputs a common-mode pulse to the differential signal lines; a second switch provided between the differential signal lines and the pulse generator; a detector that detects, after generation of the common-mode pulse starts, timing at which a voltage level of the common-mode pulse exceeds a threshold; and a controller that places the second switch in an on state to connect the pulse generator to the differential signal lines, and powers down the output driver and then places the first switch in an off state to allow the pulse generator to output the common-mode pulse to the differential signal lines.

Abstract: A Low Voltage Differential Signaling (LVDS) compliant receiver includes a differential amplifier having inputs and outputs. A first input coupling capacitor and second input coupling capacitor are electrically coupled to each of the first differential input and the second differential input, respectively. The receiver also includes a first and a second regenerative feedback latching mechanism, and the first regenerative feedback latching mechanism is electrically coupled between the first input coupling capacitor and the first differential output. The second regenerative feedback latching mechanism is electrically coupled between the second input coupling capacitor and the second differential output.

Abstract: A motor includes a rotor, a sensor unit, an offset unit, a rectification unit and a modulating unit. The sensor unit outputs a first signal in accordance with a magnetic field variation of the rotor. The offset unit is coupled to the sensor unit, and outputs a second signal in accordance with the first signal. The rectification unit is coupled to the offset unit, and outputs a third signal in accordance with the second signal. The modulating unit is coupled to the rectification unit, and outputs a control signal in accordance with a result by comparing the third signal with a periodic signal. The modulating unit controls a reverse rotation of the rotor smoothly in accordance with the control signal. A control method of the motor is also disclosed.

Abstract: A converter according to one embodiment converts an AC voltage to a regulated output current provided to a DC load of a Z-type configuration. A filter capacitor is provided to average current flowing through the load. The converter includes a rectifier network for rectifying the AC voltage and for providing a rectified voltage, and a smoothing capacitor for smoothing the rectified voltage. The converter includes a hysteretic current mode controller which controls a switching transistor based on sensed voltage and sensed current provided through an inductor coupled in series with the load. The transistor is turned on when current reaches a low valley level and is turned off when the current reaches a peak level. Operation toggles in this manner while a sensed voltage is above a predetermined level. A valley fill network may be provided to keep sensed voltage from falling below the predetermined minimum level.

Abstract: A power converter operable to draw an input current that is in phase with an input voltage of the power converter and proportional to a voltage of the input voltage of the power converter includes a drive switch, a waveform generator, and a current shaping circuit. The drive switch is connected between an input inductor and ground and draws current through the input inductor when turned on. The current shaping circuit provides an on-time of the drive switch for a next cycle of the drive switch as a function of an input current decay time, a switching period of the waveform generator, and an output voltage of the power converter. The waveform generator is responsive to the on-time provided by the current shaping circuit for selectively turning the drive switch on and off to cycle the drive switch as a function of the received on-time.

Abstract: A power converter operable to draw an input current that is in phase with an input voltage of the power converter and proportional to a voltage of the input voltage of the power converter includes a drive switch, a waveform generator, and a current shaping circuit. The drive switch is connected between an input inductor and ground and draws current through the input inductor when turned on. The current shaping circuit provides an on-time of the drive switch for a next cycle of the drive switch as a function of an input current decay time, a switching period of the waveform generator, and an output voltage of the power converter. The waveform generator is responsive to the on-time provided by the current shaping circuit for selectively turning the drive switch on and off to cycle the drive switch as a function of the received on-time.

Abstract: In a conventional switch circuit capable of bidirectional conductivity, there is the problem that latch-up occurs in a parasitic thyristor included in a transistor having a switching function. Therefore it is an object of the present invention to provide a switch circuit capable of bidirectional conductivity while suppressing the occurrence of latch-up due to a parasitic thyristor. The present invention provides a switch circuit that includes diodes connected in parallel with each of a MOS transistor having the switching function and parasitic diodes present at the source and the drain of the MOS transistor.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: A modulator switch composed of stacks of high voltage switching devices connected in series are fired substantially simultaneously to provide pulsed, high voltage switching capable of providing megajoules of energy. The switching devices are fired by a trigger box that is clocked to provide a pulsed signal to each of the switching devices. The trigger box generally consists of a triggering or driver circuit and a pulse generating circuit. These circuits are electrically isolated from one another using suitable shielding and spacing. The pulsed output of the trigger box is fed to the switching devices across low inductance twisted cabling that is passed through toroidal transformers connected to the inputs of the switching devices. Varistors are clamped across each stack of switching devices to provide over-voltage protection for the switching devices.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. In a first configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is utilized as a two terminal device by connecting together the gate and source leads. The terminal voltage in the conducting state is considerably smaller than conventional semiconductor diodes. In a second configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a transformer such that the source and the drain serve as the two leads of a two terminal circuit.

Abstract: Switch driver circuity having first and second output nodes with a current-voltage converter connected therebetween and providing current paths of first and second directions between the nodes, switching circuity connected therewith being switchable between first and second states respectively permitting current flow of a common preselected magnitude in respective first and second opposite directions producing potential differences between the first and second output nodes of a common magnitude but respective, opposite polarities.

Abstract: A rectifier circuit is described, which comprises an arrangement of a first, a second and a third transistor, emitters of said transistors being coupled together at a first junction point and to a terminal of a first constant current source and in which arrangement collectors of the first and the second transistor are coupled together at a second junction point, a current mirror arrangement having a predetermined mirror ratio, an input of said current mirror being coupled to the second junction point and an output of said current mirror being coupled to a collector of the third transistor at a third junction point, wherein an input voltage, by which the collector-emitter currents of the first and/or the second transistor are controllable, can be supplied to the rectifier circuit bia bases of the first and/or the second transistor, while an output voltage can be taken from the base of the third transistor of the rectifier circuit and the output voltage at least substantially corresponds to the rectified input

Abstract: An analog-to-digital or digital-to-analog system contains a converter (706). The converter is supplied with a clock signal (CLK1) at a frequency fs derived from a crystal of a frequency fs/N. The frequency fs is derived from the fs/N crystal frequency by using an edge-triggered clock multiplier 705 which multiplies the crystal frequency by the factor N. The result is a low-cost clock solution that incorporates clock jitter around a localized frequency of fs/N. Sigma delta processing circuitry (702) is then used to place a null (e.g., low gain area) in the quantization noise at the same frequency where clock jitter noise is high in order to cancel the adverse cumulative effects of these two types of noise.

Abstract: A full-wave rectifier circuit (70) includes a first transistor (N1) and a second transistor (N2) in combination to form a first transistor pair (N1 and N2) for minimizing the voltage drop between ground (88) and the transponder substrates. A third transistor (P1) and a fourth transistor (P2) operate in combination to form a second transistor pair (P1 and P2) for minimizing the voltage drop between the alternating current peak voltage (118 and 120) and the output voltage (V.sub.DD) of the full-wave rectifier (70). The first transistor pair (N1 and N2) and second transistor pair (P1 and P2) are controlled by alternating current voltage input signals (118 and 120). A series regulator circuit (70) decouples the first transistor pair (N1 and N2) and the second transistor pair (P1 and P2) from capacitive loads (C1 and C2) of the full-duplex transponder circuitry (14).

Abstract: An integrated circuit arrangement with a diode characteristic including a source-drain section of a first transistor arranged in the current path between the input and output sides of the arrangement; a first inverter stage with an output fed back to its input, and whose supply voltage is provided by the voltage on the output side of the circuit arrangement; a second inverter stage to the input of which the output signal from the first inverter stage is fed and whose supply voltage is provided by the voltage on the input side of the circuit arrangement; and a third inverter stage having an input to which the output signal from the second inverter stage is fed, whose voltage supply is provided by the voltage on the output side of the circuit arrangement, and whose output signal is fed to the gate electrode of the first transistor, and thus regulates the current flow in the current path of the circuit arrangement.

Abstract: Direct voltage and alternating voltage signals are decoupled from a first and a second pair of leads. The pairs of leads each carry an alternating voltage signal and they are subject to a direct voltage between them. A capacitive connection of the leads with the inputs of a signal receiving device allows decoupling of the alternative voltage signal. For decoupling one pole of the direct voltage signal, diodes are provided that are connected to the leads of the respective pair of leads. The diodes are each connected via a respective current source transistor to one terminal for the pole of the direct voltage. The control terminals of the current source transistors are controlled by the center tap of a voltage divider connected between the diodes. The embodiment for direct voltage decoupling is readily integratable.

Abstract: In a full-wave rectifying circuit comprising a differential amplifier (20) differentially amplifies an input alternating current signal (V.sub.IN) to produce first and second amplified output voltages (V.sub.O1, V.sub.O2) and a voltage reference circuit (30) for generating a reference voltage (V.sub.REF), a differential pair circuit (40) carries out half-wave rectification on the first and the second amplified output voltages on the basis of the reference voltage to obtain first and second half-wave rectified currents (I.sub.C3, I.sub.C4). The differential pair circuit (40) includes a combining part (44) for combining the first and the second half-wave rectified currents into a full-wave rectified current (I.sub.RO). The full-wave rectifying circuit may further comprise a current/voltage converting section (50) for converting the full-wave rectified current into a full-wave rectified voltage (V.sub.RO).

Abstract: The invention relates to a control circuit for a semiconductor switch, comprising a transformer coupling (T1, T2) for generating AC voltage signals including both control energy and control information, a rectification coupling (DB1, DB2) for rectifying the AC voltage signals generated by the transformer coupling (T1, T2) for generating DC voltage levels (U1, U2, U3) appropriate for turning on and turning off a semiconductor switch (SW1), a first resistor (R2) connected at its first end to a driving electrode of the semiconductor switch (SW1), a second resistor (R1) connected between the driving electrode and the emitter or source electrode of the semiconductor switch, and a booster semiconductor switch (V1) provided between the driving electrode of the semiconductor switch (SW1) and an DC voltage output (U3) generated by the rectification coupling and intended for turning off the semiconductor switch, the driving electrode of the booster semiconductor (V1) being connected to a DC voltage output (U2) generate