Abstract: RF switching circuitry includes one or more RF switching elements, a control signal input node, a common resistor, and common resistor bypass circuitry. The one or more RF switching elements are coupled in series between a switch input node and a switch output node. A state of each one of the one or more switching elements is determined based on a control signal. The control signal input node is configured to receive the control signal. The common resistor is coupled between the control signal input node and the one or more RF switching elements. The common resistor bypass circuitry is configured to receive the switching control signal and bypass the common resistor for a predetermined time period following one or more of a leading edge of the switching control signal and a falling edge of the switching control signal.

Abstract: Provided herein are apparatus and methods for high linearity voltage variable attenuators (VVAs). In certain configurations, a high linearity VVA includes multiple shunt arms or circuits that operate in parallel with one another between a signal node and a first DC voltage, such as ground. Thus, the shunt arms are in shunt with respect to a signal path of the VVA. The multiple shunt arms include a first shunt arm of one or more n-type field effect transistor (NFETs) and a second shunt arm of one or more p-type field effect transistor (PFETs). The gates of the NFETs are controlled using a control voltage, and the gates of the PFETs are controlled using a complementary control voltage that changes inversely with respect to the control voltage.

Abstract: Systems, apparatuses and methods are disclosed providing a semiconductor die comprising a semiconductor substrate and a radio-frequency (RF) switch including one or more series field-effect transistors (FETs) and one or more shunt FETs, each of the one or more series FETs and one or more shunt FETs having a respective gate node, the RF switch being configured to receive an RF signal from a power amplifier module and provide the RF signal to an antenna. The semiconductor die may further comprise an internal regulator voltage source configured to provide an internal regulator voltage when the RF switch is in a stand-by mode and shunt arm control circuitry configured to provide the internal regulator voltage to the gate nodes of the one or more shunt FETs when the RF switch is in the stand-by mode.

Abstract: A termination circuit includes a first transistor coupled to a first pad, a first resistor coupled between the first transistor and a second pad, and an operational amplifier circuit. The termination circuit provides termination impedance to input signals received at the first and second pads. The first transistor generates a first common mode voltage of the input signals at a first node between the first resistor and the first transistor in response to an output signal of the operational amplifier circuit. The operational amplifier circuit generates the output signal based on the first common mode voltage of the input signals and based on a second common mode voltage of the input signals. The termination circuit generates the second common mode voltage at a second node that is a different node than the first node.

Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.

Abstract: A first sense resistor is connected between a fourth terminal of a power source potential of a high-potential region and a first terminal of a ground potential. A second sense resistor is connected between a third terminal of a reference potential of the high-potential region and the first terminal. A comparator is disposed in a low-potential region and uses the ground potential as a reference potential for operation. The comparator compares a voltage between an intermediate potential point of the first sense resistor and an intermediate potential point of the second sense resistor with a predetermined reference voltage. The output of the comparator is input through a control circuit and a level shift circuit to a high-side drive circuit driving an upper-arm IGBT. The output of the comparator is input to a driver circuit driving a lower-arm IGBT.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.

Abstract: A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A low-pass filter comprising: a filter input terminal; a filter output terminal; a filter FET configured to provide a resistance between the filter input terminal and the filter output terminal; a filter capacitor connected between the filter output terminal and a reference terminal; a bias FET configured to provide a bias voltage to the filter FET; a buffer connected between the filter input terminal and the bias FET, the buffer configured to source a bias current for the bias FET; and an offset voltage source configured to contribute to the bias voltage provided to the filter FET.

Abstract: Provided herein are apparatus and methods for using tuning information to adaptively and dynamically modify the parameters of an RF signal chain. The tuning information from an oscillator core, having multiple oscillators, adaptively tunes parameters of system components within a signal chain. In this way the system components are tuned to operate within a band tailored to the signal and to the oscillator core. In addition, RF impedances can be matched and power added efficiency can be enhanced in an area efficient monolithic integrated circuit.

Abstract: An apparatus for selectively providing attenuation with minimal relative phase error. A Digital Step Attenuator (DSA) is implemented on an integrated circuit (IC). Each cell of the DSA has a series compensation inductance that is introduced between an input to the cell and a resistor on the cell. The series compensation inductance allows the location of a pole present in the transfer function of the cell to be manipulated. By controlling the location of the pole in the transfer function of the DSA, the relative phase error of the cell can be controlled. In another disclosed embodiment, the capacitance of a shunt compensation capacitor is increased to manipulate a pole in the transfer function of a DSA cell.

Abstract: Provided are a threshold voltage compensation circuit of TFT and a method for the same, a shift register and a display device. The threshold voltage compensation circuit includes an input terminal, an output terminal connected to the source of the thin film transistor, a first resistor to a Kth resistor connected in series, and Kth connectable link and at least one first connectable link. Since a voltage dividing circuit having connectable links divides the voltage input to the source of the thin film transistor, such that the gate-source voltage of the thin film transistor can be changed by changing the voltage of the source of the thin film transistor when the voltage of the gate of the thin film transistor is maintained unchanged, so as to control a leakage current of the thin film transistor under a turn-off state, such that the thin film transistor can be turned off normally.

Abstract: A coherent receiver comprises an ingress signal path having an ingress line-side interface, and an ingress host-side interface. The ingress signal path is configured to receive an analog signal vector at the ingress line-side interface, to demodulate the analog signal vector, and to output a digital data signal at the ingress host-side interface. The coherent receiver also comprises clock and timing circuitry configured to receive a single reference clock signal and to provide a plurality of modified ingress path clock signals to different components of the ingress signal path, the plurality of modified ingress path clock signals derived from the single reference clock signal and the plurality of modified ingress path clock signals having different clock rates. The receiver, transmitter, or transceiver can operate in a plurality of programmable operating modes to accommodate different modulation/de-modulation schemes, error correction code schemes, framing/mapping protocols, or other programmable features.

Abstract: A switching circuit may include a switching circuit unit; a reference voltage unit connected between the switching circuit unit and a signal input terminal and providing a preset reference voltage; and a voltage generating unit dividing a first control voltage provided to the switching circuit unit by a preset magnitude to generate a second control voltage corresponding to the reference voltage, and providing the second control voltage to bodies of the plurality of respective switching devices.

Abstract: A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply.

Abstract: An electronic-fuse (e-fuse) circuit includes: an e-fuse array; a control switch, coupled to the e-fuse array, for controlling whether a voltage supply is applied to the e-fuse array in programming; and a close loop feedback circuit, coupled to the control switch and the e-fuse array, for clamping at lease one node voltage of the e-fuse array to a reference voltage, and for controlling the control switch to control a blowing current in programming the e-fuse array.

Abstract: System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

Abstract: A variable attenuator comprises a series resistance, and an adjustable shunt resistance, wherein the adjustable shunt resistance comprises a series circuit of a fixed resistor and a semiconductor element having an adjustable resistance.

Abstract: In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change.

Abstract: The semiconductor device includes a power transistor that is disposed between a first signal line, which is coupled to a first external terminal, and a second signal line, which is coupled to a second external terminal. A gate electrode of the power transistor is coupled to a third signal line. The semiconductor device further includes a clamp circuit that clamps a voltage between the first signal line and the third signal line, a first resistive element that is disposed between the third signal line and the second signal line, and a monitoring section that monitors a voltage between the third signal line and the second signal line. The clamp circuit is configured so that a clamp voltage can be changed. The monitoring section exercises control to decrease the clamp voltage when the voltage between the third signal line and the second signal line exceeds a predefined threshold value.

Abstract: An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Abstract: There is provided a radio frequency switch circuit including a first switch circuit unit connected between a first node connected to a first signal port and a common node connected to a common port, and operated according to a first control signal, a second switch circuit unit connected between a second node connected to a second signal port and the common node and operated according to a second control signal having a phase opposite to that of the first control signal, a first shunt circuit unit connected between the second node and a common source node and operated according to the first control signal, a second shunt circuit unit connected between the first node and the common source node, and a source voltage generating unit generating a source voltage, wherein the source voltage is lower than a high level of the first control signal and higher than a ground potential.

Abstract: Described are embodiments of stacked field effect transistor (FET) switch having a plurality of FET devices coupled in series to form an FET device stack. A control circuit provides biasing voltages to the gate, source, and drain contacts of each of the plurality of FET devices to switch the FET device stack to and from a closed state and an open state. In the open state, the gate contacts of each of the plurality of FET devices are biased by the control circuit at the second voltage. To prevent activation in the open state, the control circuit biases the drain contacts and source contacts of each of the plurality of FET devices at the first voltage. The first voltage is positive relative to a reference voltage, such as ground, while the second voltage is non-negative relative to the reference voltage but less than the first voltage.

Abstract: There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices; a second signal transferring unit including a plurality of second switching devices; a first shunting unit including a plurality of third switching devices; and a second shunting unit including a plurality of fourth switching devices.

Abstract: A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor.

Abstract: The impedance of the elements of a capacitor array in the transmitter is kept substantially constant over changes in process, temperature, and supply voltage. The impedance is maintained substantially constant by compensating a gate voltage supplied to switches in each element of the capacitor array to adjust for changes in temperature and supply voltage to thereby maintain a substantially constant RC product for each unit element in the capacitor array and thereby improve the quality factor of the capacitor array.

Abstract: An equalizer for compensating an input signal in a receiver of a communication system is disclosed. The equalizer includes a first transistor, having a gate for receiving a positive input voltage of the input signal; a second transistor, having a gate for receiving a negative input voltage of the input signal, and a source coupled to a source of the first transistor; and a resistor, connected with at least one capacitor to be coupled between a drain of the first transistor and a drain of the second transistor, for optimizing a resistance of the resistor, to compensate the input signal.

Abstract: The present disclosure provides an attenuator and associated methods of operations. An exemplary attenuator includes an input terminal, an output terminal, a voltage reference terminal, a first attenuation segment coupled with the input terminal and the output terminal, and a second attenuation segment coupled with the first attenuation segment and the voltage reference terminal. The attenuator further includes at least two switches coupled with the input terminal and the output terminal in parallel with the first attenuation segment, where at least some of the at least two switches have an associated voltage control terminal. For example, the attenuator includes a first switch and a second switch coupled with the input terminal and the output terminal in parallel with the first attenuation segment, wherein a first voltage control terminal is coupled with the first switch and a second voltage control terminal is coupled with the second switch.

Abstract: An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion.

Abstract: An equalizer circuit includes an input terminal, a pull-up driving unit suitable for pull-up driving an output terminal based on a signal of the input terminal, a pull-down driving unit suitable for pull-down driving the output terminal, and a capacitor connected between the input terminal and the output terminal.

Abstract: The present description relates to a semiconductor device including an array of two or more switching elements and a controller electrically connected to the array of switching elements. At least one switching element of the array of switching elements has a different electrical resistance than at least another switching element of the array of switching elements. The controller is configured to generate and transmit at least one coarse tuning signal and at least one fine tuning signal. The array of switching elements is configured to alter an electrical resistance of the array of switching elements in response to the at least one coarse tuning signal and the at least one fine tuning signal. The present description also includes a method of making a semiconductor device and a method of using a semiconductor device.

Abstract: Embodiments of the invention described herein provide a magnetic sensor interface capable of adjusting signal conditioning dynamically using a speed signal of a target such that the true positive and negative peaks of the input signal are maintained for the given target across its entire speed range (0-Max rpm), therefore increasing the signal to noise ratio at low speeds and avoiding clipping or distortion at high speeds. In one aspect, a method comprises receiving an alternating differential voltage signal from a sensor. The differential voltage signal has an amplitude that changes relative to a change in speed of a target. The alternating differential voltage signal is converted to an attenuated single-ended voltage signal that can be dynamically scaled. The attenuated single-ended voltage signal can be scaled by multiplying the attenuated single-ended voltage signal by a scaling factor.

Abstract: The present disclosure provides an attenuator and associated methods of operations. An exemplary attenuator includes an input terminal, an output terminal, a voltage reference terminal, a first attenuation segment coupled with the input terminal and the output terminal, and a second attenuation segment coupled with the first attenuation segment and the voltage reference terminal. The attenuator further includes at least two switches coupled with the input terminal and the output terminal in parallel with the first attenuation segment, where at least some of the at least two switches have an associated voltage control terminal. For example, the attenuator includes a first switch and a second switch coupled with the input terminal and the output terminal in parallel with the first attenuation segment, wherein a first voltage control terminal is coupled with the first switch and a second voltage control terminal is coupled with the second switch.

Abstract: An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion.

Abstract: One embodiment may take the form of a control circuit that provides a combined power signal and control signal to an LNB of a satellite system. The control circuit output may be transmitted to an LNB by a set-top box (STB) such that the STB may control the LNB. The control circuit may accept an enable signal from the STB to alter the circuit from a transmitting circuit to a receiving circuit. The control circuit may also integrate the functionality of a low pass filter into the communication signal circuit, thereby removing the need for a low pass filter at a power supply output. The control circuit may also provide a low overall power consumption of the circuit by isolating the communication signal from the power supply signal before the signals are combined.

Abstract: A circuit includes first to third nodes, resistors with different resistance, capacitors with different capacitance, first switches corresponding to the same number of resistors, second switches corresponding to the same number of capacitors, and a third switch. A first terminal of each resistor is connected to the first node. A second terminal of each resistor is connected to a first terminal of a corresponding one first switch, a second terminal of each first switch is connected to the second node. A first terminal of the third switch is connected to the second terminal of each first switch. A second terminal of the third switch is connected to a first terminal of each capacitor. A second terminal of each capacitor is connected to a first terminal of a corresponding one second switch. A second terminal of each second switch is connected to the third node.

Abstract: Voltage controlled variable attenuators are described that are configured to be coupled to a transmission path to furnish variable attenuation of a signal, such as a radio frequency signal. In one or more implementations, the voltage controlled variable attenuator includes at least one transistor. The transistor has an open configuration for at least substantially preventing the flow of current through the transistor, and a closed configuration for at least partially allowing the flow of current through the transistor. The variable attenuator also includes a resistive component coupled to the transistor, and configured to couple to the transmission path. The resistive component is configured to at least partially mitigate non-linear effect when the transistor transitions from the open configuration to the closed configuration.

Abstract: There is provided a high frequency switch which is satisfactory in terms of both insertion loss characteristics and harmonic characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units includes a plurality of series-connected MOSFETs formed on a silicon substrate, the plurality of MOSFETs are any one of body contact-type FETs and floating body-type FETs, and each of the switching units includes both of the body contact-type FETs and the floating body-type FETs.

Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complimentary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output port is also provided.

Abstract: A switch can be configured to receive a first signal at a first input and provide an output signal at an output, depending on a state of the switch. A switch state change can be delayed until an indication of a requested switch state different than a current switch state is received and the first signal reaches a threshold.

Abstract: An impedance calibration circuit may include a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals, a second reference voltage generator configured to provide a second reference voltage as a conversion voltage, an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal is activated, and a register configured to store the impedance calibration signals finally calibrated and generate reference voltage calibration signals in response to the stored impedance calibration signals.

Abstract: An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion.

Abstract: A tunable voltage-controlled pseudo-resistor structure, comprising: a symmetric PMOS transistor circuit and an auto-tuning circuit connected in series. Input of the auto-tuning circuit is connected to a central position Vf of the PMOS transistor circuit having its output Vg, with its purpose of keeping Vg?Vf at a constant value. The PMOS transistor circuit may produce body effect through various different bulk voltages. Through the auto-tuning circuit, Vg and Vf are kept constant to make current of transistor to produce compensation effect, such that regardless of Va>Vb or Va<Vb, a large resistance is maintained. Through utilizing the tunable voltage-controlled pseudo-resistor structure, constant resistance can be maintained under high input voltage, hereby reducing drifting of common-mode voltage, in achieving a superior resistance effect.

Abstract: A voltage controlled variable resistor circuit is configured to variably attenuate a variable source signal. A fixed attenuation circuit is coupled to receive the variable source signal and output an attenuated variable source signal. The variable source signal is further applied across a variable resistive divider formed of a fixed resistive circuit and a variable resistive circuit. The variable resistive circuit has a first input configured to receive the attenuated variable source signal and a second input configured to receive a variable resistance control signal. The variable resistive circuit is configured to have a resistance which is variable in response to the attenuated variable source signal and the variable resistance control signal.

Abstract: A switch circuit can include an impedance selection switch and a multi-output-resistance switch driver. The impedance selection switch can electrically connect an impedance to an input of an amplifier in response to a driver output signal, and include at least one transistor. The multi-output-impedance switch driver may provide the driver output signal to the switch, and have a first, relatively higher output resistance when providing a first logic state of the driver output signal to turn on the switch, and a second, relatively lower output resistance when providing a second logic state of the driver output signal to turn off the switch. The ratio of the first output resistance to the second output resistance can be greater than a selected predetermined ratio value.

Abstract: Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.

Abstract: A level-shift circuit, comprising: an input, for receiving a first voltage; an output, for outputting a second voltage; a resistor array comprising one or more resistors connected in series to the input; a current sink for providing a current that is independent of the first voltage; a switch arrangement comprising a plurality of switch connections for establishing a selected one from a plurality of force paths between the current sink and the input, the selected force path comprising a selected number of the one or more resistors of said resistor array; and at least one connection between the output and the resistor array that provides a sense path between the resistor array and the output that does not comprise any of the switch connections used to establish each of the plurality of force paths.

Abstract: In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator.