Abstract: A method and system avoid ringing at an external power transistor subsequent to switching OFF the external power transistor. A driver circuit generates a drive signal for switching the external power transistor between OFF-state and ON-state. The driver circuit comprises a drive signal generation unit configured to generate a high drive signal triggering the external power transistor to switch to ON-state, wherein an output resistance of the driver circuit is adjustable, an oscillation detection unit to detect a degree of oscillation on the drive signal, and a resistance control unit to adjust the output resistance of the driver circuit based on the degree of oscillation on the drive signal.

Abstract: A switch for an analog signal may include a main MOS transistor whose source forms an input terminal of the switch and whose drain forms an output terminal of the switch, a capacitor having a first terminal permanently connected to the source of the main transistor, a circuit for charging the capacitor, and a first auxiliary transistor configured to connect the second terminal of the capacitor to the gate of the main transistor in response to a control signal. The charge circuit may include a resistor permanently connecting the second terminal of the capacitor to a power supply line. The capacitor and the resistor may form a high-pass filter having a cutoff frequency lower than the frequency of the analog signal.

Abstract: A switching device includes: a first switching circuit, having a control node coupled to a first control signal, and arranged to selectively couple a signal node to a first amplifying circuit according to the first control signal; and a first control circuit, having a first control node and a second control node coupled to the control node of the first switching circuit and the signal node, respectively, wherein when the first switching circuit is controlled to electrically disconnect the signal node from the first amplifying circuit and a voltage level of the signal node reaches a first predetermined voltage level, the first control circuit is arranged to make the control node of the first switching circuit electrically connected to the signal node.

Abstract: A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance.

Abstract: A device for switching at least one energy storage device includes a parallel circuit of transistors that is connected in series with the energy storage device. Gate terminals of the transistors are connected to one another. At least one of the transistors from the parallel circuit is configured to be operated in avalanche breakdown and has an avalanche voltage which is lower than respective avalanche voltages of the remaining transistors.

Abstract: An inter-line switching element formed of a MOSFET is provided between a pair of signal lines. When the level of a differential signal changes from high to low, a control circuit turns on the FET for a fixed period thereby to suppress ringing by decreasing the impedance between the signal lines when the level of the differential signal transitions, and causing the energy of the distortion of the differential signal waveform to be absorbed by the on-resistance of the FET.

Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.

Abstract: A power supply controller is provided for providing a drive current to a control terminal of a power transistor in three time intervals. The controller includes control circuits configured to control the drive current in multiple stages. During a first time interval, first drive current includes a current spike for turning on the power transistor in response to a start of the control signal pulse. During a second time interval, a second drive current includes a ramping current substantially proportional to a magnitude of a current through the power transistor. During a third time interval, current flow to the power transistor is at least partially turned off before an end of the control signal pulse.

Abstract: A high voltage drive circuit includes an edge detector for generating an edge detection signal by detecting edges of a first high side input signal and a first low side input signal, the edge detector providing a high side delay signal and a low side delay signal by delaying the first high side input signal and the first low side input signal, a dead time generator for generating a dead time signal indicating a preset dead time in response to the edge detection signal, and a driver comprising a drive signal generator for providing a high side output signal and a low side output signal by inserting the preset dead time based on the dead time signal into the high side delay signal and the low side delay signal.

Abstract: A semiconductor device prevents recognition failure in mutual recognition between a host and a device compliant with USB Specifications. The semiconductor device includes: an interterminal opening/closing section having a plurality of first conductivity type MOS transistors, the respective sources or drains of which are cascaded, in which the source or drain of a first-stage MOS transistor among the cascaded MOS transistors is used as a first terminal, the source or drain of a final-stage MOS transistor among the cascaded MOS transistors is used as a second terminal, and the respective gates of the cascaded MOS transistors receive a control signal for controlling the opening or short-circuiting between the first and second terminals; and a current bypass section that reduces a current flowing into either one connection node coupling the respective sources or drains of the cascaded MOS transistors.

Abstract: An identifying circuit is connected between a Universal Serial Bus (USB) interface and a controller. The identifying circuit includes first to fourth electronic switches. When a power adapter connects to the USB interface, the first and fourth electronic switches are not turned on, and the second and third electronic switches are turned on. An identification pin of the controller receives a low level signal and determines that the power adapter connects to the USB interface. When a computer connects to the USB interface, the first and fourth electronic switches are turned on, and the second and third electronic switches are not turned on. The identification pin receives a high level signal and determines that the computer is connected to the USB interface.

Abstract: An adaptive switch circuit is provided, which includes a CMOS switch, an off-level voltage generator, and a booster circuit. The CMOS switch includes first PMOS and NMOS coupled transistors. The generator provides, via first and second outputs, first and second voltage levels, and includes second PMOS and NMOS transistors. The second PMOS transistor is series connected between VDD and a first bias source and the second NMOS transistor is series connected between VSS and a second bias source. The booster circuit, which is coupled to the generator between its outputs, and to the PMOS and NMOS gates of the CMOS switch, capacitively stores during off level first and second boost voltages, which are coupled to the PMOS and NMOS gates. The boost voltages are offset from VDD and VSS, respectively, each by approximately a threshold voltage of the respective transistor type.

Abstract: A method for controlling a switch based on transistors is disclosed. A switching circuit for switching a signal from an input port to an output port thereof is provided. A shunting circuit for switchably shunting the signal from the input port to ground is also provided. A control signal is generated for biasing a control port of the shunting circuit and an approximately complementary control signal is generated for biasing of the switching circuit to either shunt a signal received at the input port or to switch the signal to the output port. A further bias signal for biasing a port within the switching circuit along the signal path between the input port and the output.

Abstract: A load driving circuit in which the off-time Toff and the fall time Tf can be improved in turn-off operation of the N-channel type MOSFET used as a high side switch. The load driving circuit uses an N-channel type power MOSFET as a high side switch connected between a power supply and a load, including a comparator circuit for comparing a gate voltage of the power MOSFET with a power-supply voltage; and a shut-off circuit for discharging the gate terminal of the power MOSFET in turn-off operation of the power MOSFET, the rate of discharging the gate terminal of the power MOSFET performed with the shut-off circuit being set such that the discharge rate provided if the gate voltage Vg is lower than the power-supply voltage Vp is slower than the rate of discharging the same provided if the gate voltage Vg is higher than the power-supply voltage Vp.

Abstract: An ignitor semiconductor apparatus can include an output stage IGBT that controls the ON and OFF of the primary current of ignition coil, a sensing IGBT and a sensing resistance for detecting the current flowing through output stage IGBT, gate resistance and a current control circuit that detects the voltage across sensing resistance and controls the current flowing through output stage IGBT. First and second gate control circuits separately control the gate voltages of IGBT's such that the gate voltage of the output stage IGBT is higher than the gate voltage of the sensing IGBT, when the current flowing through output stage IGBT is larger than a predetermined current value, and such that the gate voltage of output stage IGBT is lower than the gate voltage of sensing IGBT, when the current flowing through output stage IGBT is smaller than the predetermined current value.

Abstract: An ESD protection circuit including a first electrostatic discharge protection circuit provided between first power supply wiring and first ground wiring; a second ESD protection circuit provided between second power supply wiring and second ground wiring; a third ESD protection circuit provided between the first ground wiring and the second ground wiring; a PMOS transistor coupled to the first power supply wiring and provided between a first CMOS circuit coupled to the first ground wiring and the first power supply wiring, the first CMOS circuit receiving a signal from a first internal circuit and outputting a signal to a first node; an NMOS transistor provided between the first node and the first ground wiring; and an ESD detection circuit that renders the PMOS transistor conductive and the NMOS transistor non-conductive during normal operation, and renders the PMOS transistor non-conductive and the NMOS transistor conductive when an ESD is applied.

Abstract: Apparatus and methods for a switch circuit to provide a substantially constant gate-to source voltage to a passgate are provided. In an example, a switch circuit includes a summing circuit having an output configured to couple to the gate of a passgate, the summing circuit can be configured to maintain a substantially constant voltage between the gate and the source of the pass gate.

Abstract: A technique for improving the linearity of a mixer is disclosed. A converter may include a mixer comprising a first metal-oxide semiconductor field-effect transistor (MOSFET) having a gate, a first conducting terminal coupled to an input of the converter, and a second conducting terminal coupled to an output of the converter, and a mixer driver having a first output coupled to the gate of the first MOSFET, the mixer driver configured to receive a local-oscillator signal having a first phase and a second phase, drive the first MOSFET off during the first phase of the local-oscillator signal, drive the first MOSFET on for a first period of time in response to a transition from the first phase of the local-oscillator signal to the second phase of the local-oscillator signal, and force the gate of the first MOSFET into a high impedance state for a second period of time during the second phase of the local-oscillator signal and after the expiration of the first period of time.

Abstract: A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Abstract: A power supply switch apparatus includes a main outlet, first and second load outlets, a manual switch, and first and second electronic switches. The positive terminal of the main outlet is connected to the positive terminal of the first load outlet and connected to the second terminal of the first electronic switch. The third terminal of the first electronic switch is connected to the positive terminal of the second load outlet. The first terminal of the first electronic switch is connected to the second terminal of the second electronic switch and connected to a voltage terminal through a first resistor. The third terminal of the second electronic switch is grounded. The first terminal of the second electronic switch is connected to the voltage terminal through the manual switch and a second resistor in that order, and grounded through a third resistor.

Abstract: An analog T switch is disclosed which has high isolation in the off state. The analog T switch can include series-connected NMOS transistors having separate gate control. The gates of the NMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog switch can include series-connected PMOS transistors having separate gate control. The gates of the PMOS transistors can be isolated from one another to improve off state isolation of the analog T switch. The analog T switch can include a substrate voltage control circuit that controls the voltage of the substrate regions in which the PMOS transistors are formed. The substrate voltage control circuit can isolate the substrate regions of the PMOS transistors from one another in the off state to improve off state isolation of the analog T switch.

Abstract: A control circuit for controlling a switching device having a first terminal, a second terminal, and a control terminal is disclosed. The control circuit includes a first diode for coupling to the first terminal of the switching device, a second diode for coupling to the second terminal of the switching device, a first transistor for coupling to the control terminal of the switching device, and a second transistor coupled to the second diode. The first transistor is coupled to the first diode. The control circuit is configured to allow current flow in only one direction between the first and second terminals of the switching device.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: A first terminal T1 is connected to the drain (or the source) of a MOS-FET (Q11), whose back gate is separated, through a capacitor C11. The MOS-FET (Q11) is connected at the source (or the drain) thereof to a second terminal T2. The back gate is connected to the source (or the drain). A control voltage VG is supplied to the gate of the MOS-FET (Q11), and a voltage having a polarity reversed from that of this control voltage VG is supplied to the drain through a resistance element R12.

Abstract: A dynamically self-bootstrapping circuit for a switch features a resistor in series with the control node of the switch. A bypass switch connects a control node to ground. When the switch is in an off-state, the bypass switch is enabled.

Abstract: An isolation circuit is provided. The isolation circuit is coupled to an output and an input node and includes a first set, a second switch set, and a body bias voltage generator. The first switch set couples a switch control node to a second voltage when a first voltage is at a first voltage level, and couples the switch control node to the input node when the first voltage is at a second voltage level. The second switch set couples the output node to the input node when the first voltage is at the first voltage level, and isolates the output node from the input node when the first voltage is at the second voltage level. The body bias voltage generator selectively provides a higher one of the first voltage and a voltage on the input node to a body of the second switch set.

Abstract: The present invention relates to a switch driving circuit and a driving method thereof. The switch driving circuit according to the present invention is supplied with a first voltage and a second voltage, is driven by a voltage difference between the first and second voltages, controls a switching operation of a power switch according to a switch driving control signal, generates a sense voltage corresponding to the second voltage, compares a predetermined reference voltage with the sense voltage, and stops the switching operation of the power switch according to the comparison result.

Abstract: A switching circuit configured to reduce the effects of signal oscillation on the operation of the switching circuit is provided. The switching circuit may include signal oscillation and detection circuitry that suppresses control signals during a detected oscillation, allowing stored energy to naturally decay in the switching circuit and thereby prevent unwanted extension of the oscillation that may be caused by the repeated switching of a semiconductor element coupled between the input and output of the switching circuit.

Abstract: In one embodiment, a system includes a replica driver that includes n-type digital-to-analog converter (NDAC) current sources. The replica driver can produce a reference voltage based on current supplied by the NDAC current sources. The system includes driver fingers that are coupled to the replica driver and each include a driver bias circuit and an output driver. The driver bias circuit includes an operational amplifier (op-amp) that can adjust current-source gate voltage in the output driver to produce voltages at output nodes of the driver fingers that approximately match the reference voltage produced by the replica driver.

Abstract: An emission driver may include a first signal processor adapted to receive a clock signal, an input signal and an inverse input signal, and generate a first output signal, a second signal processor adapted to receive the first output signal, an inverse clock signal and negative feedback signals, and generate a second output signal, a third signal processor adapted to receive the second output signal and the input signal, and generate a third output signal that is an inverse of the second output signal based on the input signal, a fourth signal processor adapted to receive the second output signal, and generate a fourth output signal based on the second output signal, the fourth output signal being an inverse signal of the third output signal, and a fifth signal processor adapted to receive the fourth output signal and output a fifth output signal based on a stored predetermined voltage.

Abstract: A first bias circuit outputs a first direct-current voltage to charge a first capacitor based on a clock signal. A second bias that outputs a second direct-current voltage to charge a second capacitor based on a clock signal. A first MOS transistor has a gate and a source. The first direct-current voltage is applied between the gate and the source of the first MOS transistor to bias the gate of the first MOS transistor. A second MOS transistor has a gate and a source, and a drain connected to the source of the first MOS transistor. The second direct-current voltage is applied between the gate and the source of the second MOS transistor to bias the gate of the second MOS transistor. A coupling capacitor has a first end connected to the source of the first MOS transistor, and a second end to which an alternating-current signal is input.

Abstract: An analog switch comprises a first transistor, a second transistor, the drain and the source thereof being connected between said first input terminal and a second output terminal whereto said second signal is output and the gate thereof being grounded or connected to a supply voltage node, a third transistor, the drain and the source thereof being connected between a second input terminal whereto said second signal is input and said second output terminal and said third transistor being turned on and off by a control signal provided to the gate thereof; and a fourth transistor, the drain and the source thereof being connected between said second input terminal and said first output terminal and the gate thereof being grounded or connected to a supply voltage node.

Abstract: Disclosed herein is a bootstrap circuit configured to employ first, second and third transistors of the same conduction type wherein: a node section connecting a gate electrode of the first transistor and a specific one of the source and drain areas of a third transistor to each other is put in a floating state when the third transistor is put in a turned-off state; a gate electrode of the second transistor is connected to a clock supply line which conveys the other one of the two clock signals; and a voltage-variation repression capacitor is provided between the node section and a first voltage supply line.

Abstract: A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches.

Abstract: Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Abstract: A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.

Abstract: A MOSFET switch is disclosed that is driven on by a circuit that provides a constant gate to source voltage, Vgs, that is independent of the input voltage, the power supply and any logic signals. The constant Vgs is derived from a reference voltage and biases the MOSFET switch such that Ron is constant, or Rflatness is minimized. A minimized Rflatness provides a higher fidelity transfer of audio signals compared to prior art switches where Rflatness is greater.

Abstract: A driver circuit comprising an insulated gate bipolar transistor having a collector coupled to a voltage supply, an emitter coupled to a source of reference potential, and a gate configured to receive a control signal from a driver circuit, and a desaturation circuit conductively coupled between an insulated gate and a collector of the insulated gate bipolar transistor to desaturate the insulated gate. The desaturation circuit includes a series coupled bias voltage source, uni-directionally conducting element and switch.

Abstract: A switch circuit device with improved insertion loss characteristics and isolation characteristics is provided. The switch circuit of the present invention includes a plurality of n-ch MOSFETs whose gates are connected together and whose drains and sources are connected in series, a p-ch MOSFET whose gate is connected to the gates of the plurality of n-ch MOSFETs and whose drain is connected to the source and drain of at least one pair of adjacent n-ch MOSFETs, and a voltage changing circuit for applying a low voltage to the source of the p-ch MOSFET while a high-level control voltage is applied to the gate of the p-ch MOSFET, and a high voltage to the source of the p-ch MOSFET while a low-level control voltage is applied to the gate of the p-ch MOSFET.

Abstract: Power savings are achieved for digital data transport over short distances by using the characteristics of resonant LC circuits. Economy of circuit elements is achieved by enabling a single pair of resonant circuits to drive large numbers of digital data lines or nodes in parallel. This maximizes power efficiency and minimizes area and cost. Resistance is minimized by insuring that all switches in the current path are fully “ON” whenever significant current is flowing through them. All other parasitic resistances in the circuits, consisting primarily of parasitic interconnect resistances, are minimized. This enables the data transmission circuits to achieve maximum Q or quality factor, which minimizes power dissipation.

Abstract: An integrated circuit device includes: an internal circuit disposed on an inside area of the integrated circuit device; and at least one regulator circuit that generates a regulation voltage formed by stepping down a power supply voltage provided from outside, wherein an output terminal of the regulator circuit is connected to a first pad that is an external terminal of the integrated circuit device and a power supply line of the internal circuit, and the regulator circuit controls the state of the output terminal based on a plurality of control signals inputted respectively to a plurality of control terminals.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: A switch circuit is disclosed. The switch circuit comprises: a hysteresis buffer, an electric switch, a first discharge resistor, a second discharge resistor, a capacitor, a feedback resistor, a first reciprocal switch, and a second reciprocal switch. When the second reciprocal switch is turned on, a power supply voltage charges the capacitor, and thus the voltage on the signal input terminal of the hysteresis buffer is decreased. Accordingly, the voltage on the signal output terminal of the hysteresis buffer is decreased, so as to turn on the electric switch. When the first reciprocal switch is turned on, the capacitor is discharged, and thus the voltage on the signal input terminal of the hysteresis buffer is increased. Accordingly, the voltage applied to the signal output terminal of the hysteresis buffer is increased, so as to turn off the electric switch.

Abstract: In the case of an electronic circuit, comprising a drive unit, which generates at least one drive signal, two or more power semiconductor switches each having a first and a second main terminal, which power semiconductor switches can be switched synchronously by the drive signal, the first and the second main terminals of the power semiconductor switches in each case being electrically connected in parallel among one another, for each of the power semiconductor switches a first and a second electrically conductive connection for connection to the drive unit, a uniform dynamic current division between the power semiconductor switches is achieved according to the invention by virtue of the fact that a first inductance is provided in each of the first electrically conductive connections, and a second inductance is provided in each of the second electrically conductive connections, the first inductance being coupled to the second inductance for each of the power semiconductor switches.

Abstract: A logic assembly (400) is composed from circuit elements of a single threshold and single conductivity type and comprises a logic circuitry (410) having at least a set of switches each having a main current path and a control terminal. The main current path forms a series arrangement having first and second conducting terminals coupled to power supply lines. The main current paths being coupled to a common node that forms an output of logic assembly (400). The control terminals of said switches being coupled to clock circuitry for providing mutually non-overlapping clock signals to said control terminal. The logic assembly further comprises an output boosting circuit (420) for boosting the output of said logic assembly (400) including a capacitive means (421) for enabling supply of additional charge to the output of said logic assembly (400).

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A bus switch with level shifting may include a first terminal configured to receive and output a first power supply voltage higher than a reference voltage, a second terminal configured to receive and output a second power supply voltage higher than the first power supply voltage, an output control terminal to which a control signal for controlling a switching between an output permitted state and an output prohibited state is inputted, a first switching element provided between the first terminal and the second terminal and having a gate, a gate control circuit to which signals are inputted from the output control terminal and the second terminal, which supplies gate voltage to the gate of the first switching element, and which controls the first switching element to be conducting or to be non-conducting, and a second switching device provided between a power source of the second power supply voltage and the second terminal, and configured to switch between conducting and non-conducting in accordance with th

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d