Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.

Abstract: An analog buffer circuit (10) includes a first p channel field effect transistor (11), an n channel field effect transistor (12) and a second p channel field effect transistor (13). The transistors are connected to one another in serial between power supplying terminals (VDD and GND). The transistors have gates connected to an input terminal (IN) in common. An output terminal (OUT) is connected to a connecting point between the n channel transistor and the second p channel transistor. With this structure, output voltage which appears on the output terminal is approximately proportional to input voltage supplied to the input terminal.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A switch that selectively changes radio frequency signals includes at least three FETs, which are connected in series. The source electrodes or drain electrodes arranged at an intermediate stage have a width narrower than that of the source electrodes or the drain electrodes arranged at the initial and final stages. It is thus possible to lower the parasitic capacitance to ground at the intermediate stage and to thereby realize the switch having a high handling power.

Abstract: A driver circuit comprising an insulated gate bipolar transistor having a collector coupled to a voltage supply, an emitter coupled to a source of reference potential, and a gate configured to receive a control signal from a driver circuit, and a desaturation circuit conductively coupled between an insulated gate and a collector of the insulated gate bipolar transistor to desaturate the insulated gate. The desaturation circuit includes a series coupled bias voltage source, uni-directionally conducting element and switch.

Abstract: A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

Abstract: The present invention exploits the impact ionization induced by drain voltage increase and the onset of a bipolar parasitic in an ?-gate field effect metal oxide insulator transistor (called PI-MOS), in order to obtain a memory effect and abrupt current switching.

Abstract: The present invention provides a radiation-tolerant, solid-state-relay without radiation-hardened parts. In further detail, the solid-state-relay includes a non-hardened P-channel MOSFET, a low power storage of voltage gain and a feedback signal with the low power stage of voltage gain being relatively insensitive to radiation effects.

Abstract: To improve the ESD protection of a circuit receiving a signal. An inverter circuit INV1 is connected to ground wiring GND1 for supplying power, and is connected to power supply wiring VDD1 via a PMOS transistor MP5. An inverter circuit INV2 is connected to ground wiring GND2 and power supply wiring VDD2 for supplying power, and its input node is connected to an output node of the inverter circuit INV1. Further, the ground wiring GND1 and the ground wiring GND2 are connected via a protection element PE0. During normal operation, the output of an inverter circuit INV3 goes to an H level, the output of an inverter circuit INV4 goes to an L level, and the PMOS transistor MP5 is turned on. When ESD is applied, the power supply wiring VDD2 is place in a floating state, the output of the inverter circuit INV4 goes to an H level, the PMOS transistor MP5 is turned off, and a current that occurs when EDS is applied does not flow into the inverter circuit INV2.

Abstract: A circuit is disclosed, including a transistor switch having a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal; a determination circuit, coupled to the first terminal and the second terminal of the transistor switch, to determine a lower or higher voltage between the input voltage and the output voltage; a voltage generator, coupled to the determination circuit, to generate a sum voltage or difference voltage using the lower or higher voltage; and a control circuit, coupled to the voltage generator and the gate terminal of the transistor switch, to apply the sum voltage or difference voltage to the gate terminal of the transistor switch during a first time interval.

Abstract: A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

Abstract: A driver circuit comprising an insulated gate bipolar transistor having a collector coupled to a voltage supply, an emitter coupled to a source of reference potential, and a gate configured to receive a control signal from a driver circuit, and a desaturation circuit conductively coupled between an insulated gate and a collector of the insulated gate bipolar transistor to desaturate the insulated gate. The desaturation circuit includes a series coupled bias voltage source, uni-directionally conducting element and switch.

Abstract: A wireless device includes high-performance CMOS RF switches that include serially connected transistors coupled between an input terminal and an output terminal, with an inductor coupled from the input to the output that resonates out the capacitance of the transistors to improve isolation. The transistors have a floating/bootstrapped body with remote body contacts.

Abstract: The present invention relates to a switching circuit and a method of controlling a threshold voltage of a semiconductor switching element of the switching circuit, wherein a bulk voltage of the semiconductor switching element (Mi) is selected in response to a control signal derived from an output signal of the semiconductor switching element (Mi). Thereby, a fast switching circuit with hysteresis, smaller cross current and precisely adjustable threshold voltages can be provided.

Abstract: An analog switch comprises a first transistor, a second transistor, the drain and the source thereof being connected between said first input terminal and a second output terminal whereto said second signal is output and the gate thereof being grounded or connected to a supply voltage node, a third transistor, the drain and the source thereof being connected between a second input terminal whereto said second signal is input and said second output terminal and said third transistor being turned on and off by a control signal provided to the gate thereof; and a fourth transistor, the drain and the source thereof being connected between said second input terminal and said first output terminal and the gate thereof being grounded or connected to a supply voltage node.

Abstract: AnNchMOS transistor (1) is provided for muting of an output terminal (10) to which positive and negative output signals are outputted, and a mute switch circuit (3) is provided for controlling on/off of the transistor (1) by switching a voltage applied to the gate of the transistor (1). When muting is turned off, the back gate of the transistor (1) is biased by resistance division between resistors (R1 and R2) connected in series between the output terminal (10) and a predetermined negative potential (VSS).

Abstract: A voltage switching circuit is provided which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.

Abstract: Analog bidirectional switches (20) comprising a first (1) and a second (2) transistor function badly in case of the signal voltage at an input or an output of the switch (20) exceeding the supply voltage used for operating the switch (20). By providing the switch (20) with a circuit (21), a second control signal (“f”) destined for the second transistor (2) is no longer generated by solely inverting a first control signal (“e”) destined for the first tranistor (1), but is generated in response to the first control signal (“e”) and by taking into account the in/output signal (“z”) at an in/output of the switch (20). The circuit (21) comprises a generator (22) for generating the second control signal (“f”) having either a fixed value or a value of the in/output signal (“z”), and comprises a detector (23) for supplying the in/output signal (“z”) to the generator (22). A further circuit (24) comprises a further generator for generating a backgate signal (“bg”) destined for the second transistor (2).

Abstract: A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.

Abstract: A circuit device having a transistor-based switch topology that substantially eliminates the possibility of latchup of the device. A series-connected low voltage threshold (LVT) N-channel transistor and a pull-up resistor are coupled across a switching (P-channel) transistor so that an integral body connection is provided for the switching transistor, which connects the body of the switching transistor to a node between the pull-up resistor and source terminal of the LVT transistor. The LVT transistor is connected with its gate and drain terminal connected to the output terminal of the switching transistor. The resistor is connected at its other end to the power supply side terminal of the switching transistor. The addition of these components in the particular configuration allows the body connection of the switching transistor to be automatically switched to the highest potential diffusion node.

Abstract: A circuit and method for reducing losses in a DC/DC converter by optimizing gate drive voltage. The circuit and method detect a change in the output load, or more specifically the output current, and adjust the gate voltage accordingly; in other words, providing adaptive gate drive voltage. In response to a reduction of output current, the invention reduces the gate voltage so as to reduce both conduction and switching losses in the semiconductor switching devices in the output stage.

Abstract: Circuits and methods are provided for reducing the voltage stress applied to the drain to source conduction path of an FET and/or to reduce the stress to the gate oxide of an FET which may have a thin gate oxide. Thus, in a current mirror circuit disclosed herein, a first field effect transistor (FET) has a first gate and a first drain, in which the first drain is conductively connected to a current source for conducting a first current. The current mirror circuit also includes at least one second FET having a second gate conductively connected to the first gate, in which the second FET is operable to output a second current in fixed proportion to the first current. A switching element having a first conductive terminal is connected to the first gate and to the second gate, the second conductive terminal being connected to the first drain of the first FET.

Abstract: The signal transmission circuit comprises a first switch controls output according to a first control pulse, the first source follower outputting signals to the first output line based on signal input into the gate, a first capacitor connected between the gate and the source of the source follower, the first circuit, based on a level of the input signal, fixing the first output line to reference potential, the second switch controlling output according to a second control pulse, the second source follower, according to signals input into the gate, supplying output signals to the subsequent stage and also to a second output line, a second capacitor connected between the gate and the source of the source follower, and the second circuit, based on a level of input signals from the source, fixing the second output line to reference potential.

Abstract: A field effect transistor switch circuit may include: (1) first, second, and third switch terminals; (2) a first field effect transistor, a pair of the main electrodes of which are connected respectively to the first switch terminal and the second switch terminal; and (3) a second field effect transistor, a pair of the main electrodes of which are connected respectively to the first switch terminal and the third switch terminal. A first resistor is connected between a control electrode and any one of the pair of the main electrodes of the first field effect transistor, and a second resistor is connected between a control electrode and any one of the pair of the main electrodes of the second field effect transistor.

Abstract: A voltage switching circuit is disclosed which is constructed from a minimum number of transistors and prevents the threshold voltage margin from being lowered by causing high-voltage cutoff and supply voltage transfer functions heretofore performed by a single depletion transistor to be shared between two series-connected depletion transistors different in gate insulating film thickness or threshold voltage. Thus, without using enhancement transistors which involve an increase in pattern area a voltage switching circuit can be provided which is small in chip area, low in cost and high in yield and reliability and provides a stable operation with a low supply voltage which is impossible with one depletion transistor.

Abstract: The present invention provides a radiation-tolerant-solid-state-relay without radiation-hardened parts. A p-channel MOSFET provides power-switching functionality. In further detail, the solid-state-relay comprises a bias section, a control section, and a power-switch section. The bias section provides a voltage bias to the control section, the control section provides a control voltage to the power switch section as a function of the voltage bias, and the power switch section provides a switching voltage to the P-channel MOSFET as a function of the control voltage.

Abstract: A CMOS analog switch is provided that can handle negative input polarity. The semiconductor substrate wherein the analog switch is formed has a substrate area of n-conductivity type. First and second p-channel transistors are formed in the n-conductivity substrate area and each have a gate, a source connected to the input terminal and a drain connected to the output terminal. The analog switch further has a comparator for comparing a voltage level at the input terminal with ground level, a switch driven by an output of the comparator to selectively connect the n-conductivity area with the signal input terminal for a positive input voltage level or to ground for a negative input voltage level, and control circuitry providing gate control signals for the first and second p-channel transistors. The inherent substrate diodes are effectively kept from becoming conductive.

Abstract: A semiconductor integrated circuit device includes a semiconductor integrated circuit formed in a semiconductor chip, and a switching element that is formed in the semiconductor chip and has a current path whose one end and the other end are both connected to the semiconductor integrated circuit. The switching element receives a control signal produced by a control circuit and causes a current to flow from the one end to the other end of the current path by a bipolar operation. The semiconductor integrated circuit device further includes the control circuit that is formed in the semiconductor chip and configured to control a conductive/non-conductive state of the current path of the switching element.

Abstract: In charging a gate of a NMOS transistor Q1, the charging speed is adjustable by varying a resistor R1. When an inputted pulse signal VIN reverses to a negative voltage, a diode D2 turns off. Then, current flows along a discharging loop formed by the gate capacitor, the resistor R1, the emitter of the transistor Q2, the base of the transistor Q2, the resistor R2 and the capacitor C1, the transformer T1 and the source of the NMOS transistor Q1. A reverse bias voltage is applied to the gate of the NMOS transistor Q1, thereby keeping the NMOS transistor Q1off-state stably.

Abstract: RF phase distortion circuits and methods for controllably phase distorting an RF signal based on amplitude of the RF signal. An MOS device is provided having a body of a first conductivity type and at least one region of a second conductivity type in the body, with a conductive layer over at least part of the body and the region of the second conductivity type and insulated therefrom. The MOS device may be coupled into a phase distortion circuit individually or in back-to-back pairs and biased to invert the body under the conductive layer for small signal amplitudes and not for large signal amplitudes, or to not invert the body under the conductive layer for small signal amplitudes and to invert the body under the conductive layer for large signal amplitudes. Various embodiments are disclosed.

Abstract: A FET switching transistor for the solenoid coil of an ABS braking system can switched ON or OFF in no more than substantially 250 ns. A higher current biasing circuit for fast turn on of the FET switching transistor is disconnected when it is necessary to limit the current flowing therethrough, whether during the inrush current to the solenoid coil or due to a fault in the system. The high speed switching of the FET switching transistor causes ringing of the current through the transistor which causes the current detector circuit to exit the current control mode. A deglitch circuit prevents the current detector from exiting the current control mode, so that a timer can be used to turn off the FET switching transistor before it can be damaged by the heat generated during current limit operation.

Abstract: A first circuit which is constituted by a thin film resistor is connected between the collector of a transistor and a power supply terminal, and a second circuit which is constituted by a semiconductor resistor is connected between the emitter of the transistor and a grounding terminal. The film thickness of a thin film resistor is set to not more than its skin depth at a frequency to be compensated for.

Abstract: A current switching circuit has greatly reduced charge injection effects with the introduction of a mirror path to mirror the switch path. The mirror path comprises a complementary switch and a pulling amplifier, e.g., a pull-down amplifier for a source current switching circuit, or a pull-up amplifier for a sink current switch circuit. The pulling amplifier mirrors the status of an output path of a current source, e.g., a transistor current source, such that when the current source is switched ON or OFF, the switching process with respect to the load, e.g., a load capacitor, is smooth and provides a clean current waveform due to greatly reduced charge injection.

Abstract: The present invention provides a switching device comprising first to third connection terminals, a first FET provided with a pair of terminals one of which is connected, via a first direct-current blocking capacitive element, to the first connection terminal and the other of which is connected, via another first direct-current blocking capacitive element, to the second connection terminal, and a second FET provided with a pair of terminals one of which is connected, via a second direct-current blocking capacitive element, to the first connection terminal and the other of which is connected, via another second direct-current blocking capacitive element, to the third connection terminal. The channel type of the first FET is the same as the channel type of the second FET. A first bias voltage is applied to a gate of the first FET, and a second bias voltage is applied to both the main terminals of the second FET.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: An improved inkjet print head driver. The driver includes a source of predrive charge for a first, drive transistor coupled by its source and drain between an output node and a power supply, and having its gate coupled to the source of predrive charge. A second transistor is provided, adapted to receive an input signal at its gate. A third, control transistor is coupled by its source and drain between the gate of the first transistor and the second transistor, the second transistor being coupled by its source and drain between the third transistor and ground. Optionally, a resistor is coupled in parallel with the third transistor, i.e., across the source and drain of the third transistor.

Abstract: A method for use with a switch having a field-effect transistor (FET). The method includes restricting the drain-source voltage of the FET to a predetermined range, and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal, a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal, and a control circuit coupled to the gate terminal, the first gate, and the second gate.

Abstract: A voltage regulator circuit for providing a regulated output voltage at an output terminal, the regulator circuit including a current source (Icontrol) including a current source MOSFET a current mirror circuit including a driver MOSFET (M1) and a follower MOSFET (M2) interposed between the current source and the output terminal, the current source and current mirror being operatively linked as to regulate an input voltage Vin to the regulated output voltage, wherein the circuit further includes an EMC stabilising MOSFET having its drain connected to its substrate and placed in series with any of the driver or follower MOSFETs.

Abstract: In a bus driver for driving a bus having first and second power supply terminals, an input terminal for receiving an input signal and an output terminal connected to the bus, a switching element is provided between the output terminal and the second power supply terminal, and the switching element is controlled by a voltage at the input terminal. A pull-up resistor is connected between the first power supply terminal and the output terminal.

Abstract: In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signal from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.

Abstract: A high-frequency circuit, wherein there is provided a switching transistor connected between an input terminal and an output terminal, with a gate electrode connected to a control terminal via a resistance element, and with an effective gate portion of the gate electrode divided into a plurality of sections, and arrangement is made of additional capacitance elements added in parallel to a capacitance between a gate and a source or drain of the switching transistor at positions in proximity to one ends of at least two effective gate sections of the plurality of effective gate sections. Preferably, there is provided a short-circuiting transistor similarly having an additional capacitance element between the output terminal Tout and a reference voltage supply line.

Abstract: A bus switch is protected from undershoots on either of its terminals. The bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. During isolation, the gate node of the bus switch transistor is discharged to ground by a pulsed transistor, and then kept at ground by a leaker transistor. Sense-pulse circuits are attached to the first and second bus. When a low-going transition is detected by a sense-pulse circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off.

Abstract: An impedance compensation circuit and method for an input/output buffer provides dynamic impedance compensation by using programmable impedance arrays and a dynamically adjustable on-chip load. Accordingly, among other advantages, only a single off-chip or external calibrated impedance resistor is used and only a single test pad is necessary.

Abstract: Disclosed is a circuit for driving a gate of an IGBT (insulated gate bipolar transistor) inverter. The present invention includes a first IGBT of which collector is connected to a DC voltage, a second IGBT of which collector is connected to an emitter of the first IGBT, wherein an output signal is outputted from a connection point between the collector of the second IGBT and the emitter of the first IGBT, and of which emitter is connected to a ground, first and second driving circuits supplying gates and the emitters of the first and second IGBTs with DC driving voltages, respectively, through first and second gate resistors, and first and second noise interruption circuits connected between the gates-emitters of the first and second IGBTs and the first and second driving circuits, respectively, so as to interrupt noises.

Abstract: It is an object to suppress the influence of a noise pulse with a switching operation of a power switching element. A pulse generator (1) alternately outputs a pulse train having two pulses to outputs (A) and (B) synchronously with a signal input to a terminal (HIN). The pulse train is level shifted through switching elements (2) and (3) and resistive elements (8) and (9) which constitute a set of level shift circuits and is input to a flip-flop circuit (4). An output signal of the flip-flop circuit (4) is input to a control electrode of a power switching element (21) through a buffer circuit (35).

Abstract: A circuit, and a method and computer program product for use with a switch having a field-effect transistor (FET). The method and computer program product include restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.

Abstract: A circuit, and a method and computer program product for use with a switch having a field-effect transistor (FET). The method and computer program product include restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.

Abstract: A translation switch is described with a transfer MOS transistor that connects a first node to second node where the first node is referenced to a higher voltage than is the second. A pseudo-rail generator drives the gate of the MOS transistor and provides a p-rail reference voltage lower in voltage to that of the first node. The generator includes a selectively enabled active clamping circuit that clamps the gate of the MOS transfer transistor to the p-rail potential and sinks current from the p-rail when higher voltages appear on the p-rail to thereby maintain the p-rail at a substantially constant potential.

Abstract: A clock buffer circuit (100) for generating buffered clock signals (CLKI and CLKI_) in response to an external clock signal (CLKX) is disclosed. A first buffer section (102) drives to a first output node (114) between high and low logic levels in reponse the CLKX signal. To reverse the adverse effects of noise on the falling edges of CLKX signal, a boost section (108) and clock generator (106) are provided. In response to low-to-high transitions at the first output node (114) the pulse generator (106) generates a pulse at a pulse output (126). In response to the pulse, the boost section (108) provides additional driving capability for further pulling the first output node (114) to the high logic level. The first output node provides the CLKI_ signal. A second buffer circuit (104) provides the CLKI signal in response to the CLKI_ signal. An enabling section (110) is provided for enabling, or alternatively, disabling the preferred embodiment (100).

Abstract: The present invention provides a biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortion without affecting the transistor input or output impedance or any impedance matching network which may be used. In a preferred embodiment, the invention is incorporated in a latteral diffused metal-oxide semiconductor (LDMOS) transistor to reduce hysteresis brought about by a drain bias circuit without any impact on the transistor output impedance By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced.