Abstract: Techniques, systems and apparatus are described for providing a voltage selection circuitry and a DC-to-DC converter having such voltage selection circuitry. The voltage selection circuitry includes a first terminal voltage sensing unit that senses a voltage of a first terminal and a second terminal voltage sensing unit that senses a voltage of a second terminal. The voltage selection circuitry also includes a comparison unit connected to the first terminal voltage sensing unit and the second terminal voltage sensing unit. The comparison unit compares the voltage of the first terminal with the voltage of the second terminal and outputs a comparison signal indicating a difference between the sensed voltages of the first and second terminals. The voltage selection circuitry includes a selection unit that selects a higher voltage from the sensed voltages of the first and second terminals in response to the comparison signal.

Abstract: In an exemplary aspect of the invention, a clock signal amplifier circuit includes an amplifier circuit, a first switch part, and a second switch part. The amplifier circuit amplifies a clock signal. The first switch part controls ON/OFF of the amplifier circuit according to a select signal. The second switch part opens and closes complementarily to the first switch part according to the select signal. The amplifier circuit receives a test clock signal used in a test mode operation state through the second switch part. Further, the amplifier circuit outputs a signal generated by amplifying an input signal serving as the clock signal, or the test clock signal, according to the select signal.

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract: An analog multiplexer with an insulated power supply includes: an analog signal transformer receiving an analog signal input in its primary winding via an FET, and ON/OFF driving the FET to generate a pulse with an amplitude of the analog signal in its secondary winding; a drive transformer receiving a drive pulse input in its primary winding via an FET to generate a pulse turning ON/OFF the FET in its secondary winding; an inhibit generation circuit generating an inhibit pulse having a wider pulse width than that of the drive pulse; an AND gate determining a logical product of a continuous pulse from a continuous pulse generation circuit and the inhibit pulse to obtain a power supply pulse train; and a rectifying/smoothing circuit obtaining a direct current voltage corresponding to the power supply pulse train to apply the direct current voltage to the primary winding of the transformer through high resistance.

Abstract: A programmable delay element, variable-length delay chain, and ring oscillator are disclosed. The programmable delay element performs phase interpolation of input signals in response to a control signal and can be used in combination with other delay elements to create a highly-modular, variable-length delay chain or ring oscillator. The ring oscillator can be used as part of a digitally-controlled oscillator (DCO) in a digital clock synthesizer to adjust the frequency and phase of a clock signal by fractional unit delay steps. Within the variable-length delay chain, some programmable delay elements can be configured to scale the delay-step of other programmable delay elements so that a plurality of step sizes can be implemented with identical delay elements. Also, variations of the delay chain generate in-phase and quadrature phase (I/Q) signals in either an end-tap or center-tap configuration.

Abstract: The present invention relates to a detection circuit (100) capable to detect a rectified phase-cut or sinusoidal wave-form using its duty cycle or average value and in response, to select the respective dim mode amongst the linear phase-cut and step-dimming. The circuit (100) receives the rectified waveform with its duty cycle, which is derived through a comparator (22, 24) and converted into a DC signal. The latter which is controlled by the duty cycle is then compared to a reference level (40) through another comparator (20) that, in response, supplies a signal controlling a switching device (30). The switching device (30) will be thus automatically connected either to one set signal level when the DC signal is greater than the reference level (40), namely when the circuit (100) detects a rectified sinusoidal waveform, or to the same level as the DC signal when the DC signal is less than the reference level (40), namely when the circuit (100) detects a rectified phase-cut waveform.

Abstract: Signals are coupled to and from stacked semiconductor dies through first and second sets of external terminals. The external terminals in the second set are connected to respective conductive paths extending through each of the dies. Signals are coupled to and from the first die through the first set of external terminals. Signals are also coupled to and from the second die through the conductive paths in the first die and the second set of external terminals. The external terminals in first and second sets of each of a plurality of pairs are connected to an electrical circuit through respective multiplexers. The multiplexers in each of the dies are controlled by respective control circuits that sense whether a die in the first set is active. The multiplexers connect the external terminals in either the first set or the second set depending on whether the bonding pad in the first set is active.

Abstract: Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1 and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

Abstract: A system comprises a load and a voltage regulator. The voltage regulator is configured to select a gate drive signal from among a plurality of input voltages. The voltage regulator is configured to use the selected gate drive signal to turn on a power transistor to produce a regulated voltage for the load.

Abstract: Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

Abstract: A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

Abstract: Circuits and methods for a differential signal interface for coupling differential signals at a first frequency on a pair of opposite polarity signals to a multiple gigabit transceiver with generic buffers for receiving, transmitting or transceiving out of band signals at a second frequency lower than the first frequency are disclosed. Termination networks are provided coupling generic input buffers to respective ones of the pair of opposite polarity signals for receiving out of band signals where the opposite polarity signals are placed at voltages so that the differential voltage between them is below a threshold voltage. Methods for providing generic buffers with multiple gigabit transceivers for receiving and transmitting out of band signals on a differential signal interface are provided. Out of band signals are received when the out of band signaling protocol is not known.

Abstract: A fraction-N frequency divider includes a multi-phase clock generator, a first phase selector, a second phase selector, a glitch-free multiplexer, a control circuit, and a counter. The multi-phase clock generator is used for generating a plurality of clock signals with different phases. The first phase selector selects one of the clock signals as a first clock signal according to a first phase selecting signal. The second phase selector selects one of the clock signals as a second clock signal according to a second phase selecting signal. The glitch-free multiplexer is used for selectively outputting one of the first and second clock signals. The control circuit generates the first and second phase selecting signals and controls the clock switching timing of the glitch-free multiplexer according to a divisor setting. The counter is used for generating a frequency-divided signal according to the output of the glitch-free multiplexer.

Abstract: An integrated circuit high voltage analog switch has digital logic-level control interface circuit. A level translator is coupled to the digital logic-level control interface circuit. A plurality of output multi-channel high voltage switches is coupled to the level translator.

Abstract: An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

Abstract: A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A multi-voltage multiplexer system includes multiple voltage inputs, each voltage input providing a different input voltage, and multiple control inputs operative to select one of the input voltages for output. Each of multiple transistors is connected to a different one of the voltage inputs and to a different one of the control inputs, and the transistors are connected to an output such that the selected input voltage is provided at the output. A bulk of each of the transistors is connected together to form a bulk network, and the bulk network is connected to the gate of each transistor such that the transistors connected to non-selected voltage inputs have gates set at approximately the maximum of the input voltages.

Abstract: According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.

Abstract: A method for configuring a signal path within a digital integrated circuit. The method includes transmitting an output from a first logic module, receiving the output at a second logic module, and conveying the output from the first logic module to the second logic module by using a configurable signal path. The configurable signal path is variable by selectively including at least one latch.

Abstract: A first switching circuit has an input for receiving a first input signal, and a second switching circuit has an input for receiving a second input signal. A node is connected to receive outputs from both the first and second switching circuits. A filter receives an unfiltered signal from the node to generate an output signal. A circuit is provided to alternately actuate the first and second switching circuits during a transition time period so as to smoothly transition the output of the filter between the first and second input signals. At least one of the first and second input signals is a time-varying analog signal. The smooth transition between the first and second input signals has a shape determined by pulse width and frequency characteristics of pulses output by the circuit to alternately actuate the first and second switching circuits. The shape may include a linear ramp, an S-shaped curve, a parabolic curve and a hyperbolic curve.

Abstract: A voltage regulator arrangement having a first voltage regulator, whose input connection is connected to the supply potential connection and whose output connection is connected to a first supply potential connection of a circuit arrangement, with the first voltage regulator supplying the circuit arrangement with a supply voltage in a rest state. A second voltage regulator is also provided, whose input connection is connected to the supply potential connection, and whose output connection is connected to a second supply potential connection of the circuit arrangement, with the second voltage regulator supplying the circuit arrangement with a supply voltage during its normal operation.

Abstract: An interface system delivers an output signal having a first signal characteristic in response to first and second input signals having the first signal characteristic and a second, different signal characteristic. The interface system includes a signal input for receiving a first signal having a first signal characteristic and a second signal having a second signal characteristic which is different from the first signal characteristic, a detector circuit for detecting whether the signal at the input is the first signal or the second signal, and a translator circuit for translating either of the first signal or the second signal into the output signal.

Abstract: A logic module (400) that is capable of implementing data-path and random logic (command Z in block 42) uses control logic for selectively coupling one or more of the input terminals (10, 12, 14, 16, 18, 40) to the at least one output terminal (20). The control logic comprises a plurality of logic elements (26, 28, 30, 32) arranged to generate a first set of two-input logic functions (f, (a, b)) and a programmable inverter (36) arranged to generate a second set of two-input logic functions, the second set of two-input logic functions being the complement functions of the first set of two-input logic functions. SRAM memory cells (4 bit memory batch (38)) may be used for configuration purposes, realizing a compact logic module or block that is also re-programmable.

Abstract: A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.

Abstract: A semiconductor module is provided. Multiple external terminals are connected to an external circuit. Each semiconductor chip includes multiple pads. Wiring lines connect the multiple pads provided to each of the multiple semiconductor chips and the corresponding external terminals or corresponding different pads, respectively. Multiple input terminals of a switch are connected to corresponding internal nodes included within the semiconductor module, and an output terminal thereof is connected to a monitoring terminal provided as an external terminal. The switch makes a connection between the output terminal and one input terminal selected from among the multiple input terminals.

Abstract: A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.

Abstract: A semiconductor device includes an external pin, a control parameter decision circuit, and a register update circuit. The control parameter decision circuit includes a register and an output selector. The register is initialized in accordance with resetting of the semiconductor device. The output selector, according to a level value of an external input signal supplied via the external pin, selects one of a signal whose level value is set equal to a register value of the register and a signal whose level value is set opposite to the register value of the register, and outputs the selected signal as a control parameter signal. The register update circuit updates the register value of the register when a level value of the control parameter signal need be changed.

Abstract: A power supply circuit for a pulse width modulation controller includes a first resistor and an electric switch having first, second, and third terminals. The first terminal is capable of receiving a control signal of a computer. The second terminal is connected to a stand-by power supply of the computer. The third terminal is connected to the pulse width modulation controller via the first resistor.

Abstract: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.

Abstract: An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.

Abstract: A signal output circuit adapted to a selector circuit is constituted of an inverter circuit which activates propagation of an input signal therethrough in an active level of a control signal and which inactivates it in an inactive level of the control signal, and a control circuit which maintains the input terminal of the inverter circuit at a predetermined potential irrespective of the level of the input signal in the inactive level of the control signal. This achieves high-speed and high-precision propagation of the input signal. The selector circuit is formed using a plurality of signal output circuits so as to selectively output one of first and second input signals in response to the control signal.

Abstract: An integrated circuit includes a power amplification circuit and a switch circuit wherein the switch circuit is coupled to an output of the power amplification circuit, a bypass input, and a control input, such that the switch selectively couples the power amplification circuit output or the bypass input to an output of the integrated circuit.

Abstract: To provide an analog multiplexer capable of extending the frequency characteristic of the analog multiplexer in terms of frequency band.

Abstract: The present invention discloses a voltage level generating device. The voltage level generating device includes: a reference voltage generating module, a first circuit module, a second circuit module, and a switch module. The voltage level generating device disclosed in the present invention only requires a buffer, a voltage regulator, and a arithmetic logic unit (ALU) to attain the same function of the conventional common voltage level generating device, and thus the circuit layout area can be reduced so as to decrease the cost of the integrated circuit (IC). In addition, the voltage level generating device disclosed in the present invention also can select different output of voltage level in order to reduce the power consumption of a display device.

Abstract: A clock synchronization unit is provided for an electronic system, particularly for a microprocessor, that includes a first input for a first clock signal, a second input for a second clock signal, a third input for a select control signal, and an output for a system clock signal. A first control module controlled by the first clock signal, a second control module controlled by the second clock signal and connected to the first control module in terms of signaling technique is also provided. The first control module upon application of a predefined signal level of the select control signal at the third input synchronously with the first dock signal, is designed to set the system clock signal from the first clock signal to a predefined logic signal level as the system clock hold signal, and the second control module is designed, synchronously with the second clock signal, to reset the system clock hold signal and to cause an output of the second clock signal as the system clock signal.

Abstract: A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different.

Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.

Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: The invention provides a signal coupling circuit and method for coupling an analog input signal to a processing circuit. The signal coupling circuit includes a number of first coupling units, a second coupling unit and a first multiplexer. The first coupling units are coupled to a first input terminal of the processing circuit, for respectively receiving a plurality of input signals. The first multiplexer is coupled between the first coupling units and the processing circuit for selecting one of the input signals and transmitting the selected input signal to the processing circuit. The second coupling unit is coupled to a second input terminal of the processing circuit, for receiving a common reference signal, wherein the processing circuit uses the common reference signal as reference for processing some or all of the input signals.

Abstract: An integrated circuit having cascade-connected multiplexers and a precharge unit. The cascade-connected multiplexers each have a plurality of data inputs, a data output, wherein each data input and each data output has two terminals for the application of a dual-rail signal, and a control input, wherein a signal present at the control input defines which of the data inputs is connected to the data output. The precharge unit, which is driven with a precharge unit control signal, is connected to the data output or at least one of the data inputs of one of the multiplexers to thereby bring the data outputs and/or data inputs of the multiplexers into a precharge state before execution of a computation operation.

Abstract: A voting scheme for analog signals is described. An analog block is replicated to provide three analog blocks that are designed to have substantially the same analog output based on receiving substantially the same input. Voting is used to compare the analog outputs from the three analog blocks. In one example, the analog output from one of the three analog blocks having a middle value between the values of the other two analog outputs is provided as an output of the voter circuit. In another example, if the original analog block provides the analog output having the middle value, the output of the original analog block is provided as an output of the voter circuit. Otherwise, an output of another analog block is provided as an output of the voter circuit. In another example, the analog voter circuit determines which of the three analog outputs have been impacted by a transient event based on a non-zero output of transconductor circuits.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A signal conversion circuit for converting an inputted differential signal into a single-ended signal comprises a differential amplifier circuit for amplifying the differential signal, and generating a first non-inverted signal and a first inverted signal being inverted the first non-inverted signal, a first inverter for generating a second non-inverted signal being inverted the first inverted signal and an interpolation unit for interpolating a phase difference between the first non-inverted signal and the second non-inverted signal.

Abstract: Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

Abstract: An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the well of the PMOS FET switch will not allow the drain/source to well diode to be forward biased. In a second case, a second power rail is logically coupled to the lower of either and input signal or ground, wherein the well of the NMOS FET will not allow the drain/source to well diode to be forward biased.

Abstract: The present invention relates to a semiconductor integrated-circuit device capable of seamlessly switching a power source obtained by rectifying a carrier wave and an external power source. The semiconductor integrated-circuit device having a non-contact card function and a non-contact reader/writer function includes a rectifier 131 for rectifying a received carrier wave, a serial regulator 132for obtaining a predetermined voltage from an output voltage of the rectifier 131, and a power-supply control circuit 138 for turning on/off the voltage from a battery 160. In a case where the output voltage of the battery 160 is equal to or higher than a predetermined voltage, the power-supply control circuit 138 selects the voltage of the battery 160 as power required for operation of an IC 300 when a reader/writer mode signal or a card mode signal is received.

Abstract: A passive CMOS differential mixer circuit with a mismatch correction circuit for balancing the electrical characteristics of the two output paths. Once the output paths of the differential circuit are balanced, or matched as closely as possible, second order intermodulation product generation can be inhibited or at least reduced to acceptable levels. The mismatch correction circuit receives a digital offset signal, and generates one or more voltage signals to be selectively applied to the signal paths of the passive differential mixer circuit. The voltage signals can be adjusted back gate bias voltages applied to the bulk terminals of selected transistors to adjust their threshold voltages, or the voltage signals can be adjusted common mode voltages applied directly to a selected signal path. Since the differential mixer circuit is passive, no DC current contribution to noise is generated.