Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: An analog multiplexer with an insulated power supply includes: an analog signal transformer receiving an analog signal input in its primary winding via an FET, and ON/OFF driving the FET to generate a pulse with an amplitude of the analog signal in its secondary winding; a drive transformer receiving a drive pulse input in its primary winding via an FET to generate a pulse turning ON/OFF the FET in its secondary winding; an inhibit generation circuit generating an inhibit pulse having a wider pulse width than that of the drive pulse; an AND gate determining a logical product of a continuous pulse from a continuous pulse generation circuit and the inhibit pulse to obtain a power supply pulse train; and a rectifying/smoothing circuit obtaining a direct current voltage corresponding to the power supply pulse train to apply the direct current voltage to the primary winding of the transformer through high resistance.

Abstract: An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current.

Abstract: Disclosed herein is a multiplexer circuit. The multiplexer circuit includes a first differential output unit, a second differential output unit, and a selection unit. The first differential output unit receives NRZ input signals (D1 and D1) and a clock signal (CLK), and generates differential RZ-mode outputs (R1 and R1). The second differential output unit receives NRZ input signals (D2 and D2) and an inverted clock signal ( CLK), and generates differential RZ-mode outputs (R2 and R2). The selection unit receives the RZ-mode output signals (R1, R1, R2, and R2) generated at the first differential output unit and the second differential output unit, and generates NRZ mode outputs in each half cycle of the clock signal (CLK).

Abstract: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.

Abstract: An integrated circuit high voltage analog switch has digital logic-level control interface circuit. A level translator is coupled to the digital logic-level control interface circuit. A plurality of output multi-channel high voltage switches is coupled to the level translator.

Abstract: A system for operating a transducer comprising, a first node connected to a first transducer, a first photo-activated switching device having a first source, a first drain connected to the first node, and a first gate operative to receive a first logic signal, a first terminal connected to the first source; a second photo-activated switching device having a second source connected to the first node, a second drain, and a second gate operative to receive a second logic signal, and a second terminal connected to the second drain.

Abstract: Circuits, methods, and apparatus that provide isolation between receive and transmit circuits in a wireless transceiver. One example provides switches that can be included on an integrated circuit with at least portions of a wireless transceiver. These switches vary the impedance of transmitter and receiver circuits between a termination impedance and a high impedance by inserting or removing components in parallel with matching networks. Signal losses are minimized since these switches are shunt connected to input and output paths on the wireless circuit and are not connected directly in either signal path.

Abstract: A multi-voltage multiplexer system includes multiple voltage inputs, each voltage input providing a different input voltage, and multiple control inputs operative to select one of the input voltages for output. Each of multiple transistors is connected to a different one of the voltage inputs and to a different one of the control inputs, and the transistors are connected to an output such that the selected input voltage is provided at the output. A bulk of each of the transistors is connected together to form a bulk network, and the bulk network is connected to the gate of each transistor such that the transistors connected to non-selected voltage inputs have gates set at approximately the maximum of the input voltages.

Abstract: A first switching circuit has an input for receiving a first input signal, and a second switching circuit has an input for receiving a second input signal. A node is connected to receive outputs from both the first and second switching circuits. A filter receives an unfiltered signal from the node to generate an output signal. A circuit is provided to alternately actuate the first and second switching circuits during a transition time period so as to smoothly transition the output of the filter between the first and second input signals. At least one of the first and second input signals is a time-varying analog signal. The smooth transition between the first and second input signals has a shape determined by pulse width and frequency characteristics of pulses output by the circuit to alternately actuate the first and second switching circuits. The shape may include a linear ramp, an S-shaped curve, a parabolic curve and a hyperbolic curve.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: A redundant power supply connected to a common load is provided. Each power supply is connected to the common load through a series of MOSFET pairs. Each MOSFET in a MOSFET pair is individually controlled to reduce power consumption as well as the need for heat sinks on discrete diodes. Moreover, by providing individually controllable MOSFETs the present invention is capable of switching between power supplies without shorting the power supplies or having a significant drop in bus voltage.

Abstract: A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.

Abstract: A power up biasing circuit for a split power supply based circuit includes a split power supply state sensing circuit that produces a pair of complimentary control signals indicating a presence or absence of a suitable biasing power supply voltage. A pseudo power supply voltage, based on a first power supply is selected by a selector circuit for acting as a biasing voltage for one or a plurality of components to be protected during initial power up where there is an absence of a second power supply voltage, based on the pair of complimentary control signals. Once the second power supply voltage has fully ramped up to steady state, the selector circuit selects the second power supply voltage as the biasing voltage for one or a plurality of component to be protected.

Abstract: A low jitter, high phase resolution phase lock loop incorporating a ring oscillator-type VCO is designed and constructed to operate at a characteristic frequency M times higher than a required output clock frequency. Multi-phase output signals are taken from the VCO and selected through a Gray code MUX, prior to being divided down to the output clock frequency by a divide-by-M frequency divider circuit. Operating the VCO at frequencies in excess of the output clock frequency, allows jitter to be averaged across a timing cycle M and further allows a reduction in the number of output phase taps, by a scale factor M, without reducing the phase resolution or granularity of the output signal.

Abstract: Clock multiplexing techniques generate an output clock signal by detecting edges of a selected input clock signal and toggling the output clock signal based on detected edges of the selected input clock signal. Toggle signals are generated based on detected edges of the selected input clock signal. Toggle signals are used to control when the output clock signal is to toggle high or low. A latch holds the state of the output clock signal in its current state until changed by receipt of a toggle signal. Switching from use of a first clock signal to use of a second clock signal occurs regardless of whether the first input clock is operating. A delay is introduced that prevents glitches in the output clock signal that are less than one half clock period of the next selected input clock signal in duration.

Abstract: To provide an analog multiplexer capable of extending the frequency characteristic of the analog multiplexer in terms of frequency band.

Abstract: A back-up power supply system includes, in one embodiment, a threshold detector circuit; a first switching circuit for enabling access to a back-up power source, the first switching circuit comprising at least a first transistor; and an inverting switch coupled between the first switching circuit and the threshold detector circuit, the inverting switch comprising an input and an output, the inverting switch configured to receive a signal at the input, invert the signal, and provide the inverted signal from the output to the first switching circuit, the inverting switch further comprising a delay circuit, the delay circuit configured to provide a substantially-immediate high-output during an off-to-on transition at the output of the inverting switch and a switching delay during an on-to-off transition at the output of the inverting switch, the inverting switch comprising a first resistive branch in parallel to a second branch comprising the delay circuit, the first resistive branch and the second branch connec

Abstract: A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different.

Abstract: A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge.

Abstract: Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

Abstract: Methods and apparatus for utilizing a solid state relay arrangement as a part of a protection scheme for a telecom wireline card suitable are disclosed. According to one aspect of the present invention, a line card that is suitable for use in an optical network device includes an electrical port, a plurality of input lines, an output line, and protection circuitry. The protection circuitry switches or multiplexes the plurality of input lines into the output line, and includes a solid state relay arrangement and power isolation circuitry. The power isolation circuitry provides a high impedance to power rails associated with the solid state relay arrangement, and the solid state relay arrangement includes at least one N-channel field effect transistor (FET), at least one protection diode, and at least one charge pump.

Abstract: A double pole single throw (DPST) switch circuit including a first circuit portion corresponding to a first input port, a second circuit portion corresponding to a second input port, and an output port, wherein each of the first and second circuit portions include at least one first transistor providing a portion of an isolation channel, at least one second transistor providing a portion of a transmit channel, and at least one third transistor for providing a control bias for selecting either the transmit channel or the isolation channel.

Abstract: Integrated circuit devices include operational circuits that are configured to operate from power supply voltages and from high voltages that are generated in the integrated circuit device from the power supply voltages. A circuit for measuring the high voltages is also provided in the integrated circuit. The circuit includes a common high voltage measurement pad and high voltage switch units connected to the common high voltage measurement pad. A respective high voltage switch unit is configured to transmit a corresponding one of the high voltages to the common high voltage measurement pad in response to a corresponding enable signal. The operational circuits may be non-volatile memory cells, such as flash memory cells. Related methods of measuring high voltages in an integrated circuit device are also described.

Abstract: An (SST) driver circuit having additional circuitry for minimizing data-dependent jitter in the SST driver and increasing frequency amplitude in the SST driver. The additional circuity comprises a plurality of switches configured to be turned on or pulsed on momentarily during operation to discharge a node in the SST output stage for the purpose of removing the stored charge before the next transition cycle of the output stage.

Abstract: A power efficient multiplexer. In accordance with a first embodiment of the present invention, a power efficient multiplexer comprises a transmission gate structure for selectively passing one of a plurality of input signals and a stacked inverter circuit for inverting the one of a plurality of input signals. Both the stacked inverter and the transmission gate provide beneficial reductions in static power consumption in comparison to conventional multiplexer designs.

Abstract: A first switch circuit includes first and second N-type MOSFETs. A second switch circuit includes third and fourth N-type MOSFETs. A control signal is input to a first inverter and a third inverter, the output of the first inverter input to a second inverter and the gate of the fourth MOSFET, the output of the second inverter input to the gate of the first MOSFET, the output of the third inverter input to a fourth inverter and the gate of the third MOSFET, the output of the fourth inverter input to the gate of the second MOSFET. A first input voltage is connected to the source of the second MOSFET and the sources of N-type MOSFETS in the third and fourth inverters. A second input voltage is connected the source of the fourth MOSFET and the sources of N-type MOSFETS in the first and second inverters.

Abstract: According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.

Abstract: A MOSFET-based, multi signal-switching circuit controllably passes analog/audio signals and digital signals through a common terminal to a single connector. Analog/audio signals are coupled through a single N-channel MOSFET analog signal switch which, when turned-ON, minimizes distortion of the analog/audio signal and capacitive loading to an adjacent, MOS-based or CMOS-based digital data signal switch. A respective turn-OFF circuit maintains its associated switch MOSFET turned OFF.

Abstract: A dual mode comparator circuit is disclosed. The dual mode comparator includes a plurality of differential transistor pairs. Each differential transistor pair includes a plurality of inputs and outputs. The outputs of the differential transistor pairs are coupled to inputs of a multiplexor. The multiplexor includes at least one control input for selecting between the multiplexor inputs and provides the selected input to the multiplexor output. The dual mode comparator further includes a comparator back end that is coupled to the output of the multiplexor. The comparator back end may include a folded cascode and additional gain stages. The comparator back end provides the comparator output to the next stage. The dual mode comparator may be used in automatic testing equipment embodiments.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.

Abstract: A serializer is described that incorporates a register and a delay circuit for each serial bit. The serializer provides a timing signal that is generated and output simultaneously with the output of the data bit that ensures close timing alignment of the data bit and the timing signal. No clock is used. This allows the deserialzer/receiver to reliably receive the data bit. Each illustrative delay circuit is configured to trigger the next register/delay circuit to output the next sequential bit and its timing signal.

Abstract: An integrated circuit system comprising: forming an analog switch including: providing a current source for driving the analog switch, coupling a first source follower to the current source for forming a first input to the analog switch, coupling a second source follower to the current source for forming a second input to the analog switch, and coupling a switch to the first source follower and the second source follower for selecting the first input, the second input, or a combination thereof; and selecting a voltage output signal from the first source follower, the second source follower, or a combination thereof including isolating the first input from the second input.

Abstract: A selection circuit includes a first switching unit that selects and outputs a first signal from among a plurality of analog signals input thereto; a second switching unit that outputs a second signal from a reference voltage supplied therein; and an amplifier that adds the first signal and the second signal.

Abstract: An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.

Abstract: A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: An embodiment of this invention provides a circuit and method for reducing the number of electronic components needed to calibrate circuits on an IC. A multiplexer is located on the IC where the outputs of a plurality of circuits located on the IC are each connected to a separate data input of the multiplexer. The control input of the multiplexer selects which data input of the multiplexer is connected to an external component. Each data input is individually connected to the component periodically.

Abstract: Systems and methods are discussed for using a floating-gate MOSFET as a programmable reference circuit. One example of the programmable reference circuit is a programmable voltage reference source, while a second example of a programmable reference circuit is a programmable reference current source. The programmable voltage reference source and/or the reference current source may be incorporated into several types of circuits, such as comparator circuits, current-mirror circuits, and converter circuits. Comparator circuits and current-mirror circuits are often incorporated into circuits such as converter circuits. Converter circuits include analog-to-digital converters and digital-to-analog converters.

Abstract: A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.

Abstract: A multiplexer circuit provided herein includes a plurality of pass devices coupled in parallel between a power supply and a ground supply. According to one embodiment, each pass device may include a first pair of transistors, which is coupled in series between the power supply and the ground supply, and a second pair of transistors, which is coupled to the first pair of transistors for controlling a current passed there through. In general, the second pair of transistors may be configured for increasing the amount of current passed through the first pair of transistors. For example, the second pair of transistors may utilize a bootstrapping effect to increase a pair of control voltages supplied to the gate terminals of the first pair of transistors. The increased control voltages function to over-drive the gate terminals of the first pair of transistors, thereby increasing the amount of current passed there through.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.

Abstract: A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selection signal for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the selection signal. Generating an output signal from the high-speed MUX circuit may include generating the single selection signal therein and transmitting one of the first and second input signal as a MUX circuit output signal, based on the single selection signal.

Abstract: A voltage transfer circuit outputs an equivalent to an input voltage when enabled. Otherwise, the transfer circuit is in standby and outputs an equivalent to a standby voltage (e.g., signal ground). The voltage transfer circuit includes a switching circuit, a standby circuit, and an input-transfer circuit. The output of the transfer circuit is fed back to both the switching circuit and the input-transfer circuit. When the transfer circuit is in standby, the feedback of the output voltage provides for voltage-balancing in the input-transfer circuit, thereby reducing or eliminating leakage current in the input-transfer circuit. Similarly, when the transfer circuit is in active mode, the feedback of the output voltage provides for voltage-balancing in the standby circuit, thereby reducing or eliminating leakage current in the standby circuit.

Abstract: A semiconductor device, which may be changed to a mirror package after the assembly without having to reinstall bonding wires, comprises: a plurality of fixed external terminals which include a power supply external terminal and a ground potential external terminal and which are arranged symmetrically in fixed positions; a plurality of variable external terminals of different types which are arranged symmetrically; a plurality of reverse-polarity selection external terminals which are symmetrically arranged in fixed positions, and a signal switching circuit which switches the arrangement of the symmetrically arranged variable external terminal according to the setting of the selection terminal.

Abstract: A power supply voltage switch circuit for selecting a power supply voltage of an integrated circuit according to a first control signal. The power supply voltage switch circuit contains a high voltage selecting module for generating an output voltage according to the higher of a first and a second voltages; a level shifting module electrically connected to the high voltage selecting module to receive the output voltage as power supply, for performing level shifting to a first control signal according to the output voltage; and a selecting switch module electrically connected to the level shifting module for selectively outputting the first or the second voltage as the power supply voltage of the integrated circuit according to the level-shifted first control signal.

Abstract: An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

Abstract: A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL1) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN1) and a PMOS transistor (MP1) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN1) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP1) compensates for voltage undershoot conditions at the pad.

Abstract: The invention discloses a semiconductor switching circuit suitable for a Single Pole n Throw (SPnT) switching circuit having: a common terminal; first through third terminals, ground and control terminals, through FETS, shunt FETs, wherein when a first electric potential is supplied only to a Jth control terminal, and a second lower electric potential is supplied to the other control terminals, the common and Jth terminals are electrically connected and the first through third terminals are electrically disconnected.