Abstract: Methods related to controlling switches. In some embodiments, a method for controlling a radio-frequency switch can include providing or generating a control signal to allow generation of a plurality of reference levels by a regulator, or to allow the regulator to be in sleep mode. The method can further include operating the regulator based on the control signal to generate the plurality of reference voltage levels for operation of the radio-frequency switch, or to be in the sleep mode.

Abstract: An output driving system includes an output driver, a first ESD (Electrostatic Discharge) protection circuit, a second ESD protection circuit, a first differential amplifier, a second differential amplifier, a first capacitor, and a second capacitor. The output driver has a first output node for outputting a first output voltage, and a second output node for outputting a second output voltage. The first differential amplifier generates a first amplified voltage according to the first output voltage and the second output voltage. The first capacitor has a first terminal for receiving the first amplified voltage, and a second terminal coupled to the first output node. The second differential amplifier generates a second amplified voltage according to the first output voltage and the second output voltage. The second capacitor has a first terminal for receiving the second amplified voltage, and a second terminal coupled to the second output node.

Abstract: Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.

Abstract: A charge pump circuit generates a charge pump voltage that powers a bias circuit. The bias circuit generates a reference current and generates switch currents from the reference current. Gate-source voltages are generated from the switch currents and applied to switching components of switch circuits to connect two nodes. The gate-source voltages can be generated in the bias circuit and provided to the switch circuits. The gate-source voltages can also be generated in the switch circuits.

Abstract: An integrated circuit comprises an ADC including a first track-and-hold amplifier and a timing generator configured to generate a clock signal for controlling the ADC. The timing generator comprises a quadrature filter responsive to a differential input signal for generating a differential quadrature (I/Q) output signal. The timing generator further comprises at least one first vector sum circuit operatively coupled or connected to an output of the quadrature filter and configured to weight and sum components of the differential I/Q output signal for generating a clock signal having a desired delay.

Abstract: In one embodiment, a voltage comparator circuit includes a first comparator circuit to compare a first voltage and a second voltage and a second comparator circuit to compare the first voltage and the second voltage. The voltage comparator circuit may include charge storage circuitry and positive feedback circuitry. Such circuitry may boost current within the first and second comparator circuits to enable the voltage comparator circuit to output a comparison decision within a delay threshold in response to input transitions within a slew rate threshold.

Abstract: According to one embodiment, a semiconductor switch includes a power supply, a driver, a switch section, and a first potential controller. The power supply includes a first potential generator and a second potential generator. The first potential generator is configured to generate a negative first potential. The second potential generator is configured to generate a positive second potential that a power supply potential is stepped down. The driver is supplied with the first potential and a third potential and configured to output at least one of the first potential and the third potential based on a terminal switching signal. The switch section is configured to connect a common terminal to any one of a plurality of radio frequency terminals according to an output of the driver. The first potential controller includes a divider and an amplifier.

Abstract: A multiplexing circuit comprising an converter for converting an input voltage signal to an input current signal. A plurality of first current mirrors for mirroring the input current signal. A switching unit selectively switches each first current mirror to a corresponding output.

Abstract: A system is provided that includes an input node configured to receive a signal indicative of sensor data. The system also includes a first transistor configured to route the signal to a positive channel when a polarity of the signal is positive. Moreover, the system includes a second transistor configured to route the signal to a negative channel when a polarity of the signal is negative. Additionally, the system includes the positive channel coupled to the first transistor configured to route the signal to an analysis component. Furthermore, the system includes the negative channel coupled to the second transistor and configured to route the signal to the analysis component.

Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.

Abstract: According to one embodiment, a semiconductor switch includes a power supply, a driver, a switch section, and a first potential controller. The power supply includes a first potential generator and a second potential generator. The first potential generator is configured to generate a negative first potential. The second potential generator is configured to generate a positive second potential that a power supply potential is stepped down. The driver is supplied with the first potential and a third potential and configured to output at least one of the first potential and the third potential based on a terminal switching signal. The switch section is configured to connect a common terminal to any one of a plurality of radio frequency terminals according to an output of the driver. The first potential controller includes a divider and an amplifier.

Abstract: According to one embodiment, a semiconductor switch includes a voltage generator, a voltage controller, a driver, and a switch unit. The voltage generator generates a negative first potential. The voltage controller controls the first potential according to a terminal switch signal input from an outside. The driver is input the terminal switch signal, and outputs at least one selected from the first potential and the second potential based on the terminal switch signal. The second potential is a power supply voltage or is higher than the power supply voltage. The switch unit is provided on an SOT substrate, switches a connection between an antenna terminal and any one of high frequency terminals based on the output of the driver.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: A logic signal transmission circuit includes a driving circuit, an isolation section, and a latch section. The driving circuit converts an input digital signal to a differential digital signal. The isolation section blocks direct current and passes the differential digital signal. The latch section has even numbers of inverters which are connected in a loop and output a logic signal by turning ON and OFF a power supply voltage in a complementary manner. An input impedance of the latch section is set so that when a logic level of the differential digital signal changes, a transient voltage inputted through the isolation section to the latch section changes across a threshold voltage of the latch section. When the transient voltage changes across the threshold voltage, a logic level of the logic signal changes.

Abstract: In a measuring device, the measured data of a data recording component (10) are transmitted to an evaluating component via an output device (12). Parameters of the measuring device are stored in a memory (18). For the purpose of parameterization, parameters from the evaluating component can be stored in the memory (18) over a data cable for transmitting the measured data. To this end, the output device (12) for this data cable (Z) is operated at high impedance.

Abstract: An integrated circuit can comprise: a first port, a second port, and a third port; and a plurality of microwave operational amplifiers coupled to each other and the first port, the second port, and the third port. The plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the first port to the second port while substantially isolating the signal provided to the first port from the third port; the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the second port to the third port while substantially isolating the signal provided to the second port from the first port; and the plurality of microwave operational amplifiers can be arranged to substantially pass a signal provided to the third port to the first port while substantially isolating the signal provided to the third port from the second port.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: A switch control circuit has a first terminal, a second terminal, a third terminal, a serial-parallel converter, a selector, a driver circuit and a tri-state buffer. The serial-parallel converter converts a serial switching control signal inputted from the third terminal into first parallel switching control signals when the first terminal is at a first power-supply potential. The selector selects either the first parallel switching control signals converted by the serial-parallel converter or second parallel switching control signals inputted into the second and third terminals, depending on the potential of the first terminal. The driver circuit converts potential levels of the first parallel switching control signals or the second parallel switching control signals selected by the selector and generates parallel switching control signals with potential levels capable of switching a switch circuit.

Abstract: An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. On each of the two or more strata, the clock distribution network includes a clock grid having a plurality of sectors for providing the global clock signals to various chip locations, a multiple-level buffered clock tree for driving the clock grid and including at least a root and a plurality of clock buffers, and one or more multiplexers for providing the global clock signals to at least a portion of the buffered clock tree. Inputs of at least some of the plurality of clock buffers on each of the two or more strata are shorted together using chip-to-chip interconnects to reduce skewing of the global clock signals with respect to the various chip locations.

Abstract: A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: A semiconductor device of the present invention is provided with a terminal for connecting a plurality of buses to the outside of the semiconductor device, a bus interface circuit for treating the plurality of buses as the same bus within the semiconductor device and a controller connected to the bus interface circuit.

Abstract: Provided is an electronic circuit system which facilitates skew timing adjustment while preventing increase of power consumption. An electronic circuit system includes: a track hold circuit module formed by a hierarchical tree structure of track hold circuits which can track-hold an analog value of an analog signal; and a control signal generation module which supplies an operation control signal to each of the track hold circuits in the hierarchical tree structure. In the hierarchical tree structure, the number of track hold circuits of each of the hierarchies is stepwise changed from the first hierarchy of the input side to which an analog signal is inputted, toward the final hierarchy of the final output side as the number of hierarchies is increased.

Abstract: According to one embodiment, a semiconductor switch includes a power supply, a driver, a switch section, and a first potential controller. The power supply includes a first potential generator and a second potential generator. The first potential generator is configured to generate a negative first potential. The second potential generator is configured to generate a positive second potential that a power supply potential is stepped down. The driver is supplied with the first potential and a third potential and configured to output at least one of the first potential and the third potential based on a terminal switching signal. The switch section is configured to connect a common terminal to any one of a plurality of radio frequency terminals according to an output of the driver. The first potential controller includes a divider and an amplifier.

Abstract: A method and an apparatus to drive an analog signal into a sensory tissue. The apparatus includes an analog-to-digital converter converting an original analog signal to a digital signal at an analog-to-digital converter sample rate. The apparatus includes a digital transceiver communicating wirelessly with the analog-to-digital converter to receive the digital signal. The apparatus includes a digital data buffer receiving the digital signal from the digital transceiver. The apparatus includes a digital-to-analog converter communicating with the digital data buffer and converting the digital signal into a reconstructed analog signal at a digital-to-analog converter sample rate faster than the analog-to-digital converter sample rate, the analog signal comprising a plurality of intensity values. The apparatus includes a pixel clock matching the digital-to-analog converter sample rate. The apparatus includes a bio-interface array comprising a plurality of electrodes and operably proximate to the sensory tissue.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: Embodiments of the present invention include a family of multi-way switches that can be configured to output an input signal to any combination of n output signal lines. Certain embodiments of the present invention employ a memristive junction between the input signal and each output signal line, the state of which is configured by one or more control signal lines. The memristive junction between the input signal line and each output signal can be switched between a stable, low-conductance state and a high-conductance state. A wide variety of different types of multi-way switches may be fabricated according to various embodiments of the present invention.

Abstract: A dynamic element matching method and system thereof is provided. The method includes grouping a plurality of switches into a plurality of groups; allocating a plurality of to-be-turned-on switches of the switches for an input signal to the groups; and maintaining a switch activity of each of the groups at a predetermined value. Accordingly, mismatch noise and harmonic noise are effectively reduced.

Abstract: Circuitry includes a voltage-controlled switch having a transmitter input, a receiver input, and an output that connects to one of the transmitter input and the receiver input. Passive components form a low-pass filter that is electrically connected to the transmitter input. The passive components are part of a multilayer ceramic passive module that includes a base body made of superimposed dielectric layers and electrically conductive layers. The voltage-controlled switch is on an upper portion or a lower portion of the base body.

Abstract: According to one embodiment, a semiconductor switch includes a voltage generator, a voltage controller, a driver, and a switch unit. The voltage generator generates a negative first potential. The voltage controller controls the first potential according to a terminal switch signal input from an outside. The driver is input the terminal switch signal, and outputs at least one selected from the first potential and the second potential based on the terminal switch signal. The second potential is a power supply voltage or is higher than the power supply voltage. The switch unit is provided on an SOT substrate, switches a connection between an anntena terminal and any one of high frequency terminals based on the output of the driver.

Abstract: A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.

Abstract: There has been a problem that the distortion characteristic of a switch circuit for a high frequency is deteriorated. A switch circuit in accordance with one aspect of the present invention includes a transistor connected in series between input and output terminals, a control terminal that receives a signal to control the conductive state of the transistor, a first resistor connected between the control electrode of the transistor and the control terminal, and a series circuit of a diode and a second resistor, the series circuit being connected in parallel with the first resistor between the control terminal and the control electrode of the transistor.

Abstract: A device includes a first circuit, a second circuit, and a control circuit controlling the first and the second circuits. The control circuit controls a plurality of output signals of the second circuit so as to have the same potential when the control circuit activates the first circuit and inactivates the second circuit.

Abstract: In a method of generating clock signals for a level-sensitive scan design latch, at least one test input signal is transmitted to a plurality of splitter leaves. Once the test input signal is stabilized at each of the splitter leaves, generating a shaped oscillator clock signal having a predetermined pattern of pulses from a central root is generated. At the plurality of splitter leaves, the test input signal is logically combined with the shaped oscillator clock signal, thereby generating a first latch clock signal and a second latch clock signal. The logically combining action includes applying a delay of less than one clock cycle to the shaped oscillator clock signal to generate a delayed oscillator clock signal; logically combining the delayed oscillator clock signal with a second signal so as to generate the first latch clock signal; and logically combining the shaped oscillator clock signal with a third signal so as to generate the second latch clock signal.

Abstract: An electronic apparatus includes a main output part to output an image signal, a sub output part to output the image signal to an external apparatus, a connecting sensor to sense whether the external apparatus is connected to the sub output part, and an image processor to output the image signal to the main output part when the external apparatus is not connected to the sub output part and to the sub output part when the external apparatus is connected to the sub output part, depending on a sensing result of the connecting sensor. Accordingly, the electronic apparatus is capable of automatically outputting the image signal to the external apparatus in the case in which the electronic apparatus is connected to the external apparatus.

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Abstract: A clock generating circuit includes a source clock, a first clock generated from the source clock through a first header, a second clock generated from the source clock through a second header and an inverter, wherein the second clock is out of phase with respect to the first clock, a first delayed falling edge clock, wherein the first delayed falling edge clock corresponds to the first clock with a first delayed falling edge, and a second delayed falling edge clock, wherein the second delayed falling edge clock corresponds to the second clock with a second delayed falling edge. The first delayed falling edge clock is generated from a first leading edge path and a first falling edge path, both originating from the source clock, that are inputted to a first delay chain.

Abstract: An output buffer including a first input stage circuit, a first output stage circuit, a second output stage circuit, a first switching module, and a second switching module is disclosed. The first output stage circuit is coupled to a first data line. The second output stage circuit is coupled to a second data line. The first switching module is coupled between the first input stage circuit and the first output stage circuit. The second switching module is coupled between the first input stage circuit and the second output stage circuit.

Abstract: A sequence circuit includes a switch circuit (30) and a control circuit (50). The switch circuit has an input terminal connected with a node (11) and an output terminal connected to a super I/O chip (10). The control circuit includes a first transistor (Q4) and a second transistor (Q5), the first transistor has a gate connected to the node and a drain connected to a sleep control signal terminal (S3?), the second transistor has a base connected to the drain of the first transistor and a collector connected to the super I/O chip. When the computer is off or in one of the sleep states, the node is at low level and the output terminal of the switch circuit outputs a low level signal; when the computer is on, the node is at high level and the output terminal outputs a high level signal.

Abstract: A semiconductor device of the present invention includes a plurality of switch cells having a switch transistor that controls conducting states of a global power supply line and a local power supply line according to a control signal, and a delay circuit that delays the control signal and transmits the control signal to the switch transistor connected to a subsequent stage, a chain unit that receives the control signal from outside, transmits the control signal by the delay circuit connected in series, and sequentially conducts the switch transistor, and a tree unit that is provided with the control signal via the switch cells disposed in a last stage of the chain unit, distributes the control signal to a plurality of groups by the delay circuit connected in parallel, and conducts the switch transistor in parallel by the distributed control signal.

Abstract: A cross point switch, in accordance with one embodiment of the present invention, includes a plurality of tri-state repeaters coupled to form a plurality of multiplexers. Each set of corresponding tri-state repeaters in the plurality of multiplexers share a front end module such that delay through the cross point switch due to input capacitance is reduced as compared to conventional cross point switches.

Abstract: A method and associated apparatus for enabling a plurality of functions of an integrated circuit to be controlled on a single pin of the circuit. The method includes the steps of providing each of the functions with a designated periodically recurring sampling instance during which time the status of a signal on the single pin will be considered to relate to the function designated to that sampling instance, and controlling each of the functions according to the status of the signal on the single pin during each of the plurality of functions' corresponding designated sampling instance.

Abstract: In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal.

Abstract: An interface circuit and an electronic device are used for expanding an output port of a micro processing unit. The interface circuit includes an input port electrically connected to the output port of the micro processing unit for receiving a control signals, and a plurality of output ports selectively driven to control external circuits by inputting different values of the control signal at the input port.

Abstract: A circuit for data alignment includes a first latch unit and a second latch unit. The first latch unit latches serial input data by using a plurality of first clocks with different phases and the same frequency to output latched data. The second latch unit latches the data from the first latch unit by using a plurality of second clocks with a lower frequency than the first clocks and more diverse phases to thereby output parallel data.