Abstract: An electrical circuit having improved linearity includes a resistive circuit having a plurality of field effect transistors (FETs) and one or more gate biasing circuits.

Abstract: A composite field effect transistor, in accordance with one embodiment, includes a zener diode, a junction field effect transistor and a metal-oxide-semiconductor field effect transistor. A gate of the junction field effect transistor is coupled to an anode of the zener diode. A cathode of the zener diode is coupled to a gate of the metal-oxide-semiconductor field effect transistor. A drain of the metal-oxide-semiconductor field effect transistor is coupled to a source of the junction field effect transistor.

Abstract: A bias circuit able to keep a bias current constant even if a threshold voltage of a transistor changes, provided with a resistance element connected between a bias voltage supply line and a gate and changing in resistance value linked with the threshold value of the transistor. Even if the threshold value of the transistor changes, the resistance value changes in response to the change of the threshold value. When the threshold voltage increases, the resistance value decreases and the bias voltage is adjusted by resistance division to increase. When the threshold voltage decreases, the resistance value increases and the bias voltage is adjusted by resistance division to decrease. The transistor is a junction type transistor having a first conductivity type channel and a second conductivity type gate. The resistance element is formed in the second conductivity type semiconductor region.

Abstract: A switching circuit uses multiple common-drain JFETs to serve as the low-side switches of the switching circuit, and each of the low-side JFET is coupled between a high-side switch and a power node. Since a JFET can endure high voltage at both drain side and source side, and has good heat dissipation capability at drain side, the drain of the low-side JFET is coupled to the power node to enhance the heat dissipation capability and accordingly, all the low-side JFETs are allowed to be packaged in a same package to reduce the PCB layout area.

Abstract: A high-frequency switch circuit arrangement. A plurality of stages (for example, two stages) of capacitative elements connected in series (C11 and C12, C21 and C22) are used in a shunt path of a high-frequency component. If a surge voltage is applied, the voltage that each capacitative element should bear decreases in inverse proportion to the number of the connection stages. Consequently, the surge resistance of the capacitative element is improved. The capacitative elements connected in series can be manufactured using the usual manufacturing process of compound semiconductor devices and if the structure of the invention is adopted, a protective diode need not be provided. As the capacity is made common and the device structure is designed, the high-frequency switch circuit arrangement can be further made compact, etc.

Abstract: To turn on a JFET, a two-stage turn-on current control is employed in a JFET driver circuit and a JFET driving method, by which a shortly pulsed high sourcing current is provided to turn on the JFET rapidly and efficiently, and a continuous low sourcing current is provided after the JFET turns on for reducing the power dissipation. After the JFET turns off, a negative charge pump is also employed to promise the JFET at a turn-off state. A special power sequence is further employed to ensure the JFET could be turned off during the power supply coupled to the JFET starts up.

Abstract: A control circuit for an inductive load driver includes a control block activated by a trigger signal and an output coupled to the control terminal of a power element. The control circuit includes an auxiliary current generator capable of delivering a current that is added to the current provided by control block and the sum of these currents is provided to the control terminal of the power element. The auxiliary current generator enables the inductive load driver to operate normally even though the trigger voltage is less than an optimal voltage value.

Abstract: The invention discloses a semiconductor switching circuit suitable for a Single Pole n Throw (SPnT) switching circuit having: a common terminal; first through third terminals, ground and control terminals, through FETS, shunt FETs, wherein when a first electric potential is supplied only to a Jth control terminal, and a second lower electric potential is supplied to the other control terminals, the common and Jth terminals are electrically connected and the first through third terminals are electrically disconnected.

Abstract: A circuit for driving a depletion-type JFET comprises a capacitor connected between the gate of the depletion-type JFET and a control signal, and a switch that is controlled by the control signal connected between the gate and source of the depletion-type JFET. The depletion-type JFET is turned on when the control signal is at a high voltage, and is turned off when the control signal is switched to a low voltage. The circuit and its driven depletion-type JFET can be integrated on a single chip to be a new power switch apparatus.

Abstract: A drive control circuit for a junction field-effect transistor having a gate terminal, a drain terminal and a source terminal as well as a gate leakage current and a maximally permissible gate current, includes a current supply which feeds the gate and produces a control current which is greater than the gate leakage current and smaller than the maximally permissible gate current for turning the junction field-effect transistor off.

Abstract: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the second terminals of the plurality of resistor elements. With this configuration, the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering. As a result, the power that can be handled can be increased. Furthermore, since the potentials at the intermediate connection points of the plurality of FETs connected in series can be prevented from lowering, the deterioration of the distortion characteristic and the isolation characteristic owing to the lowering of the potentials at the intermediate connection points of the plurality of field-effect transistors connected in series is prevented, and excellent high-frequency characteristics are obtained.

Abstract: The present invention relates generally to electrical cascade circuits using normally-off junction field effect transistors (JFETs) which have low on-resistance for low voltage and high current density applications. Proper configuration of the normally-off JFETs allows for low voltage drop, low-on resistance, high current density and high frequency operations. More particularly, these cascade circuits are configured to provide amplification of an input signal and signal switching capabilities. In general two or more normally-off JFETs are coupled together on a substrate to create a desired characteristic. For a three terminal gate-controlled cascade amplification circuit, an input signal at the first JFET can realize a signal gain of 80 dB to 120 dB at the second JFET. A four terminal gate-controlled cascade switching circuit, comprised of two JFETs, switches on or off to regulate current flow through the second JFET.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode.

Abstract: An integrated circuit includes an output buffer operable to drive an output node. The output buffer may comprise a MOSFET having a JFET integrated within a portion of a drain region of the MOSFET. The JFET may comprise a gate of second conductivity formed in semiconductor material of first conductivity type, which is contiguous with the drain region for the MOSFET. A voltage shaping circuit may control a bias of the JFET gate in accordance with the voltage levels of an output node and a predetermined output impedance.

Abstract: A matching circuit for coupling a conventional metal-oxide semiconductor field effect transistor (MOSFET) driver to the gate of a junction field effect transistor (JFET). A driver circuit optimized for driving a MOSFET is combined with a matching circuit to provide gate drive for a JFET. The matching circuit comprises a resistor and capacitor in parallel. For driving enhancement mode JFETs having a gate grid array structure and a pinch-off voltage greater than 0.4 volts, the range of resistor values is 10 to 200 ohms, and the range of capacitor values is 1 to 100 nF. For devices having a pinch-off voltage less than 0.4 volts, the range of resistor values is 100 to 2000 ohms. The matching circuit may further include a diode to provide a bias.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: A drive control circuit for a junction field-effect transistor having a gate terminal, a drain terminal and a source terminal as well as a gate leakage current and a maximally permissible gate current, includes a current supply which feeds the gate and produces a control current which is greater than the gate leakage current and smaller than the maximally permissible gate current for turning the junction field-effect transistor off.

Abstract: A voltage detection device (10, 30) utilizes grounded gate J-FET transistors (16,17,18) to detect desired input voltage values. The grounded gate J-FET transistors (16,17,18) function in different modes as the input voltage varies to facilitate detecting the desired input voltage values.

Abstract: A two terminal semiconductor circuit that can be used to replace the semiconductor diodes used as rectifiers in conventional DC power supply circuits. Three semiconductor circuits that can efficiently supply the DC currents required in both discrete and integrated circuits being operated at low DC supply voltages are disclosed. All three circuits have a forward or current conducting state and a reverse or non current conducting state similar to a conventional semiconductor diode. In a first configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is utilized as a two terminal device by connecting together the gate and source leads. The terminal voltage in the conducting state is considerably smaller than conventional semiconductor diodes. In a second configuration, an asymmetrical, enhancement mode, Junction Field Effect Transistor (JFET) is connected with a transformer such that the source and the drain serve as the two leads of a two terminal circuit.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.

Abstract: A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.

Abstract: A high-frequency-signal switching circuit includes a first high-frequency-signal path which includes first and second diodes connected in series with a high-frequency amplifier stage therebetween, and a second high-frequency-signal path formed of a third diode connected in parallel to the first high-frequency-signal path. A switching-voltage supply section switches the high-frequency amplifier stage and first and second diodes ON, and the third diode OFF, so that a high-frequency signal is transferred through the first high-frequency-signal path, or switches the high-frequency amplifier stage and first and second diodes OFF and the third diode ON, so that a high-frequency signal is transferred through the second high-frequency-signal path.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: The present invention is composed of: positive and negative control power sources P and N, first and second semiconductor device groups A and B in which a plurality of semiconductor devices 12 and 13 and also 15 and 16 are series-connected to these positive and negative control power sources P and N, switching signal source 17 that supplies ON/OFF control signals to semiconductor devices 12 and 13 and also 15 and 16 of these first and second semiconductor device groups A and B, and delay circuits 18 and 19 that delay for a specified time the ON/OFF control signals supplied to any one of semiconductor devices 12 and 13 and also 15 and 16 of first or second semiconductor device groups A and B from this switching signal source 17.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.

Abstract: The present invention relates to a bias circuit for biasing a depletion mode power transistor. The bias circuit includes a voltage offset circuit and a transistor, where the voltage offset circuit is serially coupled between the gate terminal of the depletion mode power transistor and the drain terminal of the transistor. The bias circuit generates a bias voltage that, when applied to the gate terminal of the depletion mode power transistor, maintains a substantially constant drain current through the power transistor over a range of threshold voltages caused by process and temperature variations.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: A high power MOS transistor consists of a large number of sub-transistors (T1 to T6) connected in parallel. The gate electrodes of the sub-transistors (T1 to T6) can be driven individually via controllable switching elements (SW1 to SW6; SQ1 to SQ5).

Abstract: A first FET is connected between first and third nodes, a second FET is connected between second and fourth nodes, a third FET is connected between third and fifth nodes and a fourth FET is connected between fourth and fifth nodes. A fifth FET is connected between first and sixth nodes and a sixth FET is connected between second and sixth nodes. The gates of the first, fourth and sixth FETs are connected to a first control terminal and the gates of the second, third and fifth FETs are connected to a second control terminal. A power-supply terminal is connected to the fifth and sixth nodes. The first and second nodes are connected to a common terminal through first and second capacitors, respectively. The fifth and sixth FETs form a pull-up switching circuit. The pull-up switching circuit pulls up the source of an FET in an OFF state to the power-supply voltage and isolates the source of an FET in an ON state from the power-supply voltage.

Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.

Abstract: A half-bridge circuit where the transistors comprising the half-bridge are electronically interlocked--precluding cross-conduction; and high-side voltage generation and logic level translation are integral to the interlock mechanism.

Abstract: The present invention relates to a circuit that pulls down the power supply line in an electronic system to a low state when the electronic system is turned off. More specifically, the present invention is an active circuit that establishes a low impedance between a power supply line and a return line when a system's power is turned off, and establishes a high impedance between a power supply line and a return line when the system is turned on.

Abstract: A low power consumption mixing circuit and process comprise first and second field effect transistors "FETs." The first and second FETs each have at least a control electrode and a drive electrode. The drive electrodes of the first and second FETs are coupled together by a capacitor. An AC signal is supplied to the control electrode of the first FET through a first matching circuit, and the first FET amplifies the AC signal. The capacitor removes the DC component from the amplified AC signal that appears at the drive electrode of the first FET. The amplified AC signal, which is free from the DC component, is provided to the drive electrode of the second FET. A second AC signal is supplied to the control electrode of the second FET by another matching circuit. The second FET mixes the first and second AC signals that are supplied to the drive electrode of the second FET. This mixed signal is then provided through an output matching circuit as a mixed output signal.

Abstract: A monolithic microwave semiconductor integrated circuit including a bias stabilizing circuit of a current mirror type formed of a bias control transistor formed of an enhancement mode compound semiconductor field effect transistor and a biased transistor formed of an enhancement mode compound semiconductor field effect transistor.

Abstract: A power supply circuit disclosed herein includes a three-terminal regulator for stabilizing a positive voltage applied thereto, a voltage converter for converting the stabilized voltage into a negative voltage, a power-supply section for stabilizing a voltage by a light-emitting diode, and a control circuit for applying a bias voltage across a drain and source of a GaAs FET amplifier only when a voltage is being applied across the gate and source of the amplifier. When power is introduced from a power supply, the presence of the negative voltage supplied from the voltage converter is sensed by the control circuit and a bias begins to be applied to the gate. Therefore, when it is sensed that a predetermined voltage is applied to the gate, a bias begins to be applied to the drain of the FET thereafter. When power from the power supply is cut off, a drop in voltage is sensed and the drain bias begins being cut off while the gate bias for the FET is cut off thereafter.

Abstract: In order to prevent a malfunction caused by an electrical noise and limit an excessive main current at a high speed while cutting off the same to a value close to zero, the main current is regulated by an IGBT (1) which is connected with a load. A part of this main current is shunted to another IGBT (2). The as-shunted current flows through a resistor (3), to be converted to a voltage across the resistor (3). When the main current is excessively increased by shorting of the load or the like, this voltage exceeds a prescribed value so that a transistor (5) and a thyristor (7) enter conducting states. Consequently, a voltage across a gate (G) and an emitter (E) of the IGBT (1) is so reduced as to cut off the main current. The transistor (5) prevents the main current from excessive increase since the same has a high speed of response, while the thyristor (7) cuts off the main current to zero since the same has lower resistance in conduction.