Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.

Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.

Abstract: A circuit for a phase connection of an inverter includes upper and lower bridge halves and respectively associated upper and lower bridge segments. Each bridge half has an outer switch and an inner switch connected in series. Each bridge segment has a diode and the inner switch of the associated bridge half connected in series. An output of the circuit is respectively connected to upper and lower potentials through the outer switches and is further connected to a center potential applied between the upper and lower potentials through each of the upper and lower bridge segments. Each bridge half further has a parallel power switch. The parallel switch of each bridge half is connected in parallel to the series-connected outer and inner switches of the bridge half. The output of the circuit is further respectively connected to the upper and lower potentials through the parallel switches.

Abstract: A driving module for driving a Digital Visual Interface includes an integrated chip, a pull-up resistor unit, and a voltage converter. The pull-up resistor unit includes a plurality of resistors. The voltage converter includes an array of resistors comprising a plurality of resistors and a MOSFET. Each resistor of the array of resistors includes a first end and a second end. The first ends are electrically connected to outputs of the integrated chip, and the second ends are electrically connected to a drain of the MOSFET. A source of the MOSFET is connected to ground, and a gate of the MOSFET is electrically connected to an output of the main board.

Abstract: A solid-state relay is provided, which includes a first transistor, a second transistor, a first transmission circuit, and a second transmission circuit. A gate of the first transistor is connected to one of a source and a drain of the second transistor, one of a source and a drain of the first transistor is connected to a first terminal, and the other of the source and the drain of the first transistor is connected to a second terminal. The first transmission circuit supplies a first signal to the gate of the first transistor. The second transmission circuit supplies a second signal to a gate of the second transistor. The first terminal is connected to the second terminal when the first transistor is turned on by the first signal.

Abstract: A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.

Abstract: An electronic circuit includes a reverse-conducting IGBT and a driver circuit. A first diode emitter efficiency of the reverse-conducting IGBT at a first off-state gate voltage differs from a second diode emitter efficiency at a second off-state gate voltage. A driver terminal of the driver circuit is electrically coupled to a gate terminal of the reverse-conducting IGBT. In a first state the driver circuit supplies an on-state gate voltage at the driver terminal. In a second state the driver circuit supplies the first off-state gate voltage, and in a third state the driver circuit supplies the second off-state gate voltage at the driver terminal. The reverse-conducting IGBT may be operated in different modes such that, for example, overall losses may be reduced.

Abstract: An isolation structure of a high-voltage driving circuit includes a P-type substrate and a P-type epitaxial layer; a high voltage area, a low voltage area and a high and low voltage junction terminal area are arranged on the P-type epitaxial layer; a first P-type junction isolation area is arranged between the high and low voltage junction terminal area and the low voltage area, and a high-voltage insulated gate field effect tube is arranged between the high voltage area and the low voltage area; two sides of the high-voltage insulated gate field effect tube and an isolation structure between the high-voltage insulated gate field effect tube and a high side area are formed as a second P-type junction isolation area.

Abstract: A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET.

Abstract: Embodiments provide a switching device including a field-effect transistor (FET) having a source terminal, a drain terminal, a gate terminal, and a body terminal. The FET may be switchable between an on state, in which the FET passes a transmission signal between the source terminal and the drain terminal, and an off state, in which the FET prevents a transmission signal from passing between the source terminal and the drain terminal. The FET may receive a control signal at the gate terminal to switch the FET between the on state and the off state. The switching device may further include one or more forward diodes coupled between the gate terminal and the body terminal to bias the body terminal during the on state, and one or more reverse diodes coupled between the gate terminal and the body terminal to bias the body terminal during the off state.

Abstract: Radio-frequency (RF) switch circuits are disclosed having adjustable resistance to provide improved switching performance. RF switch circuits include at least one field-effect transistor (FET) disposed between first and second nodes, each of the FET having a respective gate and body. An adjustable-resistance circuit is connected to either or both of the respective gate and body of the FET(s).

Abstract: The present invention discloses a semiconductor switch comprising a switching unit. Said switching unit includes: a transistor having a drain, a gate and a source; a drain bias resistor coupled to the drain; a drain bias selecting circuit to couple the drain bias resistor with a first or a second drain bias according to the transistor's state; a gate bias resistor coupled to the gate; a gate bias selecting circuit to couple the gate bias resistor with a first or a second gate bias according to the transistor's state; a source bias resistor coupled to the source; and a source bias selecting circuit to couple the source bias resistor with a first or a second source bias according to the transistor's state, wherein the first and second drain biases are different, the first and second gate biases are different, and the first and second source biases are different.

Abstract: Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a buffer circuit that outputs a drive signal generated according to a comparison result of an input signal and an output signal through a first node, drives a second node in response to the drive signal, and divides a voltage level of the second node to generate the output signal through a third node. The second semiconductor device includes a stabilization circuit that is connected to the third node through a connector to stabilize the output signal.

Abstract: A circuit arrangement including a first transistor, a second transistor and a third transistor. The first transistor and the second transistor are configured so that the current flowing through the first transistor is proportional to the current flowing through the second transistor and the third transistor. The first transistor, the second transistor and the third transistor are configured to operate in an ohmic mode. The second transistor and the third transistor are coupled in series to each other. The first transistor, the second transistor and the third transistor match each other in at least one characteristic.

Abstract: A radio frequency (RF) switch which comprises an RF domain section having a plurality of RF switching elements. A DC domain section is provided having circuitry configured for controlling the RF switching elements in response to one or more control signals. A resistive load is provided between the RF domain section and the DC domain section. A bypass circuit is configured for selectively bypassing at least a portion of the resistive load.

Abstract: An antifuse according to an embodiment of the invention herein can include a depletion mode metal oxide semiconductor field effect transistor (“MOSFET”) having a conduction channel and a metal gate overlying the conduction channel. A cathode and an anode of the antifuse can be electrically coupled to the gate, such that the antifuse is programmable by driving a programming current between the cathode and the anode to cause material of the metal gate to migrate away. Under appropriate biasing conditions, when the antifuse is unprogrammed, the conduction channel is turned on unless a voltage above a first threshold voltage is applied to the gate to turn off the conduction channel. The gate can be configured such that when the antifuse has been programmed, the conduction channel remains turned on even if a voltage above the first threshold voltage is applied between the gate and a source region of the MOSFET.

Abstract: A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

Abstract: Apparatus, systems, and methods are provided for protecting a switching device using a gate driver device. An exemplary gate driver system includes an interface for coupling to a switching device, a desaturation detection arrangement coupled to the interface to detect a desaturation condition based on an electrical characteristic at the interface, and a deactivation arrangement coupled to the interface to deactivate the switching device in a manner that is influenced by the electrical characteristic at the interface. In one embodiment, the switching device is deactivated by providing a deactivation current to a control terminal of the switching device and adjusting the deactivation current based on an electrical characteristic at the interface.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Abstract: A protective device for a voltage-controlled semiconductor switch has a gate connection, a power emitter connection, an auxiliary emitter connection and a collector connection. The semiconductor switch can switch a current between the collector connection and the power emitter connection. A voltage-limiting device limits the voltage between the gate connection and the power emitter connection. A deactivation device is connected to the voltage-limiting device and deactivates the voltage-limiting device during a switch-on of the semiconductor switch.

Abstract: Power switches operate with reduced power consumption. A circuit controls a power switch via its gate having a gate capacitor. The circuit comprises an on-control switch coupling the gate of the power switch with a charge supply to provide a gate charge to the gate capacitor of the power switch, thereby putting the power switch to the on-state; a transformer and an off-control switch coupling the gate of the power switch with ground via a primary winding of the transformer to discharge the gate capacitor of the power switch, thereby causing a discharge current through the primary winding and thereby putting the power switch to the off-state; wherein a secondary winding is coupled to the charge supply, such that a current, which is induced in the secondary winding, recharges the charge supply.

Abstract: An integrated circuit 2 includes a transistor 26 Which has a normal switching speed arising during normal operations of that transistor that apply electrical signals within normal ranges. If it is desired to change the speed of operation of the transistor, then speed tuning circuitry 12 applies a tuning electrical signal with a tuning characteristic outside of the normal range of characteristics to the transistor concerned. The tuning electrical signal induces a change in at least one of the physical properties of that transistor such that when it resumes its modified normal operations the switching speed of that transistor will have changed. The tuning electrical signal may be a voltage (or current) outside of the normal range of voltages applied to the gate of a transistor so as to induce a permanent increase in the threshold of that transistor and so slow its speed of switching. Temperature of a transistor may also be controlled to induce a permanent change in performance/speed.

Abstract: According to one embodiment, a semiconductor device includes: a first switching element; a first interconnection; a first resistor; and a second interconnection. The first switching element includes a first control terminal, a first electrode terminal, and a first conductor terminal. The second switching element includes a second control terminal, a second electrode terminal, and a second conductor terminal. The first interconnection includes a first through a fourth interterminal interconnections. The first resistor is connected at a first end to the first control terminal. The second resistor is connected at a first end to the second control terminal and is connected at a second end to a second end of the first resistor. The second interconnection is provided between the first electrode terminal and the second electrode terminal and/or between the first control terminal and the second control terminal.

Abstract: A method for rendering a half-bridge circuit containing normally on switches such as junction field effect transistors (JFETs) inherently safe from uncontrolled current flow is described. The switches can be made from silicon carbide or from silicon. The methods described herein allow for the use of better performing normally on switches in place of normally off switches in integrated power modules thereby improving the efficiency, size, weight, and cost of the integrated power modules. As described herein, a power supply can be added to the gate driver circuitry. The power supply can be self starting and self oscillating while being capable of deriving all of its source energy from the terminals supplying electrical potential to the normally on switch through the gate driver. The terminal characteristics of the normally on switch can then be coordinated to the input-to-output characteristics of the power supply.

Abstract: According to an embodiment, an FET drive circuit includes an FET, a first circuit, a resistor and a third rectifying device. The first circuit includes a first rectifying device, a second rectifying device and a capacitive element sequentially provided in series from a drain to a gate of the FET, the first rectifying device allowing a forward electric current flowing from the drain to the gate, and the second rectifying device having a predetermined breakdown voltage with respect to the electric current from the drain to the gate. The resistor is provided between a power source and a connecting point of the second rectifying device and the capacitive element; and the third rectifying device provided between a source and a gate of the FET.

Abstract: An electronic component includes a switching device comprising a source, a gate, and a drain, the switching device having a predetermined device switching rate. The electronic component further includes a gate driver electrically connected to the gate and coupled between the source and the gate of the switching device, the gate driver configured to switch a gate voltage of the switching device at a gate driver switching rate. The gate driver is configured such that in operation, an output current of the gate driver cannot exceed a first current level, wherein the first current level is sufficiently small to provide a switching rate of the switching device in operation to be less than the predetermined device switching rate.

Abstract: An RF switch includes a transistor and a compensation capacitor circuit. The compensation capacitor circuit includes a first compensation capacitor and a second compensation capacitor of the same capacitance. The compensation capacitor circuit is used to improve voltage distribution between a control node and a first node of the transistor and between the control node and a second node of the transistor.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the FET at a position electrically between a gate terminal of the FET and a body terminal of the FET.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.

Abstract: Universal Serial Bus (USB) protection circuits are provided. A circuit includes a plurality of first transistors connected in series between a pad and ground. The circuit also includes a plurality of second transistors connected in series between the pad and a supply voltage. The circuit further includes a control circuit that applies respective bias voltages to each one of the plurality of first transistors and to each one of the plurality of second transistors. The bias voltages are configured to: turn off the plurality of first transistors and turn off the plurality of second transistors when a pad voltage of the pad is within a nominal voltage range; sequentially turn on the plurality of first transistors when the pad voltage increases above the nominal voltage range; and sequentially turn on the plurality of second transistors when the pad voltage decreases below the nominal voltage range.

Abstract: A transistor includes a substrate, an electrically conductive material layer, and an electrically insulating material layer. At least a portion of one or more of the substrate, the electrically conductive material layer, and the electrically insulating material layer define a reentrant profile.

Abstract: An apparatus includes: a switch having a first transistor, the first transistor having a gate, wherein the switch is connected between a first pad and a second pad; and a first biasing circuit coupled to the gate of the first transistor, wherein the first biasing circuit is configured for outputting a first voltage, the first voltage being the lowest one of (1) a voltage of the first pad, (2) a voltage of the second pad, and (3) a ground voltage; wherein the gate of the first transistor is driven by the first voltage from the first biasing circuit in response to an enable signal being set for configuring the switch to be off.

Abstract: An improved field effect transistor (FET) is provided by segmenting the gates of a power FET wherein a controller can “decide” how much of the FET to use, thus increasing efficiency.

Abstract: In an integrated circuit having input circuitry whose positive and/or negative input signals are gated by one or more clocked input switches, the switch clock signal CLK_SW used to clock the input switch(es) is automatically generated based on the higher of the IC's power supply voltage VDD and the positive input signal voltage Vplus. In one embodiment, a clock level shifter shifts an input clock signal CLK_VDD from the VDD voltage domain to generate a level-shifted clock signal CLK_VPLUS in the Vplus voltage domain. Based on a control signal VSEL, a clock selector selects either the input clock signal or the level-shifted clock signal to be the switch clock signal. An over-voltage detector generates both the logic state and the voltage domain of the control signal based on the higher of VDD and Vplus, such that the input switches are appropriately clocked even during over-voltage conditions in which Vplus>VDD.

Abstract: There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices and at least one first diode device individually connected to control terminals of the plurality of first switching devices to enable or block signal flow between a common port transmitting and receiving a first high frequency signal and a first port inputting and outputting the first high frequency signal; and a second signal transferring unit including a plurality of second switching devices and at least one second diode device individually connected to control terminals of the plurality of second switching devices to enable or block signal flow between the common port transmitting and receiving a second high frequency signal and a second port inputting and outputting the second high frequency signal.

Abstract: Two semiconductor switches are arranged in parallel in a load circuit for connecting a power source with a load. Further, the semiconductor switches are controlled so as to be alternately tuned on and off. As a result, since a current flows through only either of the semiconductor switches, an offset error detected by current sensors includes only an offset error of either of the semiconductor switches, the detection of current with high accuracy can be accomplished. Therefore, when performing the control of shutting off the circuit to cope with the occurrence of an overcurrent flowing through the load, the shutoff control with high accuracy can be accomplished.

Abstract: A circuit is provided and includes current sources, switches, a control module, and capacitances. The current sources adjust current flowing through a load. Each of the switches activates a respective one of the current sources. Kick-back voltages are generated at inputs of the current sources in response to the current sources being turned ON. A control module generates control signals to change states of the switches to alternate a direction in which the current flows through the load. A first capacitance is connected between a first pair of the current sources and a second pair of the current sources. A second capacitance is connected between the first pair of the current sources and a reference terminal. A third capacitance connected between the second pair of the current sources and the reference terminal. The first capacitance, the second capacitance, and the third capacitance reduce magnitudes of the kick-back voltages.

Abstract: In one embodiment, a level-shifter for driving a high-side power switch with sub-nanosecond timing integrity, without requiring a high-side gate-drive power supply, is provided. A drive source is connected to the gate of a power switch through a common-mode choke, and the latter level-shifts the common-mode voltage of the drive signal to the common-mode level of the power switch. The same level-shifter may also be used to drive a low-side power switch to avoid ground bounce.

Abstract: There is provided a semiconductor device capable of preventing the passage of current that is unexpected in a circuit operation even in the case of reverse connection, thus ensuring higher safety. The semiconductor device has a switch circuit which includes: a first transistor; a second transistor having a drain thereof connected to a drain of the first transistor, a source and a back gate thereof connected to a back gate of the first transistor, and a gate thereof connected to a source of the first transistor; and a third transistor having a drain thereof connected to the source of the first transistor, a source and a back gate thereof connected to the back gate of the first transistor, and a gate thereof connected to the drain of the first transistor.

Abstract: A low voltage isolation circuit is coupled between an input terminal for receiving a high voltage signal and an output terminal for transmitting the high voltage signal to a load. The isolation circuit includes a driving block; having a first driving transistor coupled between a first voltage reference and an intermediate node and a second driving transistor coupled between the intermediate node and a second voltage reference; an isolation block connected between the input and output terminals and, through a protection block to the intermediate node. The protection block includes first and second protection transistors (MD1, coupled in anti-series to each other and having control terminals receiving complementary protection driving signals. The isolation block includes a voltage limiter block, a diode block and a control transistor connected across the diode block between the input and output terminals and having a control terminal connected to the intermediate node through the protection block.

Abstract: A power device includes a switching device having a control terminal and an output terminal; and a driving circuit configured to provide a driving voltage to the control terminal such that a voltage between the control terminal and the output terminal remains less than or equal to a critical voltage. A rise time required for the driving voltage to reach a target level is determined according to current-voltage characteristics of the switching device. And, when the voltage between the control terminal and the output terminal exceeds the critical voltage, leakage current is generated between the control terminal and the output terminal.

Abstract: A comparator unit includes: a comparison section configured to compare a control pulse with an electric potential based on a signal voltage; and a control section configured to control, based on the control pulse, operation and non-operation of the comparison section.

Abstract: A basic and simple power control circuit for selectively controlling power to an electronic device is provided. The electronic device includes a power module, a system power port, and a processing unit, the processing unit includes a first and a second power control pins. The power control circuit includes a power switch, a trigger signal producing sub-circuit, a trigger-receiving sub-circuit, and a switch controlling sub-circuit. The switch is connected between the power module and the system power port. The trigger signal producing sub-circuit produces a trigger signal. When receiving a trigger signal, the trigger-receiving sub-circuit follows a first control signal output by the second power control pin to output the first control signal. The switch controlling sub-circuit turns off the power switch when receiving the first control signal.

Abstract: An analog interface processing circuit includes a first and second signal processing interface, a processing system connected to the first and second signal processing interfaces, a biasing voltage source switchably coupled to said first signal processing interface via a first switch assembly and switchably coupled to said second signal processing interface via a second switch assembly, and a first control output of said processing system controllably coupled to said first switch assembly and a second control output of said processing system controllably couple to said second switch assembly.

Abstract: A multi-path power switch scheme for functional block wakeup is disclosed. The scheme may be applied to functional blocks of an integrated circuit. When a power on procedure is initiated within a given functional block, a first group of power switches in a functional block may be powered on, while a second group of power switches is inhibited from powering on. After a predetermined time has elapsed, activation of the second group of power switches is initiated. After initiation of a power up procedure for a given functional block, the powering up of a second functional block to be powered on may initially be inhibited. After a predetermined time has elapsed, the powering on of the second functional block may be initiated. Overlap between times when the first and second groups of switches are active may depend on process, voltage, and temperature variations.

Abstract: A readout device is adapted for dual-band sensing, and includes an amplifier, two direct injection (DI) readout circuits to be respectively connected to two sensors, and a switching module. Through operation of the switching module, one of the DI readout circuits can be electrically connected to the amplifier, and cooperate with the other DI readout circuit to achieve a dual-band sensing feature.

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.