Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A switching capacitor generation circuit which reduces the on-resistance and parasitic capacitance of a switch element and improves the operation properties of the switch element. The switching capacitor generation circuit, which has first and second output terminals, includes a first capacitor coupled to the first output terminal, a second capacitor coupled to the second output terminal, and a single switch element coupled between the first and the second capacitors.

Abstract: A high-voltage tolerant pass-gate assembly (18) for controlling an electrical signal between a first pad (12) and a second pad (14) includes a pass-gate (24) and a first native device (26). In certain embodiments, the first native device (26) is positioned between the first pad (12) and the pass-gate (24). The first native device (26) is permanently enabled. In another embodiment, the pass-gate assembly (18) includes a second native device (28) positioned between the pass-gate (24) and the second pad (14). The second native device (28) can also be permanently enabled. Neither the first native device (26) nor the second native device (28) controls an on-off state of the pass-gate (24). The first native device (26) can have a first voltage and the pass-gate (24) can have a supply voltage that is substantially similar to the first voltage.

Abstract: A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.

Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: A disclosed embodiment is a switching circuit including a number of transistors fabricated in a device layer situated over a buried oxide layer and a bulk semiconductor layer. Each transistor has a source/drain junction that does not contact the buried oxide layer, thus forming a source/drain junction capacitance. The disclosed switching circuit also includes at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thus electrically isolating at least one of the transistors in the switching circuit so as to reduce voltage and current fluctuations in the device layer. The disclosed switching circuit may be coupled to a power amplifier or a low noise amplifier and an antenna in a wireless communications device, and be controlled by a switch control signal in the wireless communications device.

Abstract: A buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an input/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: The method of the present invention for switching an output driver of the type comprising an n-mos transistor and a p-mos transistor configured in a push-pull arrangement operates by directly monitoring the level of the output signal OUT. The method comprises slowly switching off the input to the initially designated active transistor; monitoring the variation in output voltage level in response thereto; and when a desired change in output level is detected the switching the initially designated output transistor on completely and fast. Using this method the parasitic currents in the diodes are much smaller in time and amplitude.

Abstract: The application provides a switching circuit for switchably connecting an input node and an output node. The switching circuit comprises a switch operable to switchably connect the input node to the output node in response to a switching signal. A sensor is provided for sensing the voltage between the input and output nodes and providing a sense signal in response thereto. A driver coupled to the sensor adjusts the switching signal in response to the sense signal.

Abstract: An electronic circuit has an output driver (DRV) for providing a driving signal (U0). The output driver has a transistor (T) with a first main terminal, a second main terminal and a control terminal coupled to receive a control signal (Vcntrl), a power supply terminal (VSS), an output terminal (OUT) for providing the driving signal (U0) that is coupled to the second main terminal, and a sensing resistor (Rm) coupled between the power supply terminal (VSS) and the first main terminal. The output driver (DRV) further has means for temporarily disabling the coupling between the control terminal and the control signal (Vcntrl) during a peak voltage across the sensing resistor (Rm). The means may have a circuit that has a unidirectional current behavior, such as a diode (D), in series with the control terminal of the transistor (T).

Abstract: The present invention discloses a voltage adjusting circuit including a first switch element, a second switch element, a third switch element, a fourth switch element, a fifth switch element, and a sixth switch element. At first, the voltage adjusting circuit performs a discharging operation on an output voltage toward a reference voltage source, and then when the output voltage level is approaching a voltage level of an input voltage source, the voltage adjusting circuit will perform the discharging operation on the output voltage toward the input voltage source instead, and thus the voltage adjusting circuit can avoid affecting the input voltage source when performing the discharging operation. In addition, the voltage adjusting circuit does not need a digital counter to perform the above dual-phase type discharging operation or multi-phase type discharging operation, and therefore cost of the voltage adjusting circuit is lower, and the voltage adjusting circuit has good accuracy.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A higher voltage switching circuit based on a standard process limits the lowest applied voltage to an intermediate voltage between the higher voltage and ground, instead of ground. In this way, the maximum electric field across the gate dielectric is greatly reduced. In additional the use of p-type triple well also reduces junction breakdown in some embodiments. This concept is also valid in the case where the high voltage is negative, in which case the intermediate voltage is also negative.

Abstract: A transmission gate switch includes a switching unit to conduct a switching operation between first and second nodes in response to a switching signal, and an isolation unit to prevent the switching unit from being turned on by a negative swing of the first or second node while the switching unit is being turned off.

Abstract: Circuit arrangement having a power transistor and a drive circuit for the power transistor The invention relates to a circuit arrangement having the following features: a power transistor (T) having a control terminal (G) and also a first and second load path terminal (D, S), the first load path terminal (D) of which is connected to a terminal for supply potential (V1) via an inductance-exhibiting line terminal (1) and the second load path terminal (S) of which serves for connecting a load (Z), and a first drive unit (10) for off-state driving of the power transistor (T) having an output (11) connected to the control terminal (G) of the power transistor (T1), and having a first current source arrangement (Iq1) connected between the output (AK) and a first drive potential (GND), in which case the first drive unit has a second current source arrangement (S2off, Iq2; S2off, Iq2, Iq21), which is connected to the output (AK) and which provides a current (I2; I2, I21) that is dependent on a temporal change in a

Abstract: A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semiconductor substrate and the gate electrode and having a plurality of contact holes formed therein, and contact plugs formed within the contact holes. The contact plugs can include a first contact plug and a second contact plug electrically connected to the gate electrode, and a third contact plug and a fourth contact plug electrically connected to the source/drain regions.

Abstract: An RF envelope detection circuit that operations at low currents, high sensitivity, and high dynamic range. The circuit receives an AC signal at its input terminal and applies a signal on its output terminal that is a function of the envelope magnitude of the AC signal. To do so, a current source provides a current with an AC signal being superimposed thereon. A rectification circuit rectifies the AC component of this current. A voltage amplifier then amplifies the voltage for providing on the output terminal of the detection circuit. A current sink draws a current from the output terminal that has approximately the same magnitude as the current provided by the current source. A capacitor is coupled to the output terminal of the rectifier so as to store excess charge provided by the rectifier that is in excess of the magnitude of the current provided by the current source.

Abstract: An integrated high side switch with multi-fault protection. When a fault condition is detected, the switch is turned off. The switch includes a pair of transistors that are connected such that the source of the first transistor is connected with the source of the second transistor. The drain of the first transistor is thus connected to the supply voltage. A first current mirror generates a current sense output. A second current mirror generates an internal current to detect an over current fault condition. The transistors in the current mirrors are connected like the switch transistors. A high voltage operational amplifier and a transistor are used as feedback to insure that the voltage at the output of the current mirrors matches the voltage at the output of the switch. This ensures that the current mirrors generate scaled versions of the current flowing through the switch.

Abstract: A bus switch circuit includes a switch element having two terminals whose electrical connection is controlled when a control signal is input into a control terminal. The bus switch circuit further includes a first pull-up resistor and first switch circuit, a second pull-up resistor and second switch circuit. The control signal controls the electrical connections of the first and second switch circuits.

Abstract: A control device for controlling a load drive semiconductor element for driving a load has a test operation mode for measuring a leak current of the load drive semiconductor element. In the test operation mode, a control terminal of the load drive semiconductor element is electrically separated from a power source or a ground by turning off another semiconductor element. Therefore, no electric current flows from the power source to the control terminal or from the control terminal to the ground. Therefore, the leak current of the load drive semiconductor element can be easily measured, even after the load drive semiconductor element is electrically connected to the control device for fabricating one-packaged IC.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: Circuitry and methodology for controlling a FET or another transistor device provided to supply power to a circuit board insertable into a live backplane to provide inrush current slew rate control. The FET control circuit is responsive to an input signal variable in a preset manner to produce a FET control signal for controlling the FET so as to form an output signal corresponding to the input signal. The control circuit is configured to prevent the uncontrollable step in the output from being produced when the FET control signal reaches a level sufficient to control the FET. In one embodiment, a comparator is provided for comparing the FET control signal with a reference value that may correspond to a current for charging a control terminal of the FET to prevent the input signal from changing until the FET control signal exceeds the reference value.

Abstract: A source follower in which any one of the following three modes is selected by a plurality of switching elements: a first mode in which a first potential is supplied to a gate of a transistor and an input potential is supplied to a first electrode of a capacitor respectively and a second electrode of the capacitor and a source of the transistor are connected, a second mode in which an input potential is supplied to the first electrode and the gate of the transistor and the second electrode floats, and a third mode in which the first electrode and the gate of the transistor are connected and a potential thereof floats and a second potential is supplied to the second electrode, a drain of the transistor is supplied with a third potential, and a potential of the source of the transistor is supplied to a subsequent circuit.

Abstract: A simple, low cost, gate driver and bias circuit provides for a wider operating voltage range exceeding the normal component breakdown voltage of components such as NMOS and PMOS transistors. A CMOS process with an epitaxial layer as bulk and p-type substrate is used to implement the circuit in this example.

Abstract: A semiconductor device has first, second, and third connecting leads (1, 2, 3), whose respective base points (1f, 2f, 3f) have centroids (1m, 2m, 3m). The connecting leads are arranged wherein an angle (?) between a first line drawn between the centroids (1m, 3m) of the base points (1f, 3f) of first lead (1) and third lead (3) and a second line drawn between the centroids (2m, 3m) of the base points (2f, 3f) of second lead (2) and third lead (3) is 20° maximum. In addition, a semiconductor module may incorporate two or more semiconductor devices which are connected electrically in parallel.

Abstract: The present invention provides a semiconductor device that can adjust signal frequency bandwidths and consumption currents to be appropriately increased or reduced in source-follower amplifiers in all stages. The semiconductor device is comprised of a source-follower amplifier including a driver transistor D1, and a load transistor L1 that is connected to the driver transistor D1 and driven variably depending on a signal inputted to the driver transistor, wherein a gate of the load transistor L1 is applied with a variable bias voltage. The semiconductor device 1 is further comprised of a source-follower amplifier including a driver transistor D2, and a load circuit (load transistor L2) that is connected to said second driver transistor and driven variably depending on a signal outputted from the second driver transistor D2, wherein a gate of the load transistor L2 is applied with a variable bias voltage to vary a resistance value of the load transistor L2.

Abstract: The buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an put/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: A level shift circuit with high switching speed and low power dissipation is described. The circuit includes two short channel transistors, two long channel transistors, and two switching transistors. Short channel transistors are arranged to receive a high input voltage presenting relatively low impedance and low capacitance. Long channel transistors are arranged to receive a first voltage from the short channel transistors and provide an output voltage and an inverted output voltage, which are also employed to control the short channel transistors. A first switching transistor of the switching circuit enables the short channel and the long channel circuits to provide the output voltage based on a low input voltage and a logic input voltage. A second switching transistor enables the same circuits to provide the inverted output voltage based on the logic input voltage.

Abstract: Apparatus for detecting failure of an isolation device includes a current sensor to sense current through the isolation device and a circuit responsive to the current sensor output signal and to an enable signal that controls the isolation device for providing an Early Failure Warning (EFW) signal indicative of whether the isolation device has failed. The enable signal is at a first logic level when the isolation device is on and is brought to a second logic level to disable and test the isolation device. Also described is a method of detecting a failure of an isolation device including disabling the isolation device, sensing a current through the isolation device, and providing an EFW signal indicating that the isolation device has failed if the current through the isolation device is greater than a predetermined level when the isolation device is disabled.

Abstract: The drain of a power transistor M1 is connected to the non-inverting input terminal of an operational amplifier A and the drain of a transistor M2 is connected to the inverting input terminal of the operational amplifier A to make substantially equal the drain voltages of the power transistor M1 and the transistor M2, of which the gates are connected together and of which the sources are connected together. The drain current of the transistor M2 is outputted via a detection terminal 13 as a current signal proportional to the drain current of the power transistor M1.

Abstract: Certain exemplary embodiments comprise a system, comprising: an electrical isolator adapted to couple a processor of a programmable logic controller to a user load; a transistor adapted to provide switching of a control signal provided by the processor for the user load; a totem pole output coupling the electrical isolator and the transistor and adapted to switch a gate of the transistor; and a power supply adapted to provide a floating regulated DC voltage to the gate of the transistor.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: In a high tolerance I/O interface with over-voltage protection beyond 5 V, a cascoded driver with PMOS pull-up and NMOS pull-down transistors, connected to a pad, is provided. Circuitry is included to maintain the floating well voltages of the PMOS pull-up driver transistors at substantially the same voltages as their respective drains, and their gate voltages at substantially the same voltages as their respective drains, under back-drive and 5 V tolerant mode. Circuitry is also provided to increase the gate voltage of one of a cascoded pair of NMOS pull-down driver transistors, so that the drain-source junction voltage and gate oxide voltage of the transistor will be less than the breakdown voltage under back-drive and 5 V tolerant mode.

Abstract: A gradation selector circuit provided with a resistor string circuit in which resistive elements are connected in series between a high potential power source and a low potential power source and a selector circuit which is connected to the resistor string circuit, which selects one of plural analog voltages generated in the resistor string circuit according to a control signal and which outputs it to an output terminal is used. The selector circuit includes analog switching circuits that select analog voltage close to intermediate potential. The analog switching circuit includes a P-type MOS transistor to the source electrode and the back gate electrode of which the resistor string circuit is connected and a depletion type N-type MOS transistor to the source electrode of which the drain electrode of the P-type MOS transistor is connected and to the drain electrode of which an output terminal is connected.

Abstract: Provided is directed to a delay locked loop control circuit capable of reducing a test time and preventing a yield from being reduced, by preventing a failure due to a charge sharing and a failure in a specific frequency and voltage due to a noise of a feedback clock, by means of including: a level setting unit for setting an initial level of a locked state signal, which is decided whether or not phases of a reference clock and a feedback clock are aligned; a signal generation unit for generating a third control signal according to a first control signal comparing phases of the reference clock and the feedback clock, and a second control signal checking out phases of the reference clock and the feedback clock in every predetermined time; a level maintaining unit for maintaining a level of the locked state signal according to the locked state signal and a fourth control signal comparing a signal delaying the feedback clock for a predetermined time with the reference clock; a detection unit for varying a level

Abstract: A first control potential setting means (1) generates a first control potential (N2) which reverses the magnitude relationship with a second control potential (N3) when an input signal (IN) reaches the vicinity of a logical threshold value. A second control potential setting means (2) generates the second control potential (N3) which changes in the same direction as the input signal (IN), in accordance with a change in input signal (IN). An output means (3) includes transistors (Q5, Q6), and generates an output signal (OUT) having a predetermined potential on the basis of the first control potential (N2), the second control potential (N3), and a reset signal (RSET). A reset means (4) turns off the transistor (Q6) while a waveform shaping circuit is in operation.

Abstract: A mixer circuit arrangement 30 comprises a complementary transconductor circuit 31 and a mixer stage 32. The complementary transconductor circuit 31 includes two paths in parallel between a positive supply voltage VDD and ground G and is connected directly between the voltage supply terminals VDD and G. The first path includes a P-type MOS transistor TP1 and an N-type MOS transistor TN1 connected in series. Similarly, the second path includes a P-type MOS transistor TP2 and an N-type MOS transistor TN2 connected in series. The gate electrodes of the P-type transistors TP1 and TP2 are connected to a voltage bias Vbp via high value bias resistors Rb, and the gate electrodes of the N-type transistors TN1 and TN2 are connected to a second voltage bias Vbn via high value bias resistors Rb. The mixer stage 32 is connected between the output of the complementary transconductor circuit 31 and a load, the load also being connected to one of the supply terminals.

Abstract: An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.

Abstract: A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1) comprises is applied to said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A high-speed current switch circuit of this invention has an n-type MOS transistor Q11 which switches and outputs a current, and a control circuit 11 which performs switching control of the MOS transistor Q11. In the control circuit 11, a source follower is formed by an N-type MOS transistor Q12 and a constant current source I2 which is a load on this transistor. A switch SW11 is connected to the MOS transistor Q12 to perform switching control of a current flowing through the MOS transistor Q12. The control circuit 11 includes a switch SW12 capable of grounding the gate of the MOS transistor 11. The source of the MOS transistor Q12 is connected to the gate of the MOS transistor Q11. Thus, even if a large current is caused to flow through the output transistor, the output transistor can be made to operate for switching at a high speed.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS technology and can be applied to various applications, including monolithic integration of high-voltage display driver circuits in battery-powered applications.

Abstract: A semiconductor circuit disclosed herein includes a first output MOS transistor which includes a first terminal connected to a first power source and a second terminal connected to an output terminal to be connected to a load circuit; a second output MOS transistor which includes a third terminal connected to a second power source and a fourth terminal connected to the output terminal; a first functional block circuit which is connected between a control terminal of one of the first output MOS transistor and the second output MOS transistor and the output terminal, wherein the first functional block circuit includes at least one first diode, the first diode being a CB shorted NPN transistor or a CB shorted LPNP transistor; and a second functional block circuit which is provided in parallel with the first functional block circuit and includes at least one second diode connected in an opposite direction to the first diode of the first functional block circuit, the second diode being a CB shorted NPN transistor

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A driver including first and second buffers connected in parallel between a power source and a return path. In one configuration, the buffer outputs are commonly connected to an external coil and optionally a capacitive load. In another configuration, the buffers' outputs independently drive first and second external transistors. The external transistors are in series between a supply voltage source and its return path.

Abstract: An integrated device having a pad receiving, in a standard operative condition, an input signal having a first value and, in a test operative condition, a test voltage having a second value higher than the first value; an input stage connected to the pad and including an electronic component having a first terminal connected to the pad; a third-level detecting stage connected to the pad and supplying a logic third-level signal having a first level in presence of the input signal and a second level in presence of the test voltage; and a selector connected to a second terminal of the electronic component and structured to connect the second terminal to a reference potential in the presence of the first logic level of the third-level signal and to a biasing voltage higher than the reference potential and lower than the second value in the presence of the second logic level of the third-level signal.

Abstract: A power switching circuit including an MOS power switching transistor (P1) is disclosed. The power switching transistor (P1) has a body node that is selectably biased to either its source or its drain, depending upon a comparison of the voltage at the circuit input (IN) relative to the voltage at the circuit output (OUT). In a reverse voltage situation in which the output voltage exceeds the input voltage, a first body node switching transistor (P11) connected between the body node of the power switching transistor (P1) and its source is turned off by a voltage corresponding to the output voltage, as conducted from the drain of the power switching transistor (P1) through a pull-down device (P5) in an inverter.