Abstract: An analog circuit apparatus connected to a high voltage source includes a transistor and an interface unit. The transistor has a low operation voltage smaller than the high voltage source and a breakdown voltage. The interface unit is coupled to the transistor in series for preventing the low operation voltage higher than the breakdown voltage.

Abstract: An output buffer circuit of the invention comprises a first output transistor connected between a power supply potential node and an output node, a second output transistor connected between a ground potential node and the output node, a first control circuit for controlling a conductive state of the first output transistor, a first clamp circuit for supplying a given potential to a first node to which the first control circuit is connected, a control circuit for controlling a conductive state of the second output transistor, and a second clamp circuit for supplying a given potential to a second node to which the second control circuit is connected. The first clamp circuit supplies a given potential to the first node when the first control circuit is inactivated, and stops the supply of the given potential when the first control circuit is activated.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A power switching circuit including an MOS power switching transistor (P1) is disclosed. The power switching transistor (P1) has a body node that is selectably biased to either its source or its drain, depending upon a comparison of the voltage at the circuit input (IN) relative to the voltage at the circuit output (OUT). In a reverse voltage situation in which the output voltage exceeds the input voltage, a first body node switching transistor (P11) connected between the body node of the power switching transistor (P1) and its source is turned off by a voltage corresponding to the output voltage, as conducted from the drain of the power switching transistor (P1) through a pull-down device (P5) in an inverter.

Abstract: A switch circuit formed on a semiconductor substrate, comprising: a first terminal to which a signal of transmission object is inputted; a second terminal from which a signal of transmission object is outputted; a first transistor formed in a first semiconductor region in said semiconductor substrate, which has one of a source and a drain terminals connected to said first terminal and another thereof connected to said second terminal; a control circuit which controls a gate voltage of said first transistor; and a first rectifying element which has an anode terminal connected to said first terminal, a cathode terminal connected to a power supply terminal of said control circuit, said first rectifying element being formed in a second semiconductor region in said semiconductor substrate separate from said first semiconductor region.

Abstract: An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.

Abstract: A source follower in which any one of the following three modes is selected by a plurality of switching elements: a first mode in which a first potential is supplied to a gate of a transistor and an input potential is supplied to a first electrode of a capacitor respectively and a second electrode of the capacitor and a source of the transistor are connected, a second mode in which an input potential is supplied to the first electrode and the gate of the transistor and the second electrode floats, and a third mode in which the first electrode and the gate of the transistor are connected and a potential thereof floats and a second potential is supplied to the second electrode, a drain of the transistor is supplied with a third potential, and a potential of the source of the transistor is supplied to a subsequent circuit.

Abstract: The invention provides an analog switching device adapted to compensate for the effects of high frequency input signals. By providing a high pass filter between the input or output nodes and the control node it is possible to effectively introduce a portion of the high frequency component of the input signal to the control node, thereby reducing the differential between the nodes.

Abstract: Disclosed herewith is a semiconductor integrated circuit provided with a differential input circuit that can transmit data signals fast to an internal circuit free from distortion of their waveforms without increasing the subject chip in size. The differential input circuit is provided with a pair of first differential input transistors used to amplify mainly the low frequency components of those input signals and having gate terminals connected to a pair of input terminals that receive inputs of differential signals respectively, as well as a pair of second differential input transistors used mainly to amplify high frequency components of those input signals and having control terminals connected to a pair of input terminals that receive inputs of differential signals respectively through capacitance elements. The pairs of first and second differential transistors are connected to each other through a differential connection point (common source).

Abstract: An apparatus comprising a device and a resistor. The device generally comprises (i) a gate configured to receive an input voltage, (ii) a drain coupled to a first supply voltage, and (iii) a source coupled to an output. The resistive element is generally coupled between the source and a second supply voltage. The apparatus generally provides voltage tolerance between the input voltage and the output.

Abstract: A circuit configuration for signal balancing in antiphase bus drivers, particularly for a CAN bus, which have, in each driver path of the bus, a driver amplifier unit and an output stage, driven by the latter, having a power transistor circuit for transmitting an antiphase signal using a two-wire line. A control circuit is connected to one of the driver paths and controls the turn-on resistance of the power transistor circuit in this driver path such that the power transistor circuits in the two driver paths have the same turn-on resistance.

Abstract: According to some embodiments, a charge pump includes a first transistor to steer an amount of current to a second transistor coupled to the first transistor in a first folded cascode arrangement and to a current mirror to sink substantially the amount of current from a load, and a third transistor to steer the amount of current to a fourth transistor coupled to the third transistor in a second folded cascode arrangement to source substantially the amount of current to the load.

Abstract: Upon generating an inversion input signal to be inputted to a level shifter section in an inverter section, a voltage VHL, which gives an output voltage of a high level in the inverter section, is generated by a resistance division from the power supply voltages VHH and VLL in a voltage-dividing section. Thus, it becomes possible to provide a level shift circuit which can realize a reduction in the number of terminals and low power consumption by using a simple circuit construction.

Abstract: A level-shifter architecture with high-voltage driving capability and extremely low power consumption, exploiting dynamic control of the charge on the gate electrodes of the high-voltage output transistors, is provided. The architecture can be integrated in CMOS technology and can be applied to various applications, including monolithic integration of high-voltage display driver circuits in battery-powered applications.

Abstract: A high-frequency compatible bidirectional level conversion circuit in which high-voltage port A and low-voltage port B are connected using pass transistor 12, and the side of port A is connected to power supply voltage terminal C using primary and secondary switching circuits 21 and 22 connected in parallel. When port B changes from low level to high level to transmit a level-converted signal from the side of port B to the side of port A, the level at port A rises to turn on primary and secondary switching circuits 21 and 22, and secondary switching circuit 21 turns off after port A has reached the high level. When secondary switching circuit 22 is configured to have a lower impedance than that of primary switching circuit 21, the load capacitance connected to port A is charged by a high current which flows in secondary switching circuit 22 as the level of port A rises. When port B changes from the high level to the low level, secondary switching circuit 22 remains off.

Abstract: The present application and invention provides a selectively enabled bias for the pass NMOS transistor (10) of an RF switch. Two bias supplies are selectively switched to connect to the source of the NMOS transistor (10). The first higher bias supply turns the NMOS transistor (10) off and the second lower bias supply turns the NMOS transistor (10) on. The selective switch performs a single pole double throw function and may include PMOS transistors (14, 16) with inverse logic signals connected respective gates. Diodes may be used between the PMOS and the NMOS gate to reduce the capacitance load at the NMOS gate. The bias circuitry provides for lower capacitance values in the NMOS transistor (10) for reducing insertion loss, and lower parasitic input to output capacitance thereby providing better isolation when the switch is off. Moreover, when the switch is on the source to substrate and the drain to substrate capacitances are decreased thereby providing better high frequency isolation.

Abstract: An output buffer includes a pair of main complimentary MOS transistors connected to at least one additional pair of complementary MOS transistors connected in parallel to the pair of main transistors by means of a pair of switches controlled by a numeric word for activating or not activating the additional pair of transistors. A control circuit delivers the numeric word which represents the conductivity of the pair of main transistors included in the output buffer. The additional transistors are sized in such a way that when they are activated, the equivalent impedance of the output buffer is approximately constant.

Abstract: A switching point detection circuit for detecting a switching point according to a fabrication condition of MOS transistor, includes a reference voltage generation unit for generating a reference voltage, a first CMOS inverter, in which an NMOS transistor is dominant for the reference voltage, receiving the reference voltage and a second CMOS inverter, in which a PMOS transistor is dominant for the reference voltage, receiving the reference voltage.

Abstract: A CMOSFET switch includes a NMOSFET, a PMOSFET, an input formed at the connection of the source terminals of the MOSFETs, and an output formed at the connection of the drain terminals of the MOSFETs. At least one of the MOSFETs is characterized by a small magnitude inherent threshold voltage, or the CMOSFET switch has at least one circuit that is capable of reducing a voltage difference between the source and body terminals of a MOSFET, or both. The variations in on resistance can be reduced over a wide common mode range by reducing the threshold voltages of the NMOSFET and the PMOSFET of the CMOSFET switch.

Abstract: In a non-contact IC card, corresponding to increase/decrease of an operation current of an internal circuitry, absorbing current of an ICC fluctuation absorbing circuit is temporarily decreased/increased by the amount corresponding to the increase/decrease, and thereafter, the absorbing current is gradually increased/decreased to the initial value and an output current of a regulator is gradually increased/decreased. Therefore, abrupt change in output current of the regulator can be prevented, and an internal power supply potential can be stabilized.

Abstract: A voltage regulator has an input terminal, an output terminal, a first transistor connecting the input terminal to an intermediate terminal, a second transistor connecting the intermediate terminal to ground, a controller that drives the first and second transistors to alternately couple the intermediate terminal between the input terminal and ground, and a filter disposed between the input terminal and the output terminal to provide a substantially DC voltage at the output terminal. The controller drives the two transistors with different gate voltage, and the two transistors can have different gate oxide layer thicknesses.

Abstract: An analog switch and an analog multiplexer are realized by which electron charges which have been stored in a stray capacitance provided on the output side thereof before a switch is conducted do not give an adverse influence to a level of such an analog input voltage which is subsequently entered after the switch has been switched. An analog switch circuit is arranged by insulating gate type transistors and a voltage follower which is parallel-connected to these insulating type transistors. When the analog switch circuit is turned ON, the voltage follower is firstly brought into an active state, and thereafter, these insulating gate type transistors are brought into conductive conditions.

Abstract: A bi-directional high-voltage RESURF EDMOS (REduced SURface Extended Drain MOS) transistor which can endure a high voltage at its source by providing drift regions at both sides, i.e., the source and drain of the conventional RESURF LDMOS (Lateral DMOS) transistor, and exchanging the drain and the source when an analog signal of high voltage is inputted. Further, the bi-directional high-voltage RESURF EDMOS transistor provides a high-voltage analog multiplexer circuit employing a RESURF EDMOS transistor which is capable of reducing the number of necessary high-voltage elements and performing a stable operation, by constructing a high-voltage analog multiplexer having at least three inputs and a multistage high-voltage multiplexer circuit of push-pull type, pass transistor type, and combined form of push-pull type and pass transistor type by using the bi-directional high-voltage, RESURF EDMOS transistor.

Abstract: A new level shifting circuit, using a zero threshold voltage device, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has input connected to the input of the level shifting circuit and output forming an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first zero threshold NMOS transistor has the gate connected to a low bias voltage and the source connected to the first NMOS transistor drain. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first zero threshold NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input and the source connected to ground.

Abstract: A driver circuit drives at least one power switch, which circuit comprises a final stage including a complementary pair of power transistors connected to said switch at a common output node. Advantageously, this circuit comprises a respective power-on buffer stage, connected in upstream of each of the power transistors, and a power-on detector associated with each power transistor, the detector associated with one of the power transistors being connected to the buffer stage of the complementary one of the transistors to prevent the power transistors from being turned on simultaneously.

Abstract: A high performance integrated circuit device enables scaled low voltage transistors to be utilized as transfer gates with improved speed characteristics. At least some of the transistors are formed with thicker gate oxides and boosted positive and negative drive voltages are used with the thicker gate oxide transistors. The transfer gates may be driven by an inverter using a transistor formed in a triple well.

Abstract: A CMOS switch with compensation circuitry that maintains linearized gate capacitance, said switch capable of selectively processing a signal independent of changes to gate capacitance current. The switch passes signals which are substantially insensitive to changes in source impedance. Thus, the switch processes an analog signal with a minimum of distortion as a result of gate capacitance currents.

Abstract: In a parallel circuit (10) comprising a plurality of high-power IGBTs (T1, . . . ,T3) which are each driven by a dedicated gate drive circuit (GD1,. . . ,GD3), each of the gate drive circuits (GD1,. . . ,GD3) having, at its output, a p-channel MOSFET (M1, M3, M5) and an n-channel MOSFET (M2, M4, M6) in a push-pull arrangement and the outputs of the gate drive circuits (GD1, . . . ,GD3) being connected to the gates of the IGBTs (T1,. . . ,T3) in each case via a gate resistor (R1,. . . ,R3), a parallel circuit comprising more than two gate drive circuits is made possible by virtue of the fact that the outputs of the gate drive circuits (GD1,. . . ,GD3) are interconnected via a connecting line (11), and that the MOSFETs (M1,. . . ,M6) of the gate drive circuits (GD1,. . . ,GD3) are in each case connected to a positive or negative supply terminal (P1, . . . ,P3 or N1, . . . ,N3) via a constant-current source (CS1,. . . ,CS6).

Abstract: An input protection circuit capable of precisely bypassing a surge current to a power source terminal and protecting the gate of a protective transistor from an electrostatic surge. The input protection circuit has an input terminal which receives an input signal, a first power source terminal which receives a first power source electric potential, and a first protective power source potential line connected to the first power source terminal for supplying the first power source electric potential to an input protection circuit. The input protection circuit has a first input protection transistor of a first conductive type having a drain connected to the input terminal, a gate and a source connected to the first protective power source potential line.

Abstract: A circuit and method for controlling a switch include a level shifter that controls a dynamic, bi-directional high voltage analog switch. The level shifter generally includes transistors, input terminals, a voltage source, a high negative voltage source, and a diode. The configuration of the level shifter, inter alia, allows the switch to be kept ON without a current/signal, prevents dissipation of transistors of the level shifter, and provides constant gate-to-source voltage on the switch transistors for improved linearity.

Abstract: Clocked half-rail differential logic circuits are activated by a delayed clock. According to the invention, when clocked half-rail differential logic circuits of the invention are cascaded together, a delayed clock is provided for each clocked half-rail differential logic circuit and each delayed clock is timed to at least the delay of the previous clocked half-rail differential logic circuit. Consequently, according to the invention, a delay time is introduced to ensure each clocked half-rail differential logic circuit of the invention is switched or “fired” only after it has received an input from the previous clocked half-rail differential logic circuit stage. According to the invention, this is achieved without the use of complicated control circuitry.

Abstract: A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor.

Abstract: A low-noise buffer circuit stabilizing the output voltage and current to prevent noise, includes current sources connected between the CMOS circuit and power supply sources providing a power supply for the CMOS circuit, a resistor element connected to the current sources and in parallel with the CMOS circuit, the resistor element bypassing current between the current sources to prevent current fluctuation.

Abstract: In a semiconductor integral circuit having a transistor or an inverter, a leak current of the transistor or a through current of the inverter, respectively, or the like is reduced. The semiconductor integral circuit has an analog circuit which changes linearly the voltage of an input signal and causes the amount of a current flowing through the analog circuit to change in accordance with the change in the voltage of the input signal. The semiconductor integral circuit also has a logic circuit to which an input signal having a first or second voltage is input. This logic circuit outputs an output signal having the first or second voltage in response to the first or second voltage of the input signal. The absolute value of the threshold value of the MOS transistor of the analog circuit is set smaller than the absolute value of the threshold value of the MOS transistor of the logic circuit.

Abstract: An output buffer with built-in ESD protection is disclosed. The built-in ESD protection is preferably formed using transistors from the sea-of-transistors or sea-of-gates region of the integrated circuit, which may eliminate the need for dedicated ESD devices, and in particular, dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: An electronic circuit having first (VSS) and second (VDD) power supply terminals and comprising a first digital driver (DRV) and a further digital driver (DRVF). The digital drivers (DRV, DRVF) are arranged for driving capacitive loads such as charge pump capacitors (CP1, CP2) of a charge pump (CHGP). The first digital driver (DRV) comprises a first field effect transistor (T1) having a source coupled to the first power supply terminal (VSS), a drain coupled for driving the first charge pump capacitor (CP1), and a gate; a second field effect transistor (T2) having a source coupled to the second power supply terminal (VDD), a drain coupled to the drain of the first field effect transistor (T1), and a gate; a first capacitor (C1) coupled between the gate of the first field effect transistor (T1) and an input terminal (CLK) for receiving a digital input signal (UCLK); and a second capacitor (C2) coupled between the gate of the second field effect transistor (T2) and the input terminal (CLK).

Abstract: A voltage regulator has an input terminal, an output terminal, a first transistor connecting the input terminal to an intermediate terminal, a second transistor connecting the intermediate terminal to ground, a controller that drives the first and second transistors to alternately couple the intermediate terminal between the input terminal and ground, and a filter disposed between the input terminal and the output terminal to provide a substantially DC voltage at the output terminal. The controller drives the two transistors with different gate voltage, and the two transistors can have different gate oxide layer thicknesses.

Abstract: Both buses connected to a bus switch are protected from undershoots. A bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. An enable gate drives the gate node of the bus switch transistor high to enable or low to disable. Undershoot sensing circuits are attached to the first and second bus. When a low-going transition is detected by an undershoot sensing circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off.

Abstract: A ramping circuit gradually applies an erasing voltage to a memory cell. Within the ramping circuit an NMOS transistor is disclosed which gradually supplies the erasing voltage to the memory cell in response to an external ramping voltage. The NMOS transistor supplies the erasing voltage until the loss voltage of the transistor limits a maximum erasing voltage that the NMOS transistor can supply. The specification then discloses a PMOS transistor which operates to supply the erasing voltage to the memory cell when the NMOS transistor can no longer do so. The PMOS transistor is connected to control circuitry which keeps the PMOS transistor inactive until the output voltage of the NMOS transistor is limited by its voltage loss.

Abstract: A function generator includes a switching stage for forming a defined signal waveform. The switching stage includes switching transistors that are turned on in a predetermined sequence of undelayed and delayed clock signals, with an output node summing the output currents of the switching transistors. The function generator also includes a delay device that generates the undelayed and delayed clock signals from an applied clock signal. The delays of the delayed clock signals define predetermined instants within at least one period of the applied clock signal. The switching edge is divided into different time ranges whose respective edge steepnesses are adjustable independently of each other. By point-mirroring the signal waveform about a medium value of the signal edge, frequencies at twice, four times, six times, etc. the frequency of the fundamental signal frequency are reduced.

Abstract: An improved auto-zeroing circuit for reducing offset currents from high impedance CMOS current drivers. The Auto zero circuit of the present invention contains means to disconnect the output of the current driver from its low impedance load, means to substantially simultaneously connect a capacitor to the output of the current driver, and means to use the output voltage of the current sources during the zeroing mode to adjust the voltage on the capacitor. The capacitor voltage is then used to adjust either of the two output current sources to reduce the offset currents.

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract: Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors have a PFET conduction threshold voltage. The N-channel transistors have an NFET conduction threshold voltage. The threshold voltages are determined by extrapolation from the (high) gate to source voltage. Each of the N-channel transistors is paired with a corresponding P-channel transistor. The pairing is arranged in complementary symmetry (CMOS). A power supply connected across one of the pair formed from N-channel and P-channel transistors arranged in complementary symmetry is set to a voltage equal to the sum of the PFET conduction threshold voltage and the NFET conduction threshold voltage.

Abstract: A current-limit circuit and a method of limiting current supplied to a load through a power transistor utilize a control transistor that is selectively activated to a conducting state to limit the current conducted through the power transistor in response to a predefined condition. The predefined condition may be a short-circuit condition or an over-current condition. The configuration and operation of the control transistor are such that, when the control transistor is in a conducting state, the current conducted through the power transistor is limited by the structural ratio of the two transistors. However, during normal operating conditions when the control transistor is deactivated to a non-conducting state, the control transistor does not degrade the performance of the power transistor. In a first embodiment, the current-limit circuit is configured to provide protection from a short-circuit condition.

Abstract: A driver circuit in accordance with the present invention combines current controlled current source and sink circuits, which are independent of process, temperature, and supply voltage, and voltage controlled current source and sink circuits to control the slew rate at the output of the driver circuit and thereby reduce switching noise. The driver includes an output transistor coupled to an output node, a current source, a current mirror transistor having a control node connected to the control node of the output transistor and a conduction path coupled to the current source, and a voltage controlled switch coupled between the conduction path of the current mirror transistor and the control node of the output transistor. The voltage controlled switch is coupled to the output node and is open when the output node is within a first voltage range, and is closed when the output node is within a second voltage range.

Abstract: A low voltage CMOS bus switch (20) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (30) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref2, Dref3) when the supply (Vcc) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN1,MP1) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR1) turns off and a gate voltage of a N-channel pass transistor (MN1) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3.3V or 5V bus.

Abstract: Ground and power-supply bounce are reduced for a CMOS output buffer. An n-channel driver transistor and a p-channel driver transistor are attached to the output pad. The gate of the n-channel driver transistor is driven by a pre-driver inverter. The pre-driver is a CMOS inverter except that the p-channel source is connected to power through a p-channel and an n-channel source-control transistor in parallel. The n-channel source-control transistor has its gate connected to power so that it remains on. The p-channel source-control transistor has its gate driven by feedback. The feedback is buffered from the output pad, or inverted from the gate of the driver transistor. When the output buffer switches, only the n-channel source-control transistor is initially on, so the current charging the driver gate is limited. The driver turns on slowly at first. Later, the feedback turns on the p-channel source-control transistor, increasing (doubling) the current to charge the driver gate.

Abstract: Disclosed is a current booster or kicker for an output amplifier of a programmable logic control or other integrated circuit. The current booster includes a control mechanism and an auxiliary voltage supply. When a change in output state is initiated, the control mechanism connects the auxiliary voltage supply to the output of the output amplifier. After a change in output state in completed, the control mechanism disconnects the auxiliary voltage supply from the output of the output amplifier. In this way, the output amplifier can drive a relatively high capacitance load at a relatively high slew rate.

Abstract: A decoder circuit includes a detecting device which detects a selecting signal for selecting the decoder circuit, a clock-signal supplying device which supplies a clock signal, and a decoded signal outputting device which outputs a decoded signal according to timing of the clock signal when the detecting device detects the selecting signal.