Abstract: A circuit to a extend signal comparison voltage range includes a latching circuit and a comparator responsive to common-mode input signals. The comparator is coupled to the latching circuit and to a dynamic node. The circuit also includes a clocked boost circuit coupled to the dynamic node. The clocked boost circuit is configured to extend a supply voltage range of the comparator via biasing the dynamic node. A method to extend a signal comparison voltage range includes selectively shifting a voltage level of one of a ground reference of a dynamic circuit or a supply reference of the dynamic circuit in response to a clock signal.

Abstract: Several circuits and methods for field-based communication are provided. In an embodiment, a field-based communication circuit includes a receiver circuit, a detection circuit and a control circuit. The receiver circuit is configured to receive a field input signal from a field source. The detection circuit includes a voltage detection circuit and a current detection circuit configured to detect a voltage signal and a current signal, respectively associated with the field input signal. The control circuit is configured to trigger a selection of one of the voltage detection circuit and the current detection circuit based on a detection of a signal magnitude of one of the voltage signal and the current signal relative to at least a first predetermined threshold level, wherein the selection of one of the voltage detection circuit and the current detection circuit facilitates a demodulation of one of the voltage signal and the current signal.

Abstract: An object is to widen detection range of current. A current detection circuit includes a first resistor, which is connected to a first connection terminal and a second connection terminal; a second resistor, which is connected to the first resistor; a third resistor, which is connected to the first resistor; a first transistor, a source of which is connected to the second resistor; a second transistor, a source of which is connected to the third resistor, and a drain and a gate of which is connected to a gate of the first transistor; a third transistor, a source of which is connected to the source of the second transistor, and a gate of which is connected to the drain of the first transistor; and a fourth resistor, which is connected to the drain of the third transistor, and to which a voltage is input.

Abstract: An integrated circuit with multi-functional parameter setting and a multi-functional parameter setting method of the integrated circuit are provided. The multi-functional parameter setting method includes following steps: providing the integrated circuit which includes a switch unit and a multi-functional pin that is coupled to an external setting unit, sensing a programmable reference voltage of the external setting unit through one operation of the switch unit and executing a first function setting according to the programmable reference voltage, and sensing a programmable reference current of the external setting unit through another operation of the switch unit and executing a second function setting according to the programmable reference current.

Abstract: A circuit includes multiple input sub-circuits coupled to a common output node. Each input sub-circuit includes a transconductance cell. A diode is coupled between the output of the transconductance cell and a common output node. A feedback circuit is coupled between the common output node and a second input of the transconductance cell. A voltage follower is coupled between the common output node and a reference voltage, with an input coupled to the output of the transconductance cell.

Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.

Abstract: Hardware interrupt functionality associated with a disable pin may be used to place a near-field communication (NFC) device into various operational modes. For example, various intermediate voltage windows may be defined within an I/O voltage domain and a resistive divider running off an I/O rail may generate multiple reference voltages within the I/O voltage domain. In one embodiment, different comparators may compare voltage on the disable pin to the reference voltages generated with the resistive divider to determine whether the voltage on the disable pin falls within one of the intermediate voltage windows. As such, if a particular comparator determines that the voltage on the disable pin falls within one of the intermediate voltage windows, a control signal may be generated to transition the NFC device into a corresponding operational mode.

Abstract: Discussed herein is a method of controlling polarity of a data voltage and a liquid crystal display using the same, the method including calculating a direct current DC value of the data from each group which data to be output through I-channels adjacent to each other in a source drive IC belong; accumulating the DC value; comparing an absolute value of the accumulation DC value of the n-th group obtained by adding the accumulation DC value of the n?1-th group accumulated up to the n?1-th group to the DC value of the n-th group (n is positive integer) with a predetermined threshold value; and changing a group polarity data when the absolute value of the accumulation DC value of the n-th group exceeds the threshold value.

Abstract: A device (10) for determining the number of discrete events represented by an input signal is provided. The input signal may, for example, comprise pulses representing photons arriving at a detector. The device (10) may comprise a plurality, n, of comparator circuits (14) for reading the signal. For each comparator circuit (14) from i=1 to i=n, the comparator circuit (14) has a corresponding threshold value which the amplitude of a pulse representing i discrete events will exceed, but which the amplitude of a pulse representing i-1 discrete events will not exceed. Each comparator circuit (14) is arranged to output a first value when the input signal exceeds its threshold value and a second value when the input signal is less than its threshold value. The device (10) includes a counter (16) for counting the number of outputs of the first value that have been output by the plurality of comparator circuits (14).

Abstract: A comparator circuit includes a first comparator configured to store an offset during a first period, and to compare first and second input signals while compensating for the stored offset to generate a first comparison signal during a second period, a second comparator configured to compare the first and second input signals while compensating for an offset to generate a second comparison signal, and a compensation amount controller configured to control an offset compensation amount of the second comparator when the first and second comparison signals have different values.

Abstract: A voltage generator includes a digital-to-analog (D/A) converting device configured to convert an input voltage to a pair of analog voltages, and a voltage mixer coupled to receive the analog voltages via electrical wirings to combine one or both of the analog voltages into an output voltage.

Abstract: A bidirectional interface circuit includes a first current mirror circuit that copies a first reference current to generate a first current sunk from a first output terminal, a second current mirror circuit that copies a second reference current to generate a second current sunk from a second output terminal, an interception switch that is connected between the first output terminal and the second output terminal, a first comparator that outputs an upper state signal based on a comparison result of a voltage of the first output terminal and a first threshold voltage, a third current mirror circuit that copies one of a third reference current and a fourth reference current to supply a third current flowing to a third output terminal, and a second comparator that outputs a lower state signal based on a comparison result of a voltage of the second output terminal and a second threshold voltage.

Abstract: Systems and methods provide LED-based emergency lighting utilizing AC-DC switch mode power conversion technology, NiMH battery technology, and emergency lighting lamps that use high power white LEDs as the emergency lighting source. A low voltage microprocessor based circuit design reduces the battery input voltage for the unit to a nominal level of 2.4VDC. The microprocessor executes a pulse charging algorithm to lower battery maintenance mode power consumption levels and extend the useful life of the battery. Brownout detection technology does not require the determination of the AC input voltage level or transmission of the brownout detection signal to the secondary side of the circuit. A rechargeable battery is charged by a charge current selectively set to a bulk charge value, a trickle charge high value, or a trickle charge low value based on sampling of the voltage of the rechargeable battery and the charge current.

Abstract: In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier. A second resistance is coupled to the input node of the amplifier. A first switch is configured to be controlled during a first interval to couple the second resistance to a positive resistance to increase a gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to a negative resistance to decrease the gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the negative resistance.

Abstract: A comparator compares a first input voltage and a second input voltage to generate a comparative output depending on a result of the comparison. The comparator includes a first input terminal configured to receive the first input voltage, a second input terminal configured to receive the second input voltage, a differential pair including a first input transistor whose control terminal is connected with the first input terminal and a second input transistor whose control terminal is connected with the second input terminal, a tail current source configured to supply a tail current to the differential pair, and a load circuit connected to the first input transistor and the second input transistor, and the tail current source increases the tail current, as the first input voltage approaches the second input voltage, depending on the first input voltage.

Abstract: A data persistence control apparatus for an RFID tag is provided. The apparatus includes a capacitor to be charged, a charge circuit to charge the capacitor, a discharge circuit to discharge the capacitor, a switch switched on to electrically connect the charge circuit to the capacitor or the discharge circuit to the capacitor, and an output circuit to output a logic high signal or a logic low signal according to an input voltage determined based on a discharged degree of the capacitor.

Abstract: A display driver maps a selection code (a digital signal) to a reference voltage which is then used to produce a particular intensity of the radiation emitted from a pixel on a display screen (e.g., a LCD display). This mapping may be performed by one or more DACs in the display driver. However, instead of transmitting all of the different possible reference voltages to the DACs, only a subset of the reference voltages are transmitted. Each DAC may include an interpolator circuit that uses the received reference voltages to interpolate the reference voltages that were not transmitted. In this manner, the display driver may still provide the same number of unique reference voltages to a display screen while transmitting fewer reference voltages along the driver's optical channel.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: A communication apparatus includes a communication connector, a communication section, a connection section, a state detector, a controller and a warning section. The communication section controls communication performed through the communication connector, to which a communication plug is connected. The connection section connects the communication connector and the communication section. The state detector generates a state detection signal corresponding to a connection state of the communication plug relative to the communication connector. The controller determines which of a normal connection state, an improper connection state and a non-connection state the communication plug is in based on the state detection signal. The controller also controls an ON-OFF operation of the connection section. The warning section notifies a user of results determined by the controller.

Abstract: A method for determining a trigger level for a periodic analog signal in a digital signal processing system is provided. The method reduces output jitter as much as possible and avoids false trigger events. To this end, the method includes measuring the minimum and maximum values of the signal in a predetermined time, defining a plurality of potential trigger values between the minimum and maximum values, assigning to the respective potential trigger value a jitter value characteristic for the jitter created by processing the signal with the potential trigger value, and determining the optimal trigger level based on the lowest jitter value.

Abstract: Glasses apparatus interlocking with a 3D display device is provided. The glasses apparatus includes a shutter glasses unit, a synchronous signal receiving unit receiving a synchronous signal from the 3D display device, a shutter glasses which drives unit driving the shutter glasses unit, a DC/DC converter unit which converts converting a DC voltage provided from a battery, and a control unit which controls the DC/DC converter unit to apply the converted DC voltage to the shutter glasses driving unit through supplying of a PWM signal to the DC/DC converter unit and controlling the shutter glasses driving unit, which is driven by the applied DC voltage, to turn on/off the shutter glasses unit according to the synchronous signal.

Abstract: A method performs a comparison of input signals in a window comparator circuit. In a first phase, input, ground and offset voltages are stored on capacitors. A comparison is performed between a first adapted input voltage and a second adapted input voltage added to an adapted offset voltage, to provide a first output signal. In a second phase, the voltages are stored on the capacitors in a different manner. A comparison is performed between the first adapted input voltage added to the adapted offset voltage and the second adapted input voltage, to provide a second output signal. Finally, a control of the state of the output signals is performed to determine if the comparison is in a low or high state if the output signals have a same low or high output level, or in an intermediate state if the output signals have a different output level.

Abstract: A device for continuous time quantization of an input signal, in order to supply a continuous time output signal that is quantized as two bits, the device including: an electronic circuit, designed to supply a first bit of the output signal called the sign bit which at any time takes a first value when the input signal is positive and a second value when the input signal is negative, and an envelope analysis circuit designed to supply a second bit of the output signal called the envelope variation bit which at any time takes a first value, called high value, when an envelope signal of the input signal is increasing, and a second value, called low value, when the envelope signal is decreasing.

Abstract: Methods, systems, and devices are described for providing voltage comparison adapted to operate at high-speeds and over a relatively large range of supply voltages.

Abstract: An integrated circuit includes a configurable interface. The configurable interface includes an operational amplifier, a programmable gain amplifier, an analog-to-digital converter and a first select circuit. The first select circuit is configured to selectively couple the operational amplifier to the analog-to-digital converter in response to a first control signal. The first select circuit is further configured to selectively couple the programmable gain amplifier to the analog-to-digital converter in response to the first control signal.

Abstract: In one embodiment, an apparatus includes an amplifier configured to receive an asymmetric signal. A first resistance is coupled between an input node and an output node of the amplifier. A second resistance is coupled to the input node of the amplifier. A first switch is configured to be controlled during a first interval to couple the second resistance to a positive resistance to increase a gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the positive resistance. A second switch is configured to be controlled during a second interval to couple the second resistance to a negative resistance to decrease the gain of the amplifier to correct the asymmetric signal. The gain is a function of the first resistance and a combination of the second resistance and the negative resistance.

Abstract: In an embodiment, a self-defense system is disclosed. The self-defense system may include or comprise a material sized to conform to an appendage, and a defense unit coupled with the material and positioned to initiate a defense event in response to an input.

Abstract: A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.

Abstract: A flip-flop circuit includes a D flip-flop and a leakage current suppression circuit. The D flip-flop receives an input signal and a clock signal, and outputs a voltage of the input signal at a rising or falling edge of the clock signal as an output signal. The leakage current suppression circuit detects an output error caused by the leakage current flowing through at least a floating node of the D flip-flop and compensates for the leakage current to correct the output error. The leakage current suppression circuit includes a detection circuit and a compensation circuit. The detection circuit receives the output signal and clock signal and detects whether the output error has occurred to generate a detection result. The compensation circuit compensates for the leakage current according to the detection result to correct the output error.

Abstract: A binarization circuit includes a comparator that outputs a signal according to a differential voltage between the input and reference voltages. The first charging-discharging circuit generates a first voltage. The second charging-discharging circuit generates a second voltage. The control circuit compares the differential voltage with the threshold voltage, and switches between turn-on and turn-off of the second charging-discharging circuit based on a difference between the differential voltage and the threshold voltage. A sum of the reference and first voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned off. A sum of the reference and the first and second voltages of the preceding clock is supplied to the comparator when the second charging-discharging circuit is turned on.

Abstract: A differential amplifier stage under a band design whereby a data signal at a maximum transfer rate among received waveforms is subjected to attenuation upon passing through a transmission line is not amplified, and a signal at a transfer rate half the maximum transfer rate is amplified. If it is determined that a signal whose amplitude is larger in value than a high reference voltage, the signal is determined as a signal “1” while if smaller in value than a low reference voltage, the signal is determined as a signal “0”. If the first amplitude detector detects that the amplitude of the signal is smaller in value than the high reference voltage, and the second amplitude detector detects that the amplitude of the signal is larger in value than the low reference voltage, the present signal is determined as an inverting signal of an immediately preceding signal.

Abstract: A data receiving apparatus and method includes a current-voltage conversion block, which receives a current-type transmit signal including data and a clock signal inserted into the data at a different level from the data, and then converts the received signal into at least one first voltage and at least one second voltage having a different level from the first voltage, and a comparison block, which makes a comparison between the first and second voltages, and then outputs the received signal as one of the data and the clock signal based on a result of the comparison. The data receiving apparatus can easily recover a clock signal while exhibiting better characteristics during the recovery of the clock signal because it is insensitive to a variation in reference voltage and a variation in current at the transmitting state of the timing controller, which are caused by a process variation.

Abstract: A host computer includes an enclosure, a motherboard mounted in the enclosure. The motherboard includes a battery, a reference voltage generating circuit, an electronic switch, an alarm unit mounted on the enclosure, and a comparator. The reference voltage generating circuit generates a reference voltage. The comparator is connected to the battery and the reference voltage generating circuit to receive the reference voltage and detect a voltage of the battery. The comparator compares the detected voltage of the battery with the reference voltage, and outputs a control signal to turn on the electronic switch to start the alarm unit when the voltage of the battery is less than the reference voltage.

Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit specifies the kind of charger by detecting the voltages of a DP terminal and a DM terminal. The charger detection circuit detects open, pull-up, pull-down of at least one of the DP terminal and the DM terminal or formation of a short circuit between both the terminals.

Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.

Abstract: One embodiment of the present invention relates to a method and apparatus to perform a low power activation of a system by measuring the slope of a digital signal corresponding to a motion sensor measurement value. In one embodiment, a low power activation circuit is coupled to magnetic motion sensor configured to output a magnetic signal proportional to a measured magnetic field. The low power activation circuit may comprise a digital tracking circuit configured to provide a digital signal that tracks the magnetic field and a difference detector configured to detect a difference between a current digital signal and a prior digital signal stored in a digital storage means. If the detected difference is larger than a digital reference level, an activation signal is output to awaken a system from a sleep mode.

Abstract: The present invention provides a semiconductor circuit including: a comparator section that compares discharge sections, each including a first signal line connected to a high potential side of each of a plurality of battery cells that are connected in series, a second signal line connected to a low potential side of each of the plurality of battery cells, a resistance element provided between the first signal line and the second signal line, and a discharge switching element connected in series to the resistance element, wherein the comparator section compares a threshold voltage, set according to a potential difference between a potential of the first signal line and a potential of the second signal line, with a voltage according to a potential between the resistance element and the discharge switching element.

Abstract: A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current.

Abstract: A method and apparatus for providing system clock failover using a one-shot circuit are disclosed. A process, in one embodiment, is able to detect a clock failure using a one-shot circuit, wherein the clock signals are generated by a first clock circuit. Upon generating a switching signal in response to the clock failure, a system reset signal is asserted for a predefined time period in accordance with the clock failure. After switching a second clock circuit to replace the first clock circuit, the process is capable of resuming the clock signals via the second clock circuit.

Abstract: A circuit is for generating a signal that indicates whether or not an input current exceeds a pre-established threshold current and, in the affirmative case, that is representative of the difference between the input current and the threshold current. The circuit includes a diode-connected transistor biased with a first constant current in a saturation functioning condition, a sense transistor mirrored to the diode-connected transistor and biased in a linear (triode) functioning condition, a load transistor connected in series to the sense transistor, biased with a second constant current and the control terminal of which is connected in common with the respective terminals of the diode-connected transistor and of the sense transistor. The input current to be compared is injected to a common current node of the load transistor and of the sense transistor, and the output voltage is available on the other current node of the load transistor.

Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.

Abstract: This document discusses, among other things, a multiple accessory detection apparatus and methods for identifying accessories coupled to a multi-pin connector of an electronic device. The apparatus can include a first reference generator, a second reference generator, a plurality of switches to couple an output of the second generator to an accessory device and a comparator. The comparator can generate identifying information about the accessory device using the reference information received from the first reference generator and test information received using the second reference generator.

Abstract: An imaging device includes a pixel section and an amplification unit which amplifies the signal of the pixel section. The amplification unit includes an input capacitor having first and second nodes, an amplification circuit, a first feedback capacitor connected between the input capacitor and an output portion of the amplification circuit, a first MOS transistor switch connected in series with the first feedback capacitor, a second MOS transistor switch which is connected in series with the first feedback capacitor, and has a drain and a source connected to each other, a second feedback capacitor connected between the input capacitor and the output portion, a third MOS transistor switch connected in series with the second feedback capacitor, and a fourth MOS transistor switch which is connected in series with the second feedback capacitor, and has a drain and a source connected to each other.

Abstract: A look-up table circuit according to an embodiment includes: a variable resistance circuit including variable resistance devices and selecting a variable resistance device from the variable resistance devices based on an input signal; a reference circuit having a resistance value between the largest resistance value and the smallest resistance value of the variable resistance circuit; a first n-channel MOSFET including a source connected to a terminal of the variable resistance circuit and a gate connected to a drain; a second n-channel MOSFET including a source connected to a terminal of the reference circuit and a gate connected to the gate of the first n-channel MOSFET; a first current supply circuit to supply a current to the variable resistance circuit; a second current supply circuit to supply a current to the reference circuit; and a comparator comparing voltages at a first input terminal and a second input terminal.

Abstract: A power supply is described. The power supply includes a synchronous sampled comparator. The synchronous sampled comparator includes a first input that receives a reference voltage. The synchronous sampled comparator also includes a second input that receives a feedback signal. The power supply also includes power field effect transistors (FETs). The power supply further includes an inductor coupled to the power FETs and coupled to the second input. The power FETs generate a power supply voltage using the inductor. The power supply voltage is a direct current (DC) power supply voltage.

Abstract: A key press detecting circuit for detecting the status of the key is provided. The key press detecting circuit comprises a discharging circuit which discharges when the key (K1) is pressed; and a voltage detecting circuit, which comprises a combination of a PNP transistor (T2) and a NPN transistor (T3), wherein when the discharging circuit discharges for a predefined period, the PNP transistor (T2) will be turn on, which causes the NPN transistor (T3) to be turned on and to output a second signal for a second function.

Abstract: A comparator has a first input, a second input, an output, a control electrode of a first hysteresis transistor coupled to the output, and a control electrode of a second hysteresis transistor coupled to the output. A method for testing the comparator includes: reconfiguring the comparator to be an amplifier with unity gain feedback; providing an input voltage to the input; providing a first voltage to the first hysteresis transistor to provide a first offset voltage; measuring a first output voltage at the output; removing the first voltage from the first hysteresis transistor; providing the first voltage to the second hysteresis transistor; and measuring a second output voltage at the output.

Abstract: In an A/D converter, isolation switches are used between the capacitors and the conversion switches. The conversion switches are those switches used to selectively couple the plates of the binary weighted capacitors to either Vref or 0 volts during the A/D conversion process. During sampling of the input voltage signal, the isolation switches are opened to isolate the conversion switches from the wide range of possible input voltages at the bottom plates of the capacitors. Therefore, the voltage across the conversion switches is substantially limited to Vref. Hence, the conversion switches can be very fast low voltage switches. After sampling of the input voltage, when the sampled input voltage is locked in, the conversion switches operate normally to selectively connect the capacitor plates to either Vref or 0 volts for successively approximating the input voltage, whereby a digital code representing the sampled input voltage is generated.

Abstract: Systems (400, 500, 600) and methods (300) for generating a chaotic amplitude modulated signal absent of cyclostationary features by preserving a constant variance. The methods involve: generating a PAM signal including pulse amplitude modulation having a periodically changing amplitude; generating a first part of a constant power envelope signal (FPCPES) by dividing the PAM signal by a square root of a magnitude of the PAM signal; generating a second part of the constant power envelope signal (SPCPES) having a magnitude equal to a square root of one minus the magnitude of the PAM signal; and generating first and second spreading sequences (FSS and SSS). The methods also involve combining the FPCPES with the FSS to generate a first product signal (FPS) and combining the SPCPES with the SSS to generate a second product signal (SPS). A constant power envelope signal is generated using the FPS and SPS.

Abstract: When a transmission signal is detected as having been changed from a high level to a low level, two transmission lines are connected for only a predetermined time through a diode by a first transistor and a second transistor. The diode is arranged such that its forward direction is from a high-side transmission line to a low-side transmission line. The diode turns on, when a potential of the high-side transmission line becomes higher than that of the low-side transmission line by ringing and a potential difference therebetween exceeds a forward drop voltage of the diode. As a result, a peak wave level of a positive side in the ringing is limited to the forward drop voltage of the diode.