With Sensing Amplifier Patents (Class 327/51)
  • Patent number: 7583107
    Abstract: A sense amplifier circuit for low voltage applications is provided. In one implementation, the sense amplifier circuit includes a reference current generation circuit coupled to a power supply. The reference current generation circuit generates a reference current that varies linearly with respect to changes in voltages of the power supply. The sense amplifier circuit further includes a sensing circuit coupled to the reference current generation circuit. The sensing circuit senses an amplitude of a current based at least on part on the reference current.
    Type: Grant
    Filed: September 27, 2006
    Date of Patent: September 1, 2009
    Assignee: Atmel Corporation
    Inventors: Jerome Pratlong, Marc Merandat, Stephane Ricard, Sylvie Bruneau Vergnes, Laureline Bour
  • Patent number: 7570082
    Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: August 4, 2009
    Assignee: International Business Machines Corporation
    Inventors: Fadi H. Gebara, Jeremy D. Schaub
  • Patent number: 7564271
    Abstract: A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: July 21, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
  • Patent number: 7564295
    Abstract: The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 21, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yao Ker, Shine Chung, Fu-Lung Hsueh
  • Patent number: 7554867
    Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: June 30, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Hugh P. McAdams
  • Publication number: 20090160490
    Abstract: A reference voltage generator, which is used in an analog-to-digital converter, minimizes influence of kickback noise by dividing a full scale reference voltage into a number of reference voltages using a ladder resistor unit, and applying the number of reference voltages to a number of comparators, and matches a reference common mode voltage to an input common mode voltage by forming a common feedback loop using another ladder resistor unit which is a replica of the ladder resistor unit. Therefore, since kickback noise is locally discharged by a decoupling capacitor connected to each ladder resistor and a peak value of the kickback noise is also reduced, it is possible to optimize the ladder resistor unit according to power consumption. Also, since the common feedback loop is formed as a replica of the ladder resistor unit, it is possible to match a reference common mode signal to an input common mode signal.
    Type: Application
    Filed: June 12, 2008
    Publication date: June 25, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Michael CHOI, Jung-ho LEE, Jung-eun LEE
  • Patent number: 7545685
    Abstract: A high-voltage switch circuit includes an enable control circuit, a feedback circuit, a boosting circuit, and a high voltage switch. The enable control circuit precharges an output node to a set voltage in response to an enable signal. The feedback circuit supplies a feedback voltage to an input node in response to a switch control voltage generated from the output node when the output node is precharged. The boosting circuit boosts the feedback voltage and outputs a boosting voltage to the output node, in response to clock signals, thereby increasing the switch control voltage. The high voltage switch is turned on or off in response to the switch control voltage, and is turned on to receive a high voltage and output the received high voltage. The boosting circuit includes an amplification circuit of a cross-coupled type.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 9, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok Joo Lee
  • Patent number: 7538584
    Abstract: The present invention provides a sense amplifier including a current sense circuit that outputs a detection voltage corresponding to an electric current intended for comparison, a current sense circuit that outputs a reference voltage corresponding to an electric current for reference, and a comparison circuit that compares the detection voltage and the reference voltage and outputs the result of comparison thereby. In the sense amplifier, the current sense circuit is operated in accordance with a chip control signal, and the current sense circuit is operated by a delay chip control signal obtained by delaying the chip control signal by a predetermined time by means of a delay circuit. Thus, since the current sense circuit outputs a predetermined reference voltage when the operation of the current sense circuit is started, the detection voltage rapidly converges on a predetermined level without performing such a feedback operation as to repeat its abrupt rise and fall.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: May 26, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Nobuhiro Kai
  • Patent number: 7536153
    Abstract: With a capacitor C inserted in an interstage portion of multiple stages of amplifier circuits, a high pass filter is generated by the capacitor C and an input impedance |Z| of an amplifier circuit in the next stage. Accordingly, frequency components lower than a cutoff frequency fc are cut off, and therefore are not transferred to the subsequent stage. However, radio frequency components higher than or equal to a fundamental wave component determined by an envelope of a radio frequency signal intermittently transmitted can be transferred. Consequently, transfer of DC offset potentials can be cut off, and noise, such as flicker noise, having great power in a DC or near-DC zone can be effectively cut off. Thereby, the S/N ratio, detection sensitivity, and detection accuracy can be improved.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: May 19, 2009
    Assignee: Denso Corporation
    Inventors: Hisanori Uda, Hiroaki Hayashi, Yoshiyuki Kago, Yukiomi Tanaka, Kazuhiko Endo
  • Patent number: 7528633
    Abstract: A current sensing circuit and a boost converter including the current sensing circuit are disclosed. The current sensing circuit includes a switching device, a sensing transistor, and a current sensing amplifier, and senses the current flowing through the switching device. The current sensing amplifier maintains a potential of an output terminal of the switching transistor substantially equal to a potential of an output terminal of the sensing transistor based on a difference between an output current of the switching device and an output current of the sensing transistor. Accordingly, the current sensing circuit accurately senses the current flowing through the switching device.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: May 5, 2009
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Sang-Hwa Jung, Dong-Hee Kim
  • Publication number: 20090109777
    Abstract: A sense amplifier power supply circuit includes an overdriving unit configured to apply a first voltage to a sense amplifier in response to a first enable signal, a sense amplifier driving unit configured to apply a second voltage to the sense amplifier in response to a second enable signal, and a switching unit configured to selectively apply the first voltage or the second voltage to the sense amplifier in response to the first enable signal and the second enable signal.
    Type: Application
    Filed: February 14, 2008
    Publication date: April 30, 2009
    Inventor: Sang Il Park
  • Publication number: 20090103382
    Abstract: A sense amplifier for use in sensing a signal in an integrated circuit comprises an amplifier portion and an output portion. The amplifier portion comprises a gated diode having a gate terminal. The output portion comprises an output transistor in signal communication with the gate terminal of the gated diode and having a source terminal. A variable source voltage acts on the source terminal of the output transistor when the sense amplifier is in operation. The variable source voltage is temporarily altered when the sense amplifier is actively sensing the signal in the integrated circuit.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 23, 2009
    Inventors: Wing Kin Luk, Robert Heath Dennard
  • Patent number: 7521973
    Abstract: A method for detecting which of two clock signals is the first to arrive may include providing a sense amplifier comprising first and second nodes located on first and second legs thereof. The sense amplifier is configured such that the first and second nodes have a substantially equivalent initial voltage. The method then includes receiving first and second clock signals. The sense amplifier is configured such that the voltage of the first node increases and the voltage of the second node decreases if the first clock signal arrives before the second clock signal. Similarly, the sense amplifier is configured such that the voltage of the second node increases and the voltage of the first node decreases if the second clock signal arrives before the first clock signal. The method may further include sampling the voltage of at least one of the first and second nodes to determine which of the first and second clock signals was the first to arrive.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Theodoros E Anemikos, Michael Richard Quellette, Anthony D Polson
  • Publication number: 20090096487
    Abstract: The present invention discloses a sense amplifier control circuit which controls the sense amplifier. A sense amplifier control circuit comprises a voltage comparing unit outputting delay control signals having a value corresponding to each of divided voltages obtained by dividing a potential of a power supply voltage and a pull-up control signal generating unit outputting an overdrive control signal and a pull-up control signal by an active signal and changing an enable pulse width of the overdrive control signal in response to the delay control signals, whereby it is possible to reduce current consumption caused by unnecessary overdrive operation and prevent a potential drop of the power supply voltage and thus provide operational stability of the semiconductor memory device by providing the overdrive control signal of which the enable pulse width is controlled in response to the potential of the power supply voltage.
    Type: Application
    Filed: December 27, 2007
    Publication date: April 16, 2009
    Inventor: Sung Soo CHI
  • Patent number: 7514991
    Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: April 7, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Curt Schnarr
  • Patent number: 7514877
    Abstract: A display panel driving circuit includes an input part for amplifying an input on-off signal so as to generate a first on-off voltage signal, a voltage signal generation part for generating a second on-off voltage signal which is varied in response to variations of the first on-off voltage signal, and an output part generating a push-pull output voltage as a driving voltage so as to drive a display panel in response to the first and second on-off voltages. The display panel driving circuit further includes a controlling part for controlling the voltage signal generation part so that a difference between on and off voltages of the second on-off voltage signal is not smaller than a predetermined voltage. Therefore, the push-pull output voltage whose response speed is well balanced when the push-pull output voltage increases and decreases can be generated without increasing electric power consumption and a circuit area.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: April 7, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Akira Nakayama
  • Patent number: 7511538
    Abstract: A data input buffer in a semiconductor is capable of avoiding operation speed deterioration of the data input buffer due to the temperature condition or process characteristic. The data input buffer in a semiconductor device includes an input detecting unit for detecting logic level of input data by comparing the voltage level of the input data with a reference voltage, a current driving capability adjusting unit for adjusting current driving capability of the input detecting unit based on at least one of temperature condition and process characteristic, and a buffering unit for buffering the output signal from the input detecting unit.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 31, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee-Bok Kang, Jin-Hong Ahn
  • Patent number: 7498849
    Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: March 3, 2009
    Assignee: Spansion LLC
    Inventors: Takao Akaogi, Sameer Wadhwa, Michael Achter, Bhimachar Venkatesh
  • Patent number: 7495478
    Abstract: A comparator circuit of the present invention includes a comparator section and a current buffer circuit. In a normal mode, a standby current outputted from the comparator section is amplified by a predetermined times at the current buffer circuit. On the other hand, the standby current is not amplified in a standby mode.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: February 24, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Noboru Takeuchi, Takahiro Inoue
  • Publication number: 20090045849
    Abstract: A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated.
    Type: Application
    Filed: January 23, 2008
    Publication date: February 19, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Keun Kook Kim
  • Patent number: 7489165
    Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: February 10, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 7482843
    Abstract: The amplifier includes first and second inverters that form a flip-flop. In this flip-flop, an input of first inverter is connected to an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter. Control terminals of at least one transistors (MN1, MN2) of first and second transistor pairs (MP1, MN1 and MP2, MN2) that constitute first and second inverters, respectively, are connected to inputs of first and second inverters through first and second capacitances (C1, C2), respectively. At resetting, inputs (1, 2) and outputs (OUT, OUTB) of first and second inverters are not mutually cross-connected, wherein a reference signal (VR) is supplied in common to inputs (1, 2) of the first and second inverters. The one transistors (MN1, MN2) are diode-connected. Voltage differences between reference signal (VR) and respective control terminals of the one transistors are stored in the first and second capacitances (C1, C2), respectively.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: January 27, 2009
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Hiroshi Tsuchi, Osamu Ishibashi
  • Publication number: 20080279026
    Abstract: A signal sensing circuit and a semiconductor memory device using the same are provided. The signal sensing circuit comprises a sense amplifier, a kick transistor, a first control transistor, a second control transistor, a pre-charge circuit, and a recovery circuit. The kick transistor is used to pull up the operation voltage of the sense amplifier to improve the small signal sensing speed of the sense amplifier. After the signal is sensed, the recovery circuit will pull down the operation voltage of the sense amplifier to the standard level. In the present invention, the small signal sensing speed is greatly improved and the operation voltage of sense amplifier is kept away from the saturated level.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Inventors: Chun Shiah, Chun-Peng Wu, Cheng-Nan Chang
  • Patent number: 7449922
    Abstract: Sensing circuitry and a method of operating such sensing circuitry are provided. The sensing circuitry has voltage change detection circuitry for detecting a change in voltage on at least one input line and for producing at least one output signal indicative of that change during a sensing stage of operation. The voltage change detection circuitry comprises at least one latch transistor having a body region insulated from a substrate. Further, body biasing circuitry is provided which, prior to the sensing stage of operation, causes a voltage to be applied to the body region that is derived from the voltage on one of said at least one input lines. Then, during the sensing stage of operation, the body biasing circuitry causes the voltage of the body region to float. Such an arrangement enables removal of the history effect that can sometime affect such latch transistors, whilst alleviating power consumption and noise issues that can occur in certain known sensing circuits.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: November 11, 2008
    Assignee: ARM Limited
    Inventor: Sebastien Nicolas Ricavy
  • Patent number: 7432743
    Abstract: The present invention provides a semiconductor design technology, in particular a data input buffer for use therein. This data input buffer secures a data level sensing margin in a weak data transmission cycle upon an asymmetrical data pattern transmission. Specifically, the present invention provides a technology of improving a level sensing margin in a weak data transmission cycle following after adjusting a reference level for input sensing by a constant level toward a strong data direction in a strong data transmission cycle (in case of repeating data with same polarity) by tracing a pattern of transmission data. Further, the present invention employs a method of adjusting an amount of current that flows in a data input part and a reference voltage input part to make a pull-up/pull-down of the reference level without a change of the reference voltage that is constant voltage.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: October 7, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hee-Bok Kang, Jin-Hong Ahn
  • Patent number: 7417472
    Abstract: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and readout. Each channel produces a self-trigger and a fast timing output. Channel-to-channel time differences are also recorded. Integrated circuit also provides a large dynamic range to facilitate large range of applications. The trigger threshold can be adjusted to provide energy discrimination. The chip has different, externally selectable, operational modes including a sparse readout mode in which only the channels which have received signals greater than a preselected threshold value are read out. The sparse readout mode results in increased data throughput, thus providing fast data acquisition capabilities.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: August 26, 2008
    Assignee: Nova R&D, Inc.
    Inventors: Tümay O. Tümer, Gerard Visser
  • Patent number: 7411420
    Abstract: An input integrating circuit and a differential amplifier circuit are provided in a receiver circuit which samples a pair of differential input signals, detects the levels of said pair of input signals, and latches the detected levels. The above-mentioned input integrating circuit further includes: a pair of input transistors receiving the pair of input signals at respective gates thereof; a switch transistor becoming conducting in response to a sampling clock in a sampling period so as to supply a discharge current to a common source terminal of the pair of input transistors; and a precharge circuit precharging drain terminals of the pair of input transistors in a precharge period. The input integrating circuit discharges the capacitor of the drain terminals by the discharge current in the sampling period succeeding the precharge period. The differential amplifier circuit amplifies the drain terminals of the input integrating circuit.
    Type: Grant
    Filed: February 4, 2004
    Date of Patent: August 12, 2008
    Assignee: Fujitsu Limited
    Inventor: Yoshiyasu Doi
  • Publication number: 20080181024
    Abstract: A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may increase because of the use of P and Nsense amplifiers having low threshold voltages (Vth) for low Vcc sensing of data signals. A clamping device or diode is used between a Psense amplifier control line (e.g. ACT) and Vcc and/or between an Nsense amplifier control line (e.g. RNL*) and Vss (ground potential). The clamping diode is not enabled during normal memory operations, but is turned on during active power down mode to reduce leakage current through ACT and/or RNL* nodes. The clamping device connected to the ACT node may reduce the voltage on the ACT line during power down mode, whereas the clamping device connected to the RNL* node may increase the voltage on the RNL* line during power down mode to reduce sense amplifier leakage current through these nodes.
    Type: Application
    Filed: March 28, 2008
    Publication date: July 31, 2008
    Inventor: Tae Kim
  • Patent number: 7405987
    Abstract: A low voltage, high-gain current/voltage sense amplifier (ISA/VSA) circuit with improved read access time is provided herein. According to one embodiment, the ISA/VSA described herein includes a pair of current reference branches for generating a pair of reference currents in response to a pair of differential input signals supplied thereto. The differential input signals are differential voltages which are converted to differential currents by the current reference branches. In some cases, the current reference branches may be used for amplifying and mirroring the reference currents onto output nodes of the ISA/VSA. In doing so, the current reference branches may increase the amplification and improve the performance of the sense amp circuit, even under extreme mismatch conditions. In addition, positive feedback may be used within the ISA/VSA design to further increase the amplification and speed of the sense operation.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: July 29, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventor: Gary P. Moscaluk
  • Publication number: 20080169843
    Abstract: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.
    Type: Application
    Filed: October 16, 2007
    Publication date: July 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Gus Aipperspach, David Howard Allen, Louis Bernard Bushard, Phil Christopher Felice Paone, Gregory John Uhlmann
  • Patent number: 7394295
    Abstract: The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the first current; a second current mirror unit coupled to a high voltage source, outputting a third current according to a second reference current; a first impedor coupled to the second current and a low voltage source; a second impedor coupled to the third current and a low voltage source; a third current mirror coupled to the first, second and third currents, and the first current is regarded as the reference current of the third current mirror unit, thus, the current which flows through the first impedor is the first current, and the current which flows through the second impedor is a fourth current.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: July 1, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Pao Chang, Chin-Sheng Lin, Keng-Li Su
  • Patent number: 7388409
    Abstract: An offset current independent sense circuit is switchable between a store state and a sense state. In the store state, the sense circuit stores an offset current to a capacitor, and the influence of the offset current is eliminated by a transistor to regenerate the offset current based on a signal provided by the capacitor in the sense state.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: June 17, 2008
    Assignee: Richtek Technology Corp.
    Inventor: Chung-Lung Pai
  • Publication number: 20080106304
    Abstract: An amplifier circuit includes: an amplification transistor, which is connected to an input node and an output node, amplifying an input signal and generating an output signal; and a load connected between the output node and a predetermined power supply node, wherein the amplification transistor is a vertical bipolar junction transistor. A variable gain amplifier circuit includes: a voltage converter converting a control voltage and outputting a converted control voltage; and an amplification transistor receiving the converted control signal from the voltage converter and amplifying an input signal to output an output signal whose gain is proportional to the control voltage, wherein the amplification transistor is a vertical bipolar junction transistor.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 8, 2008
    Inventors: Hyun-Won Mun, Il-Ku Nam
  • Patent number: 7368955
    Abstract: In accordance with some embodiments, a current-balanced logic circuit includes a first sense amplifier, a second sense amplifier, and a current-source transistor which provides bias current to the first and second sense amplifiers. The first and second sense amplifiers are alternately activated by first and second differential clock signals, and when activated convert data received on differential input lines into logical values for storage in respective storage circuits. The storage circuits may be flip-flops, latches, keeper circuits, or other circuits for storing data.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventors: Kursad Kiziloglu, Michael W. Altmann
  • Publication number: 20080068045
    Abstract: A semiconductor integrated circuit includes one or more voltage drop detection circuits located at one or more measurement points within the integrated circuit to detect drops in the power supply potential at those points. The voltage drop detection circuits output signals indicating whether the power supply potential is within tolerance, or whether the power supply potential has fallen and corrective action is required. Being located near the measurement points, the voltage drop detection circuits can measure the power supply potential without being disturbed by electrical noise elsewhere in the semiconductor integrated circuit. The signals output by the voltage detection circuits can be reliably brought to external terminals despite the presence of such noise, because the output signals are bi-level signals.
    Type: Application
    Filed: July 20, 2007
    Publication date: March 20, 2008
    Inventor: Yasuhiro Tokunaga
  • Publication number: 20080061840
    Abstract: A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.
    Type: Application
    Filed: July 6, 2007
    Publication date: March 13, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Tae Jin Hwang, Kun Woo Park, Yong Ju Kim, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Hyung Soo Kim
  • Publication number: 20080048727
    Abstract: A sense amplifier-based latch is provided. It comprises an input circuit, a sense amplifier, a latch circuit and an output circuit. By employing the latch circuit, the variation frequency of an output signal and a complementary output signal as well as lots of charge consumption is reduced. Accordingly, the invention has less glitches and malfunctions, thus suitable for high-speed circuit applications.
    Type: Application
    Filed: June 13, 2007
    Publication date: February 28, 2008
    Inventors: Der-Min Yuan, Shih-Hsing Wang
  • Publication number: 20080048728
    Abstract: In an embodiment, a sense amplifier can perform a stable differential amplifying operation while having a high differential amplification gain. The sense amplifier comprises a current sense amplification unit, a voltage difference amplification unit, and an output stabilization unit. The current sense amplification unit receives differential input currents and generates differential output voltages corresponding to the differential input currents. The voltage difference amplification unit amplifies a voltage level difference between the differential output voltages through positive feedback using cross-coupled transistors. The output stabilization unit connects output stabilizing elements having a positive input resistance in parallel with the voltage difference amplification unit having a negative input resistance to stabilize the output of the voltage difference amplification unit.
    Type: Application
    Filed: August 27, 2007
    Publication date: February 28, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Pyo HONG, Jun-Hee LIM
  • Patent number: 7327184
    Abstract: A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input transistors, and a current source controller, where M is an integer greater than 3. The load unit is electrically connected to an output terminal, and the first and second current sources respectively supply a first amount of current and a second amount of current to the load unit. The pair of first input transistors electrically connects the first current source and the load unit in response to a first bit signal, and the pair of the second input transistors electrically connects the second current source and the load unit in response to a second bit signal. The current source controller activates or deactivates one of the first and second current sources in response to the first and second bit signals.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: February 5, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyuk Sung, Chi-Won Kim
  • Patent number: 7312641
    Abstract: A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: December 25, 2007
    Assignee: Spansion LLC
    Inventors: Takao Akaogi, Sameer Wadhwa, Michael Achter, Bhimachar Venkatesh
  • Patent number: 7307867
    Abstract: An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL? to further enlarge the voltage difference therebetween after having raised the plate-line/bit-line voltage using the plate-line/bit-line driven method.
    Type: Grant
    Filed: November 9, 2005
    Date of Patent: December 11, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Chin-Hsi Lin, Chi-Ming Weng
  • Patent number: 7298660
    Abstract: A bit line sense amplifier control circuit includes a driving signal generating unit adapted and configured to generate first through third driving signals in response to a bit line sense amplifier enable signal and an overdrive enable signal for setting an overdrive period, and to disable a first driving signal which is enabled for an overdrive period in response to a refresh signal which is enabled at a refresh mode, and a bit line sense amplifier control signal generating unit adapted and configured to generate first and second bit line sense amplifier control signals in response to the first through third driving signals. As a result, an overdrive pulse is not generated at a refresh mode to remove an overdriving period, thereby reducing current consumption at a refresh mode.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 20, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hee Jin Byun
  • Patent number: 7279939
    Abstract: Returning to FIG. 2, sense circuit 201 represents the circuit that must sense the signaling on an interconnect. NMOS device 202 is always on so that there is a continuous path to ground whenever PMOS driver 204 is on. Since leakage power is an order of magnitude less than static and dynamic power it can be omitted for clarity, although it should be noted that dynamic power increases with respect to line length since the interconnect capacitance increases as line length increases. Static power is due to flow of static current across the two resistances shown in FIG. 2, interconnect resistance 206 and the resistance of transistors 102 and 104 from FIG. 1, represented by the resistance of equivalent NMOS transistor 208 of FIG. 2.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: October 9, 2007
    Assignee: University of Massachusetts
    Inventors: Wayne Burleson, Vishak Venkotroman, Atul Maheshwari
  • Patent number: 7274220
    Abstract: A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Dean D. Gans
  • Patent number: 7274219
    Abstract: An offset current independent sense circuit is switchable between a store state and a sense state. In the store state, the sense circuit stores an offset current to a capacitor, and the influence of the offset current is eliminated by a transistor to regenerate the offset current based on a signal provided by the capacitor in the sense state.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 25, 2007
    Assignee: Richtek Technology Corp.
    Inventor: Chung-Lung Pai
  • Publication number: 20070205807
    Abstract: The amplifier includes first and second inverters that form a flip-flop. In this flip-flop, an input of first inverter is connected to an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter. Control terminals of at least one transistors (MN1, MN2) of first and second transistor pairs (MP1, MN1 and MP2, MN2) that constitute first and second inverters, respectively, are connected to inputs of first and second inverters through first and second capacitances (C1, C2), respectively. At resetting, inputs (1, 2) and outputs (OUT, OUTB) of first and second inverters are not mutually cross-connected, wherein a reference signal (VR) is supplied in common to inputs (1, 2) of the first and second inverters. The one transistors (MN1, MN2) are diode-connected. Voltage differences between reference signal (VR) and respective control terminals of the one transistors are stored in the first and second capacitances (C1, C2), respectively.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Hiroshi Tsuchi, Osamu Ishibashi
  • Publication number: 20070205808
    Abstract: The present invention provides a sense amplifier including a current sense circuit that outputs a detection voltage corresponding to an electric current intended for comparison, a current sense circuit that outputs a reference voltage corresponding to an electric current for reference, and a comparison circuit that compares the detection voltage and the reference voltage and outputs the result of comparison thereby. In the sense amplifier, the current sense circuit is operated in accordance with a chip control signal, and the current sense circuit is operated by a delay chip control signal obtained by delaying the chip control signal by a predetermined time by means of a delay circuit. Thus, since the current sense circuit outputs a predetermined reference voltage when the operation of the current sense circuit is started, the detection voltage rapidly converges on a predetermined level without performing such a feedback operation as to repeat its abrupt rise and fall.
    Type: Application
    Filed: March 1, 2007
    Publication date: September 6, 2007
    Inventor: Nobuhiro Kai
  • Publication number: 20070182458
    Abstract: A sense amplifier flip flop comprises a pre-charging portion connected between a first power voltage and first and second nodes and pre-charging the first and second nodes to a predetermined voltage in response to a clock signal, a differential input portion connected between a second power voltage and third and fourth nodes and receiving an input signal and an inverted input signal to generate a voltage difference between the input signal and the inverted input signal to the third and fourth nodes in response to the clock signal, a differential amplifying portion including a first inverter which includes a first pull-up transistor and a first pull-down transistor serial-connected between the first power voltage and the third node and inverts a signal of the second node to be outputted to the first node and a second inverter which includes a second pull-up transistor and a second pull-down transistor serial-connected between the first power voltage and the fourth node and inverts a signal of the first node to
    Type: Application
    Filed: October 23, 2006
    Publication date: August 9, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min-Ho PARK, Young-Soo SOHN
  • Patent number: 7242629
    Abstract: A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Wing K. Luk, Leland Chang, Robert H. Dennard, Robert Montoye
  • Patent number: 7230868
    Abstract: An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: June 12, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sudhir K. Madan, Bryan Sheffield