Abstract: According to an example embodiment, an apparatus for controlling a power supply voltage for an integrated circuit may be provided, which may include a plurality of different types of process region detection circuits, each process region detection circuit configured to identify a respective process region of a plurality of process regions. The apparatus may also include a voltage selection circuit configured to determine a highest voltage among the voltages associated with the identified process regions and to select a power supply voltage for the integrated circuit that is equal to the highest voltage, one or more functional test circuits configured to perform a functional test using the selected power supply voltage, and a voltage adjuster circuit configured to increase the selected power supply voltage if the functional test fails.

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract: A method of buffering data from core circuitry includes generating a first sourcing control signal responsive to indication signals indicating an operating voltage and output data, generating a second sourcing control signal responsive to the indication signals, and applying the operating voltage to an output terminal in response to the first sourcing control signal and the second sourcing control signal. The first sourcing control signal swings between the operating voltage and a reference voltage. The reference voltage is a signal selected from among a plurality of internal voltages in response to selection signals generated as a result of decoding the indication signals.

Abstract: Various technologies described herein pertain to automatically adjusting the strength of a voltage booster of an image sensor. A self-scaled voltage booster includes a regulator, a controller, and two or more charge pumps that can be selectively enabled and disabled by the controller. The controller generates controller signals for the charge pumps based on a duty cycle of a regulator signal generated by the regulator. Moreover, the controller can maintain the controller signals without modification for at least a predetermined minimum period of time after a prior modification of at least one of the controller signals. Further, the controller can include a duty cycle and delay module (or a plurality of duty cycle and delay modules) that detects the duty cycle of the regulator signal and maintains the controller signals without modification for at least the predetermined minimum period of time.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: On-chip active decoupling capacitors for regulating the voltage of an integrated circuit include a reference voltage generator, a latch-based comparator and switched DECAPs. The latched-based comparator is for comparing a reference voltage generated by the reference voltage generator and a supply voltage of the integrated circuit and outputting a comparison result. The switched DECAPs includes at least two capacitors and a plurality of switches, and coupling the at least two capacitors into a parallel configuration to sink current or a series configuration to source current based on the comparison result output by the latch-based comparator. The aforementioned on-chip active decoupling capacitors not only have lower power consumption, but also larger detection range.

Abstract: In one embodiment, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region, and a transistor which is supplied with the bias current. The bias circuit includes first to third transistors, a fourth transistor through which a first current flows, a fifth transistor, a sixth transistor through which a second current flows, and a control circuit having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current. The bias circuit generates a third current by adding the first current to the second current, and outputs the bias current that is the third current or a fourth current depending on the third current.

Abstract: Embodiments relate to a metal-oxide-semiconductor device including a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes a gate configured to change electrical characteristics based on a sensed chemical characteristic and a source and drain. One of the source and drain is connected to an analysis circuit, and a backgate is connected to an AC voltage source.

Abstract: The disclosure provides a method and an apparatus for supplying power to a 300 PIN MSA 40 Gb TRANSPONDER. The apparatus comprises a power control module (31), a second resistor (R2), a third resistor (R3) and a compensation circuit. The power control module (31) comprises an output terminal (311) and a reference voltage terminal (312). The output terminal (311) supplies power to the 300 PIN MSA 40 Gb TRANSPONDER through an Adaptable Power Supply (APS) Digital pin (33) of the 300 PIN MSA 40 Gb TRANSPONDER. The reference voltage terminal (312), one terminal of the second resistor (R2), one terminal of the third resistor (R3) and one terminal of the compensation circuit are connected with each other. The other terminal of the second resistor (R2) is connected with an APS Set pin (35) of the 300 PIN MSA 40 Gb TRANSPONDER. The other terminal of the third resistor (R3) is connected with an APS Sense pin (34) of the 300 PIN MSA 40 Gb TRANSPONDER. The other terminal of the compensation circuit is grounded.

Abstract: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be provided. The first pad is for receiving an externally applied body bias voltage. Circuitry for producing a body bias voltage can be coupled to the first pad for coupling a body bias voltage to a plurality of biasing wells disposed on the integrated circuit device. If an externally applied body bias voltage is not provided, the resistive structure automatically couples a power supply voltage to the biasing wells. The power supply voltage may be obtained internally to the integrated circuit.

Abstract: An apparatus and method are disclosed to combine pad functionality in an integrated circuit. A power, ground, or signal pad is connected to a power, ground, or signal source, respectively. The power, ground, or signal pad is additionally connected to an additional signal source, such as automatic test equipment in a testing environment. By temporarily disconnecting either the power, ground, or signal source, from the functional block within the integrated circuit to which the source is delivered, the same pad may pass in another signal to other portions of the integrated circuit. In the alternative, the same pad may pass in another signal to other portions of the integrated circuit without disconnecting the original signal by coupling the additional signal over the original signal. Further, combining pad functionality enables reuse of an input pad as an output pad for signals originating from within the integrated circuit.

Abstract: To maintain linear operation of a signal processing circuit, such as a low noise amplifier, a peak detector detects a peak of a signal associated with the signal processing circuit and compares the detected peak signal with a threshold. When the detected peak signal is greater than the threshold, a variable current source biases the signal processing circuit to place the signal processing circuit in a different mode of operation. The signal processing circuit may thereby process a larger input signal while operating in an acceptable linear region.

Abstract: A high-voltage MEMS biasing network. The network has a reset mode wherein a capacitive sensor is charged, and a functional mode wherein the MEMS biasing network provides a high impedance between the capacitive sensor and a bias voltage source. The network includes a biasing circuit, a mirror circuit, and a control circuit. The biasing circuit and the mirror circuit have a charging state and a high impedance state. The control circuit includes a first branch that controls the biasing circuit and a second branch that controls the mirror circuit. The biasing network receives a logic control signal, the first branch puts the biasing circuit into the charging state when the logic control signal is a first logic signal, and puts the biasing circuit into the high impedance state when the logic control signal is a second logic signal.

Abstract: A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit and a bias calculation circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a first series of soft decision data, and to apply the data detection algorithm to a second data set to yield a second series of soft decision data. The bias calculation circuit operable to calculate a series of bias values based at least in part on the first series of soft decision data and the second series of soft decision data. The series of bias values correspond to a conversion between the first series of soft decision data and the second series of soft decision data.

Abstract: According to an embodiment, a semiconductor integrated circuit including first and second lower-layer power supply wires extending in a first direction and first and second upper-layer power supply wires extending in a second direction is provided. First and second connection wires between the upper-layer power supply wires and the lower-layer power supply wires are arranged in a same line along the second direction. First and second position converting wires extending from the connection wires are arranged between the first and second connection wires. First and second upper-side vias provided on the position converting wires are arranged in a same line along the first direction.

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract: The present invention is to provide a graphene valley singlet-triplet qubit device. The device includes a substrate, and a graphene layer formed on the substrate. An energy gap is created between the valence band and the conduction band of the graphene layer. At least one electrical gate is configured on the graphene layer and/or on two sides of the graphene layer. The graphene layer is located in a magnetic field and a voltage is applied to at least one electrical gate, thereby creating a valley singlet-triplet qubit.

Abstract: A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.

Abstract: Provided are a voltage divider circuit with high detection precision, a small circuit area, and a reduced chip size, and a semiconductor device including the voltage divider circuit. The voltage divider circuit includes: a first resistor circuit formed to have a resistance that is weighted according to a binary code; a second resistor circuit formed to have a resistance that is weighted according to the same binary code; and a third resistor circuit including a third resistor having a resistance that is weighted according to the same binary code to have a maximum weighted bit count, in which both ends of the third resistor are alternatively connected to an output terminal by two transmission gates.

Abstract: A microelectronic package includes a microelectronic element operable to output a discrete-value logic signal indicating an imminent increase in demand for current by at least some portion of the microelectronic element. An active power delivery element within the package is operable by the logic signal to increase current delivery to the microelectronic element.

Abstract: A current sensing circuit arrangement is disclosed. The circuit arrangement includes a load transistor for controlling a load current to a load being coupled to a drain electrode of the load transistor. A sense transistor is coupled to the load transistor. The sense transistor has a drain electrode that provides a measurement current representative of the load current. The load transistor and the sense transistor are field effect transistors having a common source electrode. A measurement circuit is configured to receive the measurement current from the sense transistor and to generate an output signal therefrom, the output signal being representative of the load current.

Abstract: A power supply control circuit comprises an output transistor which controls supply of electric power to a load and a gate driving circuit which generates control signals “a” and “b” for controlling on/off of the output transistor 32 based on an external input signal. A transistor 37 discharges a gate charge of the output transistor based on the control signals “a” and “b”, when turning off the output transistor. A transistor 39 discharges more slowly than the transistor. A diode is coupled to the transistor 37 in series and which cuts off a discharge path through the transistor 37 transistor and the diode when the gate voltage of the output transistor falls to a voltage level higher than the sum of the power supply voltage Vcc and a threshold voltage of the output transistor, at a time of turning off the output transistor.

Abstract: The present invention is a semiconductor integrated circuit device including a target circuit, a voltage supply circuit that supplies the power supply voltage to the target circuit, a control circuit that controls an output voltage of the voltage supply circuit, and a target voltage prediction circuit that predicts a voltage value of the power supply voltage. The control circuit changes the output voltage of the voltage supply circuit by a predetermined voltage value. The target voltage prediction circuit detects a change amount of an operating frequency of the target circuit along with the change of the predetermined voltage value, and calculates a target voltage value based on a relation between the change amount of the operating frequency and the predetermined voltage value. The voltage supply circuit supplies a power supply voltage corresponding to the target voltage value to the target circuit.

Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.

Abstract: According to one embodiment, a semiconductor device provided with an input terminal and a resistor circuit is presented. The resistor circuit is provided with first and second transistors, a first resistor, a capacitor and a capacitor. A drain of the first transistor is connected to the input terminal. One end of the first resistor is connected to a gate of the first transistor. A drain of the second transistor is connected to a source of the first transistor. A gate of the second transistor is connected to the other end of the first resistor. A source of the second transistor is connected to a power supply of a source side. The capacitor is connected between the drain and the gate of the first transistor. The voltage supply circuit is connected to the other end of the first resistor and the gate of the second transistor.

Abstract: Provided is an analog digital converting device which consumes a low power and guarantees fast operation characteristic. The analog digital converting device includes a sub-ADC and a successive approximation ADC. The sub-ADC converts an external analog signal into a first digital signal by using first and second reference voltages. The successive approximation ADC comprises a plurality of bit streams, and converts the external analog signal into a second digital signal according to a successive approximation operation using the first and second reference voltages. The successive approximation ADC receives the first digital signal, and converts the second digital signal in a state where one of the first and second reference voltages has been applied to the bit streams based on the first digital signal.

Abstract: Embodiments relate to a method including receiving a voltage potential at a gate of a first MOSFET based on a sensed chemical characteristic. The method includes receiving at a backgate of the first MOSFET an AC voltage signal and analyzing, with an analysis circuit connected to one of a first source and a first drain of the MOSFET, the sensed characteristic based on the receiving the voltage potential at the gate of the first MOSFET.

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract: A power disconnect unit within a data transport topology of a NoC includes an asynchronous clock domain adapter unit inserted between a master side manager unit and a slave side manager unit. This configuration allows for the master and slave side managers of the power disconnect unit to be placed physically far apart on the chip, relieving the need to route long power rail signals on the chip. A response data path and associated asynchronous clock domain adapter unit is optionally included on the chip. A path to bypass the asynchronous clock domain adapter units is optionally included on the chip to enable a fully synchronous mode of operation without the data latency cost of the asynchronous adapter unit.

Abstract: A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.

Abstract: An internal voltage generating circuit includes a divided voltage generator configured to generate a divided voltage by dividing a feedback internal voltage level at a division ratio corresponding to an operation mode control signal, a voltage detector configured to detect a level of the divided voltage based on a reference voltage level, an internal voltage generator configured to receive a supply voltage as power source and generate the internal voltage in response to an output signal of the voltage detector, and an under-driving unit configured to under-drive an internal voltage terminal to a supply voltage in an under-driving operation region that is determined in response to the operation mode control signal.

Abstract: A circuit for generating a reference voltage includes a first reference voltage generating circuit disposed outside a chip and a second reference voltage generating circuit disposed inside the chip. The first and second reference voltage generating circuits output first and second reference voltages to first and second output terminals, respectively. The second reference voltage generating circuit includes at least one pull-up resistor and at least one pull-down resistor. The pull-up resistor is coupled between a first node where an internal power supply voltage is coupled and the second output terminal. The pull-down resistor is coupled between a second node and the second output terminal, wherein a voltage at the second node is relatively lower than a voltage at the first node. A third reference voltage is outputted from a node where the first output terminal is coupled to the second output terminal.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: A semiconductor device includes a semiconductor substrate having at least a pn-junction arranged in the semiconductor substrate. At least a field electrode is arranged at least next to a portion of the pn-junction, wherein the field electrode is insulated from the semiconductor substrate. A switching device is electrically connected to the field electrode and adapted to apply selectively and dynamically one of a first electrical potential and a second electrical potential, which is different to the first electrical potential, to the field electrode to alter the avalanche breakdown characteristics of the pn-junction.

Abstract: An electronic apparatus for providing supply voltage to a first external device with a predetermined pin assignment specification is provided. The electronic apparatus includes a connection interface and a voltage supplier. The connection interface includes a first pin and a second pin. The voltage supplier provides a detection voltage signal to the first pin and determines whether to provide the supply voltage according to whether the second pin is at a first level in response to the detection voltage signal. When the second pin is at the first level in response to the detection voltage signal, the voltage supplier provides the supply voltage to the first pin.

Abstract: Embodiments of a method, apparatus and circuit for voltage regulation are disclosed. One embodiment of a circuit includes a first field effect transistor (FET) having a gate, a drain and a source. A current source is connected to the drain of the FET. A second FET has a source connected to the source of the first FET by a node. The second FET also has a gate. A low-pass filter circuit has an input connected to the gate of the first FET and an output connected to the gate of the second FET.

Abstract: Dynamic biasing methods and circuits are described. The described methods generate bias voltages that are continuously varied so as to control stress voltages across transistors used within a cascode stack.

Abstract: Active sensor for switching over into a special operating mode, wherein the sensor has at least one sensor element, one evaluation circuit and two connecting lines, each with a terminal for transmitting the sensor information, wherein a supply voltage of the sensor is applied to the two connecting lines, wherein the sensor comprises a switchover module with which it is possible to switch over between a normal operating mode and a special operating mode by reversing the polarity of the supply voltage which is applied to the two terminals. A method for actuating an active sensor and to the use of the sensor, in particular as a wheel speed sensor, in motor vehicles.

Abstract: A semiconductor apparatus comprises a power-up signal generation section configured to generate a power-up signal, a driver configured to drive and output the power-up signal, and a main circuit block configured to perform predetermined functions in response to an output from the driver, wherein the power-up signal generation section and an input terminal of the driver are connected by a disconnectable element.

Abstract: A capacitive voltage divider arrangement comprising a first and second voltage divider, a first and second parasitic capacitance being formed between the first and second capacitive voltage divider. The first capacitive voltage divider comprises a signal terminal; a first capacitance for coupling the terminal to a reference potential; a second capacitance; a third capacitance that may be coupled to the reference potential, the second capacitance being coupled in between the terminal and third capacitance.

Abstract: A bias circuit according to the present invention includes: a transistor for supplying a bias current from the emitter of the transistor; an emitter potential generating device for supplying a potential to the emitter of the transistor; a switch element; and a voltage supply circuit for supplying a base voltage to the base of the transistor in response to the on/off of the switch element, wherein the emitter potential generating device generates a potential causing a potential difference between the base and emitter of the transistor to fall below a saturation voltage at the junction of the transistor, even in the case where the base of the transistor is fed with a voltage not lower the saturation voltage at the junction of the transistor.

Abstract: To provide a fast charge means for a capacitor in a negative bias generation circuit. A capacitor is present in a down converter in a negative bias generation circuit. In order to perform fast charge, the capacitance of the capacitor is reduced and a necessary amount of charge is minimized. On the other hand, an external capacitance provided separately from the capacitor in the down converter is coupled directly to a power supply voltage and charged. After the capacitor in the down converter is charged, the external capacitance and the capacitor in the down converter are coupled in parallel. Due to this, it is made possible to aim at both the increase in charge speed and the improvement of resistance to ripple noise.

Abstract: As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

Abstract: The present invention provides a reference power supply circuit which does not require trimming and prevents occurrence of deadlock of a band gap reference circuit. An RFID tag chip related to the present invention has a reference power supply including a switch for switching between a band gap reference circuit and a Vth difference reference circuit. A reference potential in band gap reference of the band gap reference circuit and an output of the Vth difference reference circuit are compared by a comparator, and a transistor operating as a switch is controlled, thereby making the reference potential in band gap reference rise, hastening startup of the band gap reference circuit, and preventing occurrence of deadlock in the band gap reference circuit.

Abstract: A register circuit is provided which can hold data even after being powered off and which does not require a save operation and a return operation. In a register circuit including a plurality of register component circuits, a first transistor with small off-state current, and a second transistor with small off-state current, a data holding portion is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. Since the first transistor and the second transistor have a small off-state current, electric charge does not leak from the data holding portion, and data is held by the data holding portion even after the register circuit is powered off. Thus, a save operation and a return operation are not required.

Abstract: Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.

Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

Abstract: A circuit includes a switching unit, a switching element, and a control unit. The control unit provides at least one supply signal depending on a switching position of the switching element. An advance signal and the supply signal(s) of the control unit are assigned to the switching unit on the input side. The switching unit supplies and controls predetermined components of the switching unit, which are configured to control the switching element in accordance with the advance signal in such a way that the components activate the switching element. The switching unit is also configured to detect the supply signal(s) present once the switching element has been activated and in response thereto to switch to supplying the predetermined components by way of the supply signal(s).

Abstract: A radiation-hardened charge pump circuit is provided. The circuit includes a first charge pump having a first charge pump output, a second charge pump having a second charge pump output, a first coincidence detector receiving as inputs the first charge pump output and the second charge pump output and producing as an output a first coincidence signal, and an analog 2:1 multiplexor for selecting either the first charge pump output or the second charge pump output based on the first coincidence signal. In alternative embodiment, the circuit includes at least three charge pumps, at least two coincidence detectors, decision logic, and a correspondingly-sized analog multiplexor.