Abstract: A four-phase charge pump circuit provided includes multiple boosting stages. Each boosting stage includes two branch charge pumps. Each branch charge pump includes a main pass transistor and a pre-charge transistor. Two ends of the main pass transistor serve as a first node and a second node of the branch charge pump respectively. A first end, a second end and a control end of the pre-charge transistor are coupled to a control end of the main pass transistor, a second node and a first node of the branch charge pump respectively. At least one boosting stage further includes two auxiliary start-up transistors. Two ends of each auxiliary start-up transistor are coupled to the control end of one main pass transistor and the second node of the branch charge pump respectively. A control end of each auxiliary start-up transistor is coupled to the control end of one main pass transistor.

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source 10, as a second power supply voltage VDD to a first circuit 13, and a second switch SW1 which switches whether or not to connect to the first circuit 13 a smoothing capacitor C1 which suppresses a fluctuation of the second power supply voltage VDD, and the first switch SWx is switched to an on state in response to that the first power supply voltage Vx has reached a sufficient voltage, and then the second switch SW1 is switched to the on state in response to that the second power supply voltage VDD has reached a sufficient voltage.

Abstract: A memory device in which data can be retained for a long time is provided. The memory device includes a memory element and a transistor which functions as a switching element for controlling supply, storage, and release of electrical charge in the memory element. The transistor includes a second gate electrode for controlling the threshold voltage in addition to a normal gate electrode. Further, the off-state current of the transistor is extremely low because an active layer thereof includes an oxide semiconductor. In the memory device, data is stored not by injection of electrical charge to a floating gate surrounded by an insulating film at high voltage but by control of the amount of electrical charge of the memory element through the transistor whose off-state current is extremely low.

Abstract: A charge pump apparatus is provided. A two-phase clock signal and a four-phase clock signal for respectively driving a two-phase charge pump circuit and a four-phase charge pump circuit are generated according to delay signals of coupling nodes between delay circuits of a ring oscillator circuit.

Abstract: In accordance with an embodiment, a method of testing an integrated circuit, includes receiving a supply voltage on the integrated circuit via a first input pin, providing power to circuits disposed on the integrated circuit via the first input pin, comparing the supply voltage to an internally generated voltage, generating a digital output value based on the comparing, and applying the digital output value to a pin of the integrated circuit.

Abstract: A switch circuit package module includes a semiconductor switch unit and a capacitor unit. The semiconductor switch unit includes a first semiconductor switch element and a second semiconductor switch element. The first semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The second semiconductor switch element includes sub micro-switch elements, each sub micro-switch element configured with a drain electrode and a source electrode. The capacitor unit includes a plurality of capacitors.

Abstract: A charge pumping apparatus in accordance with an embodiment may include a charge pump output voltage detector, a pump oscillator, and a charge pump switching controller. The charge pump output voltage detector may detect a charge pump output voltage, and may selectively output an enable signal according to the detected charge pump output voltage. The pump oscillator may output an oscillation signal during a period of time when the enable signal is activated. The charge pump switching controller may selectively operate one of a first pump and a second pump according to a predetermined stabilization time, the enable signal, and the oscillation signal.

Abstract: An apparatus for converting voltage includes terminals coupled to external circuits at corresponding voltages and a switching network having driving circuits and semiconductor switches that interconnect capacitors in successive states to one another and to the terminals. The switches interconnect some capacitors to one another through a series of switches when an activation pattern causes them to be activated. Each driving circuit has power connections, a control input, and a drive output coupled to and controlling at least one switch. A drive output of one of them couples to and drives each switch. Some of the driving circuits are powered via corresponding power connections from at least one of the capacitors such that a voltage across the corresponding power connections is less than a highest of the corresponding voltages. The terminals and the switching network are constituents of a switched capacitor converter.

Abstract: A MEMS microphone with an improved sensitivity, e.g., a reduced temperature dependence of the sensitivity. The microphone includes a MEMS capacitor, a charging circuit and a bias circuit. The bias circuit includes a closed loop control circuit and creates a bias voltage with a temperature dependence.

Abstract: A power supply includes a plurality of charge pump circuits. The charge pump circuits commonly generate an output voltage for programming a write data to the memory apparatus. Wherein, number of the charge pump circuits enabled for generating the output voltage is determined according to number of programmed bit(s) of the write data.

Abstract: A charge pump circuit may include a charge pump unit suitable for performing a charge pump operation until an output voltage reaches a target voltage; and a multi-stage charge sharing unit comprising first to Nth capacitors coupled in parallel between the charge pump unit and a load circuit, the multi-stage charge sharing unit being suitable for sequentially performing first to Nth charge sharing operations between the first to Nth capacitors, respectively, and the load circuit after the charge sharing operation, wherein the first to Nth charge sharing operations are mutually and exclusively performed, and N is a natural number equal to or greater than 2.

Abstract: A boost circuit includes a power rail to provide a supply voltage, a switch transistor controlling output of a boosted signal from a source of the switch transistor, and a timing and voltage control circuit configured to generate an equalization (EQ) signal to be applied to a gate of the switch transistor. The EQ waveform has a level being an EQ high level, an EQ low level lower than the EQ high level, or an EQ clamped level between the EQ low level and the EQ high level.

Abstract: A voltage generation circuit includes: a periodic wave generator that generates an on/off signal that is periodically enabled/disabled, where at least one between a period and a duty cycle of the on/off signal is controlled based on at least one information among temperature information, capacitance information, leakage current information, speed information, and voltage level information; and an internal voltage generator that is enabled/disabled in response to the on/off signal and generates an internal voltage.

Abstract: A distributed voltage regulator has switches that function as resistors and are distributed in rows in a grid pattern across a regulated voltage domain. The switches receive an unregulated voltage and supply the regulated voltage. Switch control lines selectively enable the switches to achieve the desired voltage regulation. Droop detect circuits are also distributed through regulated voltage domain. The droop detect circuits detect when the regulated voltage is below a threshold and supply droop detect signals indicative thereof. A plurality of select circuits receive a first group of control lines to configure the switches for charge injection in response to a droop condition and a second group of control lines to configure the switches for other voltage regulation. The select circuits select one of the first and second group of control lines as switch control lines to configure the switches based on the droop detect signals.

Abstract: An electronic device includes: a clock booster configured to generate a boosted intermediate voltage greater than a source voltage, wherein the clock booster includes: a controller capacitor configured to store energy for providing a gate signal, wherein the gate signal is for controlling charging operations to generate the boosted intermediate voltage based on the source voltage, and a booster capacitor configured to store energy according to the gate signal for providing the boosted intermediate voltage, wherein the booster capacitor has greater capacitance level than the controller capacitor; and a secondary booster operatively coupled to the clock booster, the secondary booster configured to generate an output voltage based on the boosted intermediate voltage, wherein the output voltage is greater than both the source voltage and the boosted intermediate voltage.

Abstract: Cross-coupled charge-pumps. At least some of the example embodiment are methods including: pumping charge from a first capacitor through a first field effect transistor (FET) to a voltage output and from a second capacitor through a second FET to the voltage output of the charge pump; refreshing charge to a third capacitor and a fourth capacitor during the pumping of charge; electrically isolating the first through fourth capacitors during a dead time; and then pumping charge from the third capacitor through a third FET to the voltage output and from the fourth capacitor through a fourth FET to the voltage output of the charge pump; and refreshing charge to the first capacitor and the second capacitor during the pumping of charge from the third and fourth capacitors.

Abstract: A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.

Abstract: Disclosed herein is an enable signal generation circuit. The circuit includes: an enable input terminal that receives an enable input voltage; an enable detection circuit that determines whether the enable input voltage is higher than a first reference voltage, and then outputs an inverted signal; and an output section that is connected to the enable detection circuit. The enable detection circuit is formed of at least two transistors arranged in a differential configuration, gives the two transistors offset voltages that provide different operating voltages, and causes the output section to output a signal based on the inverted signal.

Abstract: A bi-directional charge pump cell includes a p-type substrate having a main surface. A first n-well is formed in the p-type substrate that includes n+ doped regions formed in the first n? well at the main surface. A first p-well is formed in the first n? well that includes p+ doped regions formed in the first p-well at the main surface. A second n-well is formed in the first p-well that includes n+ doped regions and PMOS transistors formed at the main surface. A second p-well is formed in the first n-well that includes p+ doped regions at the main surface. A third p-well is defined in the second p-well that includes p+ doped regions and NMOS transistors at the main surface.

Abstract: A charge pump and operating method thereof are disclosed. The charge pump includes a first capacitor to a third capacitor and a first switch to a tenth switch. The charge pump is used to receive an input voltage and provide an output voltage to a load capacitor. When the charge pump is operated in a first mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (?½) times the input voltage. When the charge pump is operated in a second mode, the charge pump controls the second capacitor failure, the output voltage and the input voltage have opposite electricity and the output voltage is (??) times the input voltage.

Abstract: One embodiment of the invention relates to a trainable transceiver. The trainable transceiver includes a transceiver circuit, a user input device, a battery, and a voltage regulator circuit. The transceiver circuit is configured to reproduce and transmit control signals for operating a plurality of remote electronic devices. The user input device is configured to accept user input. The voltage regulator circuit includes a DC-DC converter configured to step up the battery voltage level, a low leakage switch configured to couple the battery and the DC-DC converter, and a temperature-sensitive current source configured to control the low leakage switch. The battery is configured to power the transceiver circuit, the user input device, and the voltage regulator circuit.

Abstract: The booster precharges a boost-voltage-output terminal to a predetermined voltage before voltage-boosting start by a charge-pump circuit in the booster. While alternately switching one capacitive electrode of a pumping capacitance between first and second voltages, the charge-pump circuit periodically applies a third voltage to the other capacitive electrode, in which the voltage is boosted by lifting up the third voltage each switching. The resultant boost voltage is successively supplied to a stabilization capacitance through a MOS switch circuit for output. Thus, a boost voltage boosted to a sum voltage of the second and third voltages can be obtained. Using a precharge voltage produced by the precharge circuit in the booster as the third voltage can make a MOS switch circuit operable to supply the third voltage and the MOS switch circuit for boost voltage output smaller than a voltage under the sum voltage of the second and third voltages.

Abstract: A semiconductor device including a first internal voltage generating circuit that includes a capacitor including a first electrode and a second electrode, and the first internal voltage generating circuit to generate an internal voltage by charging the capacitor to a first voltage and applying a second voltage to the first electrode of the capacitor to generate a third voltage that is greater than the first and the second voltages on the second electrode in absolute value, and a control circuit to perform a control by applying a fourth voltage that is less than the first voltage to the capacitor when the first internal voltage generating circuit is in a standby state.

Abstract: In one example, a voltage generator includes a plurality of voltage pumps, a voltage detection circuit, an oscillator, and a control circuit. The plurality of voltage pumps are configured to perform voltage pumping operations in a sequence and output a pumping voltage. The voltage detection circuit is configured to detect a voltage level of the pumping voltage and output a detection signal. The control circuit is configured to output, in response to the detection signal, a plurality of divided oscillator signals based on an oscillator signal of the oscillator, to enable a different one of the voltage pumps to begin each sequence of voltage pumping operations each time the pumping voltage is less than a threshold voltage.

Abstract: A method of increasing a multiplication ratio of a charge pump, the multiplication ratio defining a relationship between an output voltage of the charge pump and an input voltage of the charge pump, comprising: analyzing a first efficiency of the charge pump when the multiplication ratio is at a first ratio, calculating a second efficiency of the charge pump when the multiplication ratio is a second ratio lesser than the first ratio, and based on the first efficiency and the second efficiency, determining at least one of a target output power and a target output voltage at which to change the multiplication ratio from the second ratio to the first ratio.

Abstract: Switched-capacitor charge pump implemented in FDSOI process technology and a method of forming them are provided. Embodiments include providing a FDSOI substrate; providing a plurality of stages of a first and a second pair of an NFET and PFET over the FDSOI substrate coupled between an input terminal and an output terminal, the first and second pair of each stage being opposite each other; providing a plurality of a first and a second capacitor over the FDSOI substrate, each first and second capacitor connected to a first and a second pair of NFET and PFET of a stage, respectively; connecting a back-gate of a NFET and a back-gate of a PFET of each pair; connecting the connected NFET and PFET back-gates to a front-gate of the pair; and connecting a source of each pair to a front gate of an opposite pair within the stage.

Abstract: A booster circuit includes a charge pump circuit and a clock processing circuit. The clock processing circuit includes a first transistor of a first conductivity type, a second transistor of a second conductivity type, and a third transistor of a third conductivity type. The first and second transistors are connected in series between a high-voltage node and a low-voltage node, and gates of the first and second transistors are connected to each other. The third transistor is connected in parallel with the first transistor between the high-voltage node and an output terminal of the clock processing circuit that is connected to a node between the first transistor and the second transistor and to the charge pump circuit.

Abstract: A system includes a fuse pump; a fuse that can be blown by the fuse pump; and a voltage source configured to provide a first voltage only if the fuse pump is enabled to blow the fuse, the fuse pump blowing the fuse when the first voltage serves as a supply voltage of the fuse pump. If the first voltage serves as a supply voltage of the fuse pump, a first consumed time is required to blow the fuse. If a second voltage, provided by the voltage source, were to be served as a supply voltage of the fuse pump, a second consumed time is required to blow the fuse. The first consumed time is less than the second consumed time.

Abstract: A semiconductor system includes a semiconductor device suitable for not performing an internal refresh operation when entering a self-refresh mode in response to a self-refresh command, and cutting off input of an auto-refresh command when exiting the self-refresh mode.

Abstract: An energy harvester circuit operates to harvest energy in battery-less electrical apparatus. The circuit includes a string of capacitors coupled to a circuit input to receive energy to be harvested. A string of transistors are coupled as pumping transistors to respective ones of the capacitors in the string of capacitors. A compensation coupling circuit is coupled between each transistor in the string of pumping transistors and one of a subsequent or a preceding transistor in the string of pumping transistors.

Abstract: A charge pump circuit can be controlled by a control signal that is generated from a first signal coming from and output signal of the charge pump circuit, from a reference signal, and from a clock signal. The generation of the control signal includes a comparison of the reference signal and of the first signal in tempo with a timing signal coming from the clock signal.

Abstract: An apparatus for providing a local reference voltage for a voltage regulator includes a reference capacitor configured to provide the local reference voltage, a charge pump configured to push current to, or pull current from, the reference capacitor according to one or more control inputs received by the charge pump, and a boosting circuit configured to add or subtract a discrete quantity of charge to the reference capacitor according to one or more boosting control signals. A boosting control circuit may be configured to disconnect a boosting capacitor from the reference capacitor during a first phase of a control cycle and connect the boosting capacitor to the reference capacitor during a second phase of the control cycle. The boosting capacitor may be pre-charged (to add charge) or discharged (to subtract charge) during the first phase of the control cycle. A corresponding method is also disclosed herein.

Abstract: According to one embodiment, a semiconductor device includes: a first switch SWx which switches whether or not to supply a first power supply voltage Vx generated by accumulating a charge outputted from a power source 10, as a second power supply voltage VDD to a first circuit 13, and a second switch SW1 which switches whether or not to connect to the first circuit 13 a smoothing capacitor C1 which suppresses a fluctuation of the second power supply voltage VDD, and the first switch SWx is switched to an on state in response to that the first power supply voltage Vx has reached a sufficient voltage, and then the second switch SW1 is switched to the on state in response to that the second power supply voltage VDD has reached a sufficient voltage.

Abstract: An adaptive backlight device includes a transistor, a voltage detector and an adaptive controller. The transistor is configured to control the current flowing through a light string. The transistor provides a first voltage signal and a second voltage signal. The voltage detector generates a voltage difference signal according to the first voltage signal and the second voltage signal. The adaptive controller receives the voltage difference signal from the voltage detector. The adaptive controller includes a counter. When the adaptive controller determines that the voltage difference signal is larger than or equal to a predetermined value, the adaptive controller increases the current flowing through the light string at least once via the control end of the transistor to increase the cross voltage of the light string and decrease the cross voltage of the transistor.

Abstract: In described examples, a multi-stage charge pump includes first, second and third charge pump stages connected in series. Each of the first, second and third charge pump stages includes a charge pump circuit of a first type that increases an input signal of a respective charge pump circuit by up to a given amount. The multi-stage charge pump also includes a level shifter that swings a level clock signal between a voltage of an output signal of the third charge pump stage and one of an offset voltage and ground. The multi-stage charge pump further includes a charge pump circuit of a second type that increases the voltage of the output of the third charge pump stage by up to another amount and provides an output and the other amount is set by the level shifter. Also, the multi-stage charge pump includes a charge pump circuit of a third type.

Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.

Abstract: A charge pump circuit includes a first charge pump unit and a second charge pump unit. The first charge pump unit pumps an input voltage to output a first pumped voltage according to a first clock signal, a second clock signal and a third clock signal. The second charge pump unit pumps the first pumped voltage to output a second pumped voltage according to the first clock signal, a fourth clock signal and the third clock signal. The first clock signal and the third clock signal are non-overlapping clock signals. A falling edge of the second clock signal leads a rising edge of the first clock signal. A falling edge of the fourth clock signal leads a rising edge of the third clock signal.

Abstract: A switch drive circuit includes a high-side power supply section, a latch circuit, a high-side driver, a low-side driver, and a high-side switch control circuit. The latch circuit latches a logical level of a high-side switching signal at the time of performing switching of a high-side switch. The high-side driver drives the high-side switch by the high-side switching signal outputted from the latch circuit. The low-side driver drives a low-side switch by a low-side switching signal. The high-side switch control circuit sets, at the time of stopping the switching of the high-side switch, a stop established state in which the logical level of the high-side switching signal is fixed at a stop logic level, and releases the stop established state at the time of performing the switching of the high-side switch.

Abstract: An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Abstract: A method includes charging a capacitor connected to an input node, gradually decreasing an output voltage at an output node, and electrically connecting the input node to the output node. A circuit that performs the method is also disclosed. A system that includes the circuit is also disclosed.

Abstract: A semiconductor apparatus includes a detection voltage generation circuit configured to generate a first detection voltage and a second detection voltage of which voltage levels are varied according to characteristics of a PMOS transistor and an NMOS transistor in response to a detection enable signal, a code generation circuit configured to generate a detection code in response to the voltage levels of the first and second detection voltages, a reference voltage generation circuit configured to generate a reference voltage in response to the detection code, an internal voltage generation circuit configured to generate an internal voltage in response to the reference voltage, and an internal circuit configured to operate by receiving the internal voltage.

Abstract: A circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.

Abstract: A charge measuring device detects focused ion beam attacks on an integrated semiconductor circuit with a capacitor, a field effect transistor, and a charge collecting device all manufactured in the integrated semiconductor circuit and insulated from additional circuit elements. A first pole of the capacitor is conductively connected to the charge collecting device and a gate of the field effect transistor. When a voltage is applied to the second pole of the capacitor, a drain source current flows through the field effect transistor, and a relationship between the voltage and the drain source current is ascertained. A comparison of the relationship with a previously ascertained relationship indicates a change of the charge quantity stored in the capacitor by the charge collecting device.

Abstract: An integrated circuit includes a voltage set input terminal, a current source, a voltage clipping circuit, and a voltage regulator. The clipping circuit receives a voltage from the terminal and supplies a voltage onto a reference voltage input of the regulator. The magnitude of an output voltage VOUT output by the regulator is the voltage on reference voltage input multiplied by the voltage gain of the regulator. The user sets VOUT by attaching an external resistor to the terminal. Current from the current source flows out of the terminal, and through the external resistor, thereby setting the voltage on the terminal. If the voltage on the terminal is between V1 and V2, then VOUT is a fixed multiple of the voltage. If the voltage is less than V1, then VOUT is a predetermined VOUTMIN value. If the voltage is greater than V2, then VOUT is a predetermined VOUTMAX value.

Abstract: A mixing stage includes a first modulation stage that receives an input signal from a first common node of the mixing stage, a first local oscillator input that receives a local oscillator signal, and a first modulation signal output adapted to provide a first modulated signal. A second modulation stage of the mixing stage includes a second input that receives a phase inverted representation of the input signal from a second common node of the mixing stage, a second local oscillator input that receives the local oscillator signal, and a second modulation signal output adapted to provide a second modulated signal. A current generation circuit provides a supply current to the first common node and to the second common node. A current control circuit is adapted to superimpose an offset current to the current of at least one node of the first common node and the second common node.

Abstract: The present invention relates to a regulation circuit for a charge pump and to a method of regulating a charge pump. The regulation circuit comprises a detector operable to analyze a temporal activity of the charge pump, and a pump clock generator coupled to an output of the detector and having an output coupled to a clock input of the charge pump to vary a pump clock frequency of the charge pump in dependence of the analysis of the detector, or a supply or voltage generator coupled to an output of the detector and having an output coupled to the charge pump to vary an amplitude of a clock signal within the charge pump in dependence of the analysis of the detector.

Abstract: A DC/DC converter including: a plurality of conversion cells connected in parallel and/or in series, each cell including at least one switch and at least one passive power storage element; and a diagnosis circuit capable of individually testing the cells to detect possible defective cells, of deactivating the defective cells, and of storing the location of the defective cells.

Abstract: A circuit includes a PMOS transistor having a source coupled to an input node and a drain coupled to an output node, a control circuit operating with a voltage of an internal line to control a gate voltage of the PMOS transistor, a comparator operating with the voltage of the internal line to cause a comparator output to change from a first state to a second state in response to a drop of voltage of the input node, a switch circuit configured to connect the input node to the internal line when the comparator output is in the first state, and to connect the output node to the internal line when the comparator output is in the second state, and a block circuit configured to block a path from the output node to the input node through the PMOS transistor when the comparator output is in the second state.