Abstract: An piezoelectric electromechanical transistor has first and second terminals formed in a semiconductor region, a gate and a piezoelectric region between the gate and the semiconductor region. The piezoelectric region may be configured to drive the semiconductor region to vibrate in response to a signal applied to the gate. The transistor may be configured to produce a signal at the first terminal at least partially based on vibration of the semiconductor region.

Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.

Abstract: An SDRAM includes a DC-DC converter IC for generating a first internal power supply voltage from external power supply voltage, a regulator IC for generating a second internal power supply voltage lower than the first internal power supply voltage, from external power supply voltage, and a switching portion for supplying the first internal power supply voltage to an internal circuit in a normal operation mode and supplying the second internal power supply voltage to the internal circuit in a self-refresh mode. The switching unit allows the DC-DC converter IC and the regulator IC to operate simultaneously only for a prescribed overlapped period, at a time of operation mode switching. The DC-DC converter IC temporarily increases the first internal power supply voltage within the operating voltage range of the internal circuit in the overlapped period.

Abstract: SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

Abstract: A current limit circuit comprising: a current limit element for limiting an output current level to within a predetermined range of a limiting current and including a first PMOS transistor having a source to which a predetermined voltage is applied and a drain through which the output current is supplied; and a gate voltage generating circuit for generating a gate voltage by a feedback control such that a difference between the predetermined voltage and a gate voltage of the first PMOS transistor coincides with a threshold voltage of a second PMOS transistor having approximately the same characteristic as that of the first PMOS transistor in a state in which a predetermined current is flowing through the second PMOS transistor.

Abstract: A D/A converter having reference node for receiving a reference voltage and together network having a network reference bus connected to the reference node by way of a first electrical connection. The converter network produces a series of reference outputs derived from the reference voltage in response to a digital input applied to the converter, with the converter network sinking a network reference current at the network reference bus which varies with the converter digital input. A reference current compensator circuit is included which provides a compensation current at the network reference bus having a magnitude which varies in response to at least a portion of the digital input, with the compensation current operating to reduce variations in current through the first electrical connection caused by changes in the digital input.

Abstract: A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Abstract: A reset transistor is prevented from being deteriorated when power-down occurs during a programming operation or an erasing operation. It is made possible to protect the reset transistor as well as other transistors in a circuit to which a high voltage is applied when the power-down occurs during the erasing operation on an EEPROM, because the system is not reset all at once based only on a first reset signal POR of a power-on reset circuit, but is reset based on the first reset signal POR and a low voltage detection signal LD from a low voltage detection circuit so that the reset transistor is not turned on while the high voltage is applied to it.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.

Abstract: A start circuit including a load unit, a first switch, a second switch and a reset control circuit is provided. The load unit receives a power voltage. The first switch is electrically connected between the load unit and a ground, and receives a node voltage from the reference circuit. The second switch has a first end electrically connected to the reference circuit, a second end electrically connected to the ground, and a control end electrically connected to the second end of the load unit. The second switch determines whether to provide a start voltage to a reference circuit according to a conducting state thereof. The reset control circuit provides a discharge path between the control end of the first switch and the ground, and conducts the discharge path according to the power voltage during a period when the power voltage is smaller than a threshold voltage.

Abstract: A semiconductor device including a plurality of capacitance units connected in parallel between a first voltage and a second voltage. Each of the plurality of capacitance units includes: a capacitance element connected with the first voltage; and a capacitance disconnecting circuit connected between the second voltage and the capacitance element. The capacitance disconnecting circuit includes a non-volatile memory cell with a threshold voltage changed based on a change of a leakage current which flows from the capacitance element, and blocks off the leakage current based on a rise of the threshold voltage of the non-volatile memory cell when the leakage current exceeds a predetermined value.

Abstract: A control circuit for a transistor arrangement comprises a monitoring arrangement (60) for monitoring the current flow and voltage across the transistor arrangement (50) and means (62) for determining if the current and voltage values define an operating point which falls within a stable operating region. The stable operating region comprises a region having a boundary (30) which comprises an electro-thermal instability line.

Abstract: A design structure embodied in a machine readable medium used in a design process includes a current mirror circuit that includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled to the first node and a second node coupled to a common voltage. The mirror transistor has a gate coupled to the first node. The ratioed body bias feedback unit generates a body bias voltage coupled to the body of the reference transistor and the body of the mirror transistor. The ratioed body bias feedback unit is configured to adjust the body bias voltage in relationship to the common voltage so that the reference transistor and the mirror transistor each have a threshold voltage within a predefined range.

Abstract: A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.

Abstract: The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is grounded. At least one of the two transistors is a transistor whose channel is formed in the oxide semiconductor layer. This makes it possible to reduce power consumption due to cutoff current of at least one of the two transistors.

Abstract: A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

Abstract: A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

Abstract: An amplifier circuit and a method of signal amplification are provided. The amplifier circuit includes a first amplifier and a charge pump. The first amplifier includes a first terminal, a second terminal, and a third terminal. The first terminal is coupled to a first external voltage. The second terminal is coupled to a negative voltage. The third terminal is coupled to a ground reference voltage. The charge pump is coupled to the first amplifier for providing the negative voltage transformed from a second external voltage.

Abstract: A high-voltage MEMS system compatible with low-voltage semiconductor process technology is disclosed. The system comprises a MEMS device coupled to a high-voltage bias generator employing an extended-voltage isolation residing in a semiconductor technology substrate. The system avoids the use of high-voltage transistors so that special high-voltage processing steps are not required of the semiconductor technology, thereby reducing process cost and complexity. MEMS testing capability is addressed with a self-test circuit allowing modulation of the bias voltage and current so that a need for external high-voltage connections and associated electro-static discharge protection circuitry are also avoided.

Abstract: A varactor includes a field effect transistor (FET) integrated with at least a portion of a bipolar junction transistor (BJT), in which a back gate of the FET shares an electrical connection with a base of the BJT, and in which a reverse voltage applied to the back gate of the FET creates a continuously variable capacitance in a channel of the FET.

Abstract: A semiconductor device including: a low threshold PMOS device formed over an N-type region, the source and drain of the low threshold PMOS formed in P-regions surrounded by N-regions; a low threshold NMOS device formed in a P-type region, the source and drain of the low threshold NMOS formed in N-regions surrounded by P-regions; first and second substrate bias generators, each connected to one of the low threshold devices for generating a substrate bias; a voltage source for generating substrate bias during a standby mode to reduce leakage current; wherein a low voltage threshold is established by the source and drain regions of the low threshold devices and their respective surrounding regions of opposite polarity.

Abstract: Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply.

Abstract: A differential voltage controlled current source generating one or more output currents is based upon a single external resistor. The differential voltage controlled current source may generate an output current that is proportional to a received differential voltage and a bias current with the use of a single external resistor. The technique may be used to generate multiple accurate and process independent current sources. The current sources may be a zero temperature coefficient (ZTC) current, a proportional to absolute temperature (PTAT) current, or an inversely proportional to absolute temperature (NTAT) current. The output of the current sources may be inversely proportional to the resistance of the external resistor.

Abstract: A voltage boost circuit is driven with a clock signal CLK which toggles between voltages V1 and V2. A first MOSFET is coupled between CLK and an output node OUT, and at least one additional MOSFET is coupled between OUT and a supply voltage. The first terminal of a capacitance is coupled at its first terminal to OUT, and at its second terminal to a delay circuit arranged to toggle its output to ˜V2 or ˜V1 a predetermined amount of time after the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2 or ˜V1, respectively. The capacitance is charged to ˜V2 when the voltage applied to the clock signal side of the first MOSFET toggles to ˜V2, and OUT is increased to a voltage greater than V2 when the output of the delay circuit toggles to ˜V2. The only active device junctions subjected to the boosted voltage are MOSFET well-substrate junctions, such that no active devices are overstressed.

Abstract: Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line.

Abstract: Apparatus, systems, and methods are disclosed that operate to boost an electrical potential of a control terminal of a transistor from a signal on an input terminal of the transistor to render a channel in the transistor more conductive. Additional apparatus, systems, and methods are disclosed.

Abstract: A solar cell device includes a solar cell section configured to output a first voltage upon receiving light. A charge pump circuit includes a first charge pump. The first charge pump includes a first terminal and a second terminal. The first terminal is configured to receive the first voltage from the solar cell section, and the second terminal is configured to output a second voltage that is higher than the first voltage. An output section is configured to receive an output voltage output by the charge pump circuit. The charge pump circuit is formed on a single semiconductor substrate.

Abstract: Locked loops, bias generators, charge pumps and methods for generating control voltages are disclosed, such as a bias generator that generates bias voltages for use by a clock signal generator, such as a voltage controlled delay line, in a locked loop having a phase detector and a charge pump. The charge pump can either charge or discharge a capacitor as a function of a signal from the phase detector to generate a control voltage. The bias generator can receive the control voltage from the capacitor, and it generates bias voltages corresponding thereto. A portion of the bias generator can have a topography that is substantially the same as at least a portion of the topography of the charge pump. As a result, it can cause the charge pump to charge the capacitor at the same rate that it discharges the capacitor over a relatively wide range of control voltages.

Abstract: The present invention belongs to the technical field of semiconductor devices, and more specifically, relates to a gate-controlled PN field-effect transistor and the control method thereof The gate-controlled PN field-effect transistor disclosed by the present invention comprises a semiconductor substrate region, a drain region and a source region on the left and right sides of the substrate region, and gate regions on the upper and lower sides of the substrate region. The gate-controlled PN field-effect transistor works in the positive bias state of the source-drain PN junction and is conducted from the middle of the substrate region. The gate-controlled PN field-effect transistor provided by the present invention decreases the leakage current and increases the drive current at the same time, namely decreases the chip power consumption and improves the chip performances at the same time.

Abstract: An electronic circuit includes a plurality of circuit blocks, a plurality of bias circuits, a switching circuit, and plurality of transistors. The plurality of circuit blocks each includes a high power terminal and a low power terminal. The switching circuit includes a plurality of switches for selectively coupling a bias circuit of the plurality of bias circuits to the low power terminal of a circuit block of the plurality of circuit blocks. Each bias circuit of the plurality of bias circuits is selectively couplable to the low power terminal of each of the plurality of circuit blocks. Each transistor of the plurality of transistors has a first current terminal coupled to a circuit ground terminal, and each transistor of the plurality of transistors has a control terminal for controlling the conductivity of the plurality of the transistors by a bias circuit of the plurality of bias circuits.

Abstract: A biasing circuit of an integrated circuit includes a well of the integrated circuit and a plurality of transistors disposed in the well. The transistors couple the well to three signals providing corresponding voltages. The transistors bias the well to an extreme one of the corresponding voltages for the three signals.

Abstract: To provide a semiconductor device including: a MOS transistor formed in a semiconductor substrate and have a threshold voltage to be adjusted, a replica transistor of the MOS transistor, a monitoring circuit monitors a gate/source voltage needed when the replica transistor flows a current having a given designed value, a negative voltage pumping circuit generates a substrate voltage of the MOS transistor, based on an output from the monitoring circuit, and a limiting circuit defines the operation of the negative voltage pumping circuit, regardless of a monitoring result of the monitoring circuit, in response to an excess of the substrate voltage with respect to a predetermined value.

Abstract: A switching circuit includes a source follower current mirror having an input, an output, a first source terminal, a bias terminal, and a second source terminal; a current source coupled to the input of the current mirror; an output terminal coupled to the output of the current mirror; a first bias transistor coupled to the first source terminal; a second bias transistor coupled to bias terminal of the current mirror; and a driver transistor coupled to the second source terminal. An input transistor in the current mirror is sized such that the input voltage is substantially independent of the supply voltage.

Abstract: A negative high voltage generator includes a charge providing unit and a voltage conversion unit. The charge providing unit is configured to periodically output a predetermined amount of positive charges received from a supply voltage. The voltage conversion unit is configured to store the positive charges and to discharge the stored positive charges to a ground voltage to generate a negative high voltage having a magnitude larger than a magnitude of the supply voltage.

Abstract: A voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.

Abstract: Provided is a boosting circuit which avoids a malfunction of a peripheral circuit to be connected to the boosting circuit. The boosting circuit includes: a first discharge circuit for discharging a voltage of a first output terminal when a boosting unit stops a boosting operation; and a second discharge circuit for discharging a voltage of a second output terminal. The second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage.

Abstract: A semiconductor element 100 including an MISFET according to the present invention is characterized by having diode characteristics in a reverse direction through an epitaxial channel layer 50. The semiconductor element 100 includes a semiconductor layer 20 of a first conductivity type, a body region 30 of a second conductivity type, source and drain regions 40 and 75 of the first conductivity type, an epitaxial channel layer 50 in contact with the body region, source and drain electrodes 45 and 70, a gate insulating film 60, and a gate electrode 65. If the voltage applied to the gate electrode of the MISFET is smaller than a threshold voltage, the semiconductor element 100 functions as a diode in which current flows from the source electrode 45 to the drain electrode 70 through the epitaxial channel layer 50. The absolute value of the turn-on voltage of this diode is smaller than that of the turn-on voltage of a body diode that is formed of the body region and the first silicon carbide semiconductor layer.

Abstract: Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first voltage generator being configured to be activated in response to a first control signal taking an active level and deactivated in response to the first control signal taking an inactive level, and the second voltage generator being configured to be activated in response to each of the first control signal and a second control signal taking an active level and deactivated in response to at least one of the first and second control signal taking an inactive level.

Abstract: An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.

Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.

Abstract: A voltage converter including a first transistor, a second transistor, an inductor and a control module is provided. The first transistor has a source terminal receiving an input signal, and a body terminal receiving a first bias voltage. The second transistor has a drain terminal coupled to a drain terminal of the first transistor, a source terminal coupled to ground, and a body terminal receiving a second bias voltage. The inductor has a first terminal coupled to the drain terminal of the first terminal and a second terminal generating an output voltage. The control module is coupled to a gate terminal of the first transistor and a gate terminal of the second transistor for controlling conducting states of the first transistor and the second transistor.

Abstract: An integrated circuit that includes a data storage cell. The data storage cell has a PMOS transistor in an n-well. In addition, the data storage cell has a PMOS diode connecting a voltage source to a bias node of the n-well. Alternatively, an integrated circuit that includes a data storage cell. The alternative data storage cell has an NMOS transistor in an isolated p-well. In addition, the alternative data storage cell has an NMOS diode connecting a voltage source to a bias node of the isolated p-well.

Abstract: A circuit includes a first and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.

Abstract: A conventional circuit requires a booster circuit for generating a voltage higher than an external power supply voltage, thus low power consumption is difficult to be achieved. In addition, a display device incorporating the aforementioned conventional switching element for booster circuit has problems in that the current load is increased and the power supply becomes unstable with a higher output current.

Abstract: A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.

Abstract: An electrical contact structure distributes current along a length thereof. The electrical contact structure includes a plurality of n metal rectangles on n levels of metal. The rectangle on one metal level is at least as wide in width and vertically covers in width the rectangle on the metal level immediately below. The rectangle on one metal level is shorter in length than and substantially aligned at a first end with the rectangle on the metal level immediately below. Rectangle first ends are substantially aligned. Features of an exemplary FET transistor of this invention are a source and drain terminal electrical contact structure, a multi-level metal ring connecting gate rectangles on both ends, and a wider-than-minimum gate-to-gate spacing. The invention is useful, for example, in an electromigration-compliant, high performance transistor.

Abstract: According to one embodiment, a voltage generation circuit includes a first boost circuit, a first output circuit, a rectifying circuit, a second output circuit, and a detection circuit. The first boost circuit outputs a first voltage in first and second operation modes. The first output circuit is connected to the first boost circuit, and outputs the first voltage as a second voltage in the first operation mode. The rectifying circuit is connected to the first boost circuit, and outputs a third voltage which is lower than the first voltage in the first operation mode. The second output circuit short-circuits the rectifying circuit in the second operation mode, and outputs the first voltage as a fourth voltage. The detection circuit detects the second and fourth voltages which are supplied from the first and second output circuits.

Abstract: A CMOS IC containing a quantum well electro-optical device (QWEOD) is disclosed. The QWEOD is formed in an NMOS transistor structure with a p-type drain region. The NLDD region abutting the p-type drain region forms a quantum well. The QWEOD may be fabricated with 65 nm technology node processes to have lateral dimensions less than 15 nm, enabling possible energy level separations above 50 meV. The quantum well electro-optical device may be operated in a negative conductance mode, in a photon emission mode or in a photo detection mode.

Abstract: A method includes receiving a set of voltages comprising at least a first voltage, a second voltage, and a third voltage and biasing a well of a transistor based on the extreme voltage of the set of voltages. Biasing the well of the transistor can include concurrently providing a first signal and a second signal based on a comparison of the first voltage and the second voltage and selectively coupling the well of the transistor to a source of the extreme voltage of the set of voltages based on the first signal, the second signal, and the third voltage. An electronic device comprises a transistor and a power switching module. The power switching module includes a set of inputs, each input configured to receive a corresponding one of a set of voltages comprising at least a first voltage, a second voltage, and a third voltage, and includes an output coupled to a well of the transistor, the output configured to provide the extreme voltage of the set of voltages.