Abstract: In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.

Abstract: A start-up circuit for a bias generator circuit includes an oscillator, a power monitoring circuit and a controllable current source. As the power supplies begin to ramp up to their final voltage, the power monitoring circuit monitors power consumed by the oscillator. As the oscillator begins to ring, the power monitoring circuit couples a control signal to the controllable current source, which generates a current used to start-up the bias generator circuit. Once the bias generator circuit has achieved an active operating condition, the start-up circuit is disengaged from the bias circuit by disabling the oscillator. The start-up circuit does not consume any standby current when disabled, and does not effect the operation of the bias generator circuit.

Abstract: A biasing method and apparatus which provides bias circuits of radio frequency (RF) power transistors with a low reactive impedance at low frequencies to reduce hysteresis related distortion without affecting the transistor input or output impedance or any impedance matching network which may be used. In one embodiment, reduced hysteresis within a lateral diffused metal-oxide semiconductor (LDMOS) transistor is brought about by a drain bias circuit without any impact on the transistor output impedance. By removing the effect of the bias circuit at RF frequencies, the bias circuit can be designed with a low reactive impedance at low frequencies without any material consequences on the transistor output impedance. With a low enough reactive impedance, the hysteresis introduced by the bias circuit is substantially reduced. An auxiliary bias feed external to an RF transistor package is also embodied.

Abstract: A semiconductor circuit in which propagated noise from high-speed switching is reduced even if chip size is downsized, by comprises a first circuit such as a DC-DC converter having an oscillating circuit therein, a second circuit having no oscillating circuit, a connection pad connected to a power supply, a first power line and a second power line. A first resistor is disposed on the first power line, and a second resistor, preferably of equal resistance value to that of the first resistor, is disposed on the second power line. By providing resistors on the both or at least. one of the power lines, high-frequency noise generated by the DC-DC converter and propagated to the second circuit through the power lines is reduced.

Abstract: An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.

Abstract: A semiconductor switch circuit that assuredly preserves a switch condition when a power supply is turned off. When a first signal is set to “L” and a second signal is set to “H” and a control signal of VCC/2 is applied, a first ferroelectric capacitor and a second ferroelectric capacitor connect to a first control terminal and a second control terminal, respectively, and signals at the control terminals are stored as polarization states in the ferroelectric capacitors. After this storage, the second signal is set to “L”, the ferroelectric capacitors disconnect from the control terminals and terminals of the ferroelectric capacitors are short-circuited. Consequently, imprint effects are prevented and polarizations are assuredly preserved. To read out stored information, a power supply for two inverters is disconnected, the control signal of VCC/2 is applied, and the first and second signals are set to “H”.

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optionally, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.

Abstract: A DRAM includes a first power source section for supplying a higher operational voltage in an active mode and a lower waiting voltage in a waiting mode to a data processing section through a source line, a compensating capacitor connected to the source line for alleviating the fluctuations on the source line, a second power source section for supplying the operational voltage to the compensating capacitor, and a switch for coupling the source line to the compensating capacitor in the active mode.

Abstract: A current and temperature compensated voltage reference circuit uses a power supply voltage as low as 1.3 Volts. A folded-cascode amplifier measures the temperature dependent voltages provided by first and second bias circuits, each including two series-coupled diodes or diode-connected bipolar junction transistors (BJTs), and provides a resulting proportional to absolute temperature (PTAT) current through a cascode-protected output transistor. A voltage reference circuit uses a PTAT current through a resistor to create a PTAT voltage in series with a diode-voltage. The resistor value is adjusted until the sum of these voltages is equal to the bandgap voltage of silicon, providing a temperature compensated voltage reference. The reference circuit is suitable for use with an implantable cardiac rhythm management system having a battery that provides a power supply voltage varying approximately between 1.3 Volts and 3.25 Volts.

Abstract: The invention relates to a control circuit for a bias source including a stand-by device and a starting-aid device, with their respective outputs connected to a control input of the bias source, the starting-aid device including a switch to inhibit its operation, controlled by the bias source, said circuit including capacitive means for reactivating the starting-aid device when the “Stand-by” control signal changes state, indicating that the bias source should be reactivated.

Abstract: In a semiconductor device operating upon receiving two power supply potentials (VDD1, VDD2) (VDD1<VDD2), the two power supplies must be simultaneously turned on, or the power supply (VDD2) must be turned on earlier than the power supply (VDD1). A substrate bias circuit for generating a substrate bias voltage operates upon receiving the power supply potential (VDD2) but cannot generate a stable substrate bias voltage before a certain time elapses after turning on the power supply (VDD2). If the power supply (VDD1) is turned on during this period, latch-up may occur. To prevent this, before a predetermined period from the time of power-on elapses, including a period after the power supply (VDD2) is turned on until the power supply VDD1 is turned on, transistors (MN1, MN2, MP1, MP2) are operated under the control of a reset circuit (14) to connect an N-well (11) to the power supply voltage (VDD2) terminal and a P-well (12) to a ground voltage (VSS) terminal.

Abstract: An analog IC includes analog circuit components and digital circuit components formed from plural I2L circuits. The analog IC is supplied with first and second voltages from first and second direct current sources. The analog circuit components are driven by the first voltage and the I2L circuits are driven by the second voltage. At least one I2L circuit is activated before the analog IC receives the first voltage while the remaining at least one I2L circuit is activated after the analog IC receives the first voltage, a switching circuit switching on and off the transmission of the second voltage to the remaining at least one I2L circuit according to a voltage level of the first voltage.

Abstract: In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Abstract: A back bias voltage level sensing circuit includes a constant current generation unit for generating a constant current regardless of a variation in a power supply voltage; a switch for transferring or disconnecting the constant current generated from the constant current generation unit under the control of a switch control signal; a current distribution unit for distributing the constant current transferred by the switch by using a current mirror under the control of a first control signal; a switching current removal unit for flowing the switching current generated when the switch is turned on and turned off to the ground according to a second control signal; a back bias voltage level sensing unit for sensing a level of a back bias voltage and outputting an output signal according to the current distributed by the current distribution unit; and a switching controlling unit for receiving an oscillating signal and the output signal from the back bias voltage level sensing unit and outputting a switch control

Abstract: A Norton equivalent implementation of a fail safe bias circuit drives a bus to provide a stable bias voltage which is not affected by an output impedance of a current source. The Norton equivalent implementation has first current source, a bias resistor and a current sink in series. The bias resistor is connected across a pair of differential bus lines so that the current flowing through the bias resistor causes a bias voltage to be generated between the bus lines. The current to the bias resistor is selectively switched on and off to control the bias voltage so that the bias voltage can be turned off during high speed data transfers on the bus.

Abstract: The invention describes a circuit layout for generating a supply DC voltage in a dependent relationship to a non-constant input DC voltage in three voltage intervals, with the supply voltage being maintained at a constant nominal value in the intermediate voltage interval, and with the supply voltage being reduced by constant differential values in the other two voltage intervals in order to allow emergency functions to the maintained; implementation is effected by means of a diode arrangement for the first differential value, by means of a first Zener diode arrangement for maintaining the constant value, and by means of a second Zener diode arrangement for bridging the diode arrangement. In addition, a process will be described for generating an output voltage with superimposed current pulses for a signal generator unit which process will feed in such a supply voltage via a control circuit. The circuit layout according to this invention is particularly suitable for implementing this process.

Abstract: An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Abstract: A semiconductor integrated circuit includes a boosted potential circuit for generating a boosted potential and outputting the boosted potential at an output terminal thereof. The boosted potential generating circuit bas a variable current supply capability while the boosted potential is output. A load circuit is supplied with the boosted potential and has a load which varies based a specification signal for setting a specification of the semiconductor integrated circuit. Control circuitry, responsive to the verification signal, generates a control signal to set a current supply capability of the boosted potential generating circuit.

Abstract: An electronic circuit includes first and second inductive bias elements coupled to respective first and second switching elements for preventing avalanche current flow through the switching elements. In one embodiment, a resonant inverter circuit includes first and second switching elements with first and second freewheeling diodes coupled across the respective switching elements. A first inductive bias element is coupled to the first switching element and a second inductive bias element is coupled to the second switching element. The first and second bias elements are inductively coupled with a resonant inductive element for biasing the respective first and second switching elements against avalanche current flow.

Abstract: An internal power supply generating circuit for a semiconductor memory device reduces fluctuations in the external power supply by reducing the rate at which a drive transistor is turned on and off. The circuit includes a drive transistor that generates an internal power signal by reducing the external power supply voltage responsive to a bias signal. A feedback loop generates the bias signal and slows down the rate at which the bias signal changes, thereby reducing the rate at which the drive transistor turns on and off. The feedback loop includes a comparator for comparing the internal power supply voltage to a reference voltage and a bias circuit having a pair of push-pull transistors for generating the bias signal responsive to the output of the comparator. To slow down the rate at which the bias signal changes, the bias circuit includes a resistor coupled in series with the transistors and/or a capacitor couple to the output terminal of the bias circuit.

Abstract: In a reference voltage generating device, it causes rising of output of reference voltage to speed while preventing wraparound of power source noise after rising of reference voltage. It causes an electric supply circuit to connect to a reference voltage output terminal of a reference voltage generating source, while switching ON switches only prescribed period from just after power-ON-timing by power control signal until the time when timer circuit operates. And then after lapse of prescribed time, when the timer circuit terminates its operation, the electric charge circuit is disconnected from the reference voltage output terminal due to OFF of the switches. Consequently, during prescribed time from power ON, charging current toward load capacitance attached to the reference voltage output terminal increases, thus reference voltage rises rapidly.

Abstract: A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator.

Abstract: Input/output circuitry for electrically protecting an internal element includes an input/output terminal connected to the internal element, a pair of first and second power terminals applied with a bias voltage, a series connection of a diode and a bipolar transistor between the pair of first and second power terminals so that an intermediate point between the diode and the bipolar transistor is connected to the input terminal, and a parasitic resistance connected between a base of the bipolar transistor and the diode so that the diode is connected between the parasitic resistance and an emitter of the bipolar transistor. An electrostatic pulse applied to the input/output terminal is clamped by the series connection of the diode and the bipolar transistor to protect the internal element from an electrostatic pulse applied to the input/output terminal.

Abstract: A CMOS circuit (10), which is integrated in a semiconductor substrate, comprises a principal circuit part (12), which includes the major part of the circuit components in a well isolated from the substrate by a substrate diode. The CMOS circuit furthermore comprises a power output stage (16) driving an inductive load (26, 28). A sensor (18) is connected with one output (22, 24) of the power output stage (16) and on detection of a voltage biasing the substrate diode (30, 32) in the conducting direction produces a switching signal at the output. On occurrence of the switching signal produced by the sensor (18) a controllable switch (20) disconnects the supply voltage from the principal circuit part (12). In its own separate well (46) a status memory (14) is formed on the substrate adjacent to the principal circuit part (12), such status memory (14) comprising memory elements for storage of status data of the principal circuit part (12) on disconnection of the supply voltage.

Abstract: A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.

Abstract: An I/O circuit whose output receives a voltage V.sub.PAD which is temporarily higher than a critical voltage V.sub.DS MAX >V.sub.DS 1 across drain and source of a conducting first N-FET (110, N1) acting as a pull-down device. The first N-FET is protected against hotelectron induced degradation by a serially coupled second N-FET (130, N3). A variable drain-source voltage V.sub.DS 3 is added to V.sub.DS 1. A comparator (150) compares the received voltage V.sub.PAD to a supply voltage V.sub.CC and pulls a gate (G) of the second N-FET (N3) to V.sub.PAD or to V.sub.CC. The conductivity of the second N-FET (N3) is thereby changed so that VPAD is distributed among V.sub.DS 1 and V.sub.DS 2. The comparator (150) conveniently comprises two P-FETs (P1, P2, 160, 170).

Abstract: A low-cost power supply is connected to an object circuit and to a dummy load circuit. The object circuit sends a dummy load control signal to the dummy load which indicates the current requirement of the object. The dummy load sources an amount of current as specified by the dummy load control signal such that the total supply current from the power supply is constant. According to an aspect, the dummy load is implemented as MOS or bipolar transistors. The dummy load control signals are either analog or digital. The object may produce multiple dummy load control signals. The object may consist of multiple integrated circuits wherein each integrated circuit produces one or more dummy load control signals. Smoothing elements may be included in the power supply. In an embodiment, the object is a system of integrated circuits including a microprocessor. The system communicates via a communication bus. The microprocessor fetches instructions over the communication bus.

Abstract: In a method of temperature stabilization of a reference voltage, in a first prespecified time interval, a current having a first constant amperage and, in a second prespecified time interval, a current having a second constant amperage and alternately applied to a pn junction. During the first and second time intervals, voltages at the pn junction are supplied to an input of an analysis circuit. The analysis circuit forms the difference between the two voltages and adds the difference in a weighted manner to a voltage obtained from one of the first and second amperages. The weighted result is applied to an output of the analysis circuit. The first constant amperage is applied to the pn junction during both the first and second prespecified time intervals and the second constant amperage is applied to the pn junction during the second prespecified time interval.

Abstract: A power supply filter has a primary current source coupled to a node carrying a power supply signal. The second end of the primary current source is coupled to an impedance that is further coupled to a low voltage node. A differential amplifier having an inverting input, a non-inverting input, and an output, has its non-inverting input coupled to the junction between the impedance and the primary current source. The output of the differential amplifier carries the filtered power supply signal and is coupled to a capacitance. The capacitance is coupled between the output and a lower voltage. A feedback path is coupled between the output and the inverting input.

Abstract: A trimmable current cell and method for providing an output current at a desired level which may be used to provide a particular current level for a digital-to-analog converter. The cell includes a first circuit with two fixed resistors connected in series which initially establish the output current, and a second circuit for trimming the output current from the first circuit to the desired level. The second circuit has a series-connected pair of trimmable resistors whose common node is connected to the first circuit at a common node between the fixed resistors. Trimming one of the trimmable resistors increases the output current to the desired level and trimming the other of the trimmable resistors decreases the output current to the desired level.

Abstract: Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

Abstract: A bipolar or MOS current reference circuit is provided, which generates a reference current having no temperature dependence and which is able to be operated by a single battery having a supply voltage of approximately 1 V. This circuit includes a first transistor having an emitter or source and a base or gate connected through a resistor, a first current mirror subcircuit generating a first mirror current of an input current flowing through the resistor, and a second current mirror subcircuit generating a second current of the input current flowing through the resistor. The first mirror current has a negative temperature coefficient. The second mirror current has a positive temperature coefficient. The first and second mirror currents are added to generate a sum current having no temperature dependence, which is derived as a reference current. The sum current is supplied to the first transistor to thereby drive the first transistor.

Abstract: A drive IC is provided for suitably driving piezoelectric elements of an ink jet printer. The drive IC includes a plurality of drive output pads, a plurality of data input pads for feeding plural kinds of drive data, a plurality of shift registers each connected to a corresponding one of the data input pads, a plurality of analog switches connected to each of the drive output pads, and a selecting circuit for selectively feeding one of plural kinds of drive voltages to each of the drive output pads through a selected one of the analog switches according to the drive data.

Abstract: A power supply circuit is provided with a supplemental power source which is intermittently brought into service each time a main power source is coupled to a high power drain circuit. That is, the supplemental power source is switched to a circuit, which is susceptible to power drop, in response to switching over of the main power source to the high power drain circuit.

Abstract: A semiconductor integrated circuit which converts power-supply voltage applied from outside into optimum voltage for operating an internal circuit at the frequency of an internal clock in response to a multiplication control signal supplied to a PLL circuit from outside to generate the internal clock for operating the internal circuit by dividing a clock supplied from outside or by judging the cycle of an internal clock generated by dividing an external clock so as to supply the optimum voltage to the internal circuit.

Abstract: A voltage detecting circuit and method in a synchronous DRAM is disclosed. The circuit includes first and second pull-up switching portion, first and second pull-down switching portion, first and second pull-up portion, first and second pull-down portion, ; switching transistor and a driving portion. The pull-up and pull-down switching portion are selectively turned-on according to a mode control signal, and the current paths are different for the active power down mode and the normal mode. Each pull-up portion includes a plurality of NMOS transistors connected in series and gated by the boosted voltage and each pull-down portion includes a plurality of NMOS transistors connected in series. An effective channel length of the current path selected in case of the active power down mode is longer than that selected in case of the normal operation mode.

Abstract: A method of controlling a plurality of on-chip capacitors used to enhance power supply to logic circuits for a computer processor. The capacitors are each provided with transistors which temporarily disable the capacitors when an appropriate logic state is applied to the gate of the transistors. In this manner the effects of the capacitors upon system performance can be measured, and if a particular capacitor (or capacitor bank) is defective or presents an adverse impact, it can be permanently disabled by blowing fuses provided for each capacitor (or capacitor bank). The capacitors may be selectively disabled using a control circuit which has a multiplexer provided with a set of inputs from a register which contains a bit pattern that is used to determine which capacitors to disable. The register can be loaded with any pattern or with a pattern that corresponds to the states of the unblown fuses. Alternatively, all of the capacitors may be disabled, such as during power-on reset.

Abstract: A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.

Abstract: A semiconductor device and a method of inspecting the same are described. The semiconductor device does not need voltage adjustment of an external driver circuit, since it contains a voltage generator to inspect and memorize the best value of voltage by controlling from outside. The voltage generator has a plurality of capacitors whose electrodes of one side are connected to a common node, a potential changing circuit to change the potential to which the other electrodes of these capacitors are connected respectively, and a buffer amplifier whose input power is the voltage generated in the common node. The output power of the buffer amplifier is connected to a semiconductor integrated circuit. The potential changing circuit is provided to change the potential to which the electrode of each capacitor is connected to a source potential or to a ground potential depending on the connection of the fuse connected between the source and each of the capacitors.

Abstract: An internal voltage generating circuit for generating an internal voltage VINT from an input external voltage VEXT is provided to stabilize the internal voltage. When the external voltage VEXT is less than or equal to a first boundary voltage VT1 or a second boundary voltage VT2 (>VT1), a constant voltage VINTN independent on the external voltage VEXT, which is produced by a constant voltage generator is outputted therefrom. When the external voltage VEXT is greater than or equal to the first boundary voltage VT1 or the second boundary voltage VT2, a variable voltage (>VINTN) linearly increased with an increase in VEXT, which is produced by a variable voltage generator, is outputted therefrom. When a detecting means detects that the external voltage VEXT has been increased to VT2 or higher, the characteristic of the internal voltage is switched from a constant voltage characteristic to a variable voltage characteristic.

Abstract: A circuit for connecting a memory cell matrix to voltage sources includes a voltage sensor responsive to the voltage levels of a first voltage source and of a second voltage source by producing a sense signal, and a voltage source coupler connected between the memory cell matrix and the voltage sensor. When the first voltage source voltage level is greater than a predetermined threshold voltage level, the sense signal causes the voltage source coupler to drive the first voltage source voltage level into the memory cell matrix. When the first voltage source voltage level falls to the threshold voltage level, the sense signal also causes the voltage source coupler to drive the second voltage source voltage level into the memory cell matrix to sustain memory cell data.

Abstract: A semiconductor integrated circuit device includes a leak detection circuit which can be realized by small pattern area provides voltage Vb through two transistors M1n and M2n, which are caused to be operative in the sub-threshold area without use of a resistor at the gate of a leak current detection transistor MLn. The leak current detection magnification does not become dependent upon power supply voltage and temperature. Thus, detection of the leakage current can be precisely carried out.

Abstract: The object of the present invention is to provide a reference voltage generation circuit which is arranged to obtain the stability of a reference voltage Vref both at the time of start of the power source voltage and at the time of fluctuation of the power source voltage for the reference voltage generation circuit that generates a high reference voltage (Vref). When closing the power source, a low level signal and a high level signal are output from a power source start circuit. These signals are received by a started circuit to thereby make all transistors therein "on" and thereby output a stable reference voltage Vref. The starting characteristic is improved compared to that of a conventional reference voltage generation circuit, whereby the starting has become possible to attain. Even when the power source voltage sharply fluctuates, a stable reference voltage Vref can be output.

Abstract: A differential voltage reference circuit implemented in CMOS provides a continuous differential voltage having good substrate and supply noise-rejection and low power consumption. The differential voltage reference is operable under a low voltage power supply in the range of 1-3 volts and does not require a large silicon die area. The differential voltage reference includes two parasitic bipolar transistors and a single differential summing amplifier. PTAT and CTAT differential signals are summed at the amplifier summing junctions to provide a temperature-independent differential reference voltage. The differential amplifier maintains a common-mode level of the output at a constant level with respect to a bias voltage at the bases of the two bipolar transistors.

Abstract: The present invention provides an output buffer having a self back-bias compensating circuit that adapts the effective output transistor size to overcome current-reducing threshold voltage shifts caused by connection of the output n-wells to a high voltage. More particularly, this invention provides a circuit configuration in which bias level detection is used to switch in additional PFET legs under high back bias conditions. The extra driver legs are disabled under zero back bias. This compensates for the effect that different voltage switching environments have on PFET performance.

Abstract: A semiconductor circuit is so constructed that one of a plurality of different potentials is supplied to sources of FETs via a switching circuit, so as to vary the threshold voltage of the FETs in accordance with the operating state of the semiconductor circuit, thereby decreasing the waste of power.

Abstract: A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor.

Abstract: A circuit for supplying a reference level to a differential sense amplifier in a semiconductor memory circuit, includes a first circuit for detecting an external power supply voltage, and a second circuit controlled by the first circuit, for controlling a reference level to be supplied to a sense amplifier, on the basis of the result of the detection of the external power supply voltage. Regardless of whether the external power supply voltage is a first power supply voltage (5 V) or a second power supply voltage (3 V), it is possible to output the reference level which can avoid occurrence of malfunction.

Abstract: This invention is a voltage divider circuit having an input voltage at a first terminal (V.sub.IN) and an output voltage at a second terminal (V.sub.OUT). The circuit includes a parallel-connected first resistor (R.sub.1) and first capacitor (C.sub.1) coupled between the first and second terminals (V.sub.IN,V.sub.OUT) and a parallel-connected second resistor (R.sub.2) and second capacitor (C.sub.2) coupled between the second terminal (V.sub.OUT) and a reference (V.sub.REF). The ratio of the ohmic value of the second resistor (R.sub.2) to the sum of the ohmic values of the first and second resistors (R.sub.1,R.sub.2) is substantially equal to the ratio of the value in farads of the first capacitor (C.sub.1) to the sum of the values in farads of the first and second capacitors (C.sub.1,C.sub.2).

Abstract: A high-side gate driving circuit, where a current-mode differential error amplifier is used to regulate the current sourced to the gate. A current path is provided from the gate to the source of the power device, and a constant current is provided to the gate. A variable current source is also provided, and this current source is controlled by the output of the error amplifier. Preferably a voltage offset (avalanche breakdown diode) is interposed between the gate and source of the high-side driver; this ensures that the feedback loop will operate in a bistable mode, which avoids instability problems.