Abstract: Individual devices of a redundant array of independent devices (RAID) are coupled to an electrical power supply. For devices having widely varying load impedances, such as disks, incident with the coupling of electrical power thereto, the replacement or addition of a device in the system, while the system is in operation, causes unacceptable power transients in the power supply. To minimize such power transients, a transient suppression circuit is employed to isolate the load impedance of the device from the power supply. Isolation is achieved in the transient suppression circuit by employing an active circuit element, such as a MOSFET power transistor, as the power coupler. A capacitor controlled voltage divider circuit, incident with the coupling of electrical power thereto, couples a time varying gate voltage, which changes as a function of the rate of charge of the capacitor, to the MOSFET power transistor.

Abstract: A transfer gate is provided between an input terminal, receiving voltage Vh of the super Vcc level when a special operating mode is set, and an inverter and an n channel MOS transistor included in a super Vcc detection circuit of a DRAM. The transfer gate is rendered conductive only during a potential detection period during which signal WCBR attain an "H" level. Therefore, a leakage current flowing from the input terminal through the n channel MOS transistor to a ground terminal can be minimized, thereby reducing a consumed current.

Abstract: A current limiting circuit used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors, configured as a differential pair, combined with a fixed current source to limit the current available to a pass transistor of the voltage regulator.

Abstract: A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit.

Abstract: A circuit connects a circuit node to a voltage source selected between two alternative power supply voltage sources. The circuit includes two transistors, specifically a first transistor selectively connecting the circuit node to a first power supply voltage source of the two alternative power supply voltage sources and a second transistor selectively connecting the circuit node to the second power supply voltage source. The first transistor has a gate connected to the second power supply voltage source. The second transistor has a gate connected to the first power supply voltage source. The circuit passes the lowest voltage supplied by the two alternative voltage sources to the circuit node. The circuit is useful, for example, in a voltage translation and overvoltage protection circuit.

Abstract: A power conserving circuit is disclosed which has a start-up circuit for initiating operation of a reference voltage generator. Included are a sensing circuit for producing a pulse signal in response to initial application of an external power source; a reference voltage generator for producing a constant reference voltage independent from an external power source voltage; and a start-up circuit for starting operation of the reference voltage generator during an interval of a pulse produced by the sensing circuit. The start-up circuit includes a switch for connecting and disconnecting the external power source to the reference voltage output port, and a voltage reducing element connected between the switch and the reference voltage output port.

Abstract: A lower power trim circuit in accordance with the present invention includes the series connection of a resistive element, a first transistor, and a second transistor between nodes of a voltage source. The first transistor (which is coupled to the resistive element) is much larger, e.g. twice as large, as the second transistor. When the resistive element is in a low resistance state, the first transistor dominates a node between the first and second transistors due to its large size, thereby causing the node attain a first logical state. When the resistive element is in a high resistance state, the second transistor dominates the node, causing the node to go to a second logical state. The programmable resistive element is preferably selected from a group consisting essentially of silicide resistors, capacitors, and antifuses.

Abstract: In a semiconductor integrated circuit device including a step-down circuit for stepping down an external power supply voltage to obtain an internal power supply voltage, the external power supply voltage can be applied to an internal signal processing circuit using a conventional terminal.

Abstract: A power supply circuit disclosed herein includes a three-terminal regulator for stabilizing a positive voltage applied thereto, a voltage converter for converting the stabilized voltage into a negative voltage, a power-supply section for stabilizing a voltage by a light-emitting diode, and a control circuit for applying a bias voltage across a drain and source of a GaAs FET amplifier only when a voltage is being applied across the gate and source of the amplifier. When power is introduced from a power supply, the presence of the negative voltage supplied from the voltage converter is sensed by the control circuit and a bias begins to be applied to the gate. Therefore, when it is sensed that a predetermined voltage is applied to the gate, a bias begins to be applied to the drain of the FET thereafter. When power from the power supply is cut off, a drop in voltage is sensed and the drain bias begins being cut off while the gate bias for the FET is cut off thereafter.

Abstract: A power-efficient power regulation circuit for use in semiconductor circuit powered by a power signal includes an N-channel transistor which provides a regulated power signal having a stabilized voltage level for use by the semiconductor circuit. A bias pull-up circuit is coupled to the gate of the N-channel transistor and arranged for biasing the N-channel transistor so that it normally conducts current, and a resistive circuit, including a resistive element arranged in series with a resistor-arranged P-channel transistor, is coupled to the source of the N-channel transistor and, in response to the regulated power signal, provides a feedback control signal. A voltage control circuit, coupled to the bias pull-up circuit and the resistive circuit, is activated to control the N-channel transistor in response to the feedback control signal. The voltage control circuit may include an enabling transistor which is activated to enable the voltage control circuit.

Abstract: A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

Abstract: A clamping circuit clamping a boost signal supplied on a boost line includes a p-channel, MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. p-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented.

Abstract: A voltage generating circuit for providing a prescribed voltage, such as 1/2V.sub.DD of the power source voltage V.sub.DD, wherein the capacity of the current and the response time of the voltage generating circuit is significantly improved. When the output voltage V.sub.OUT of the voltage generating circuit drops suddenly from a reference value 1/2V.sub.DD and goes below the lower limit of an allowable voltage level VM-, an n-type MOS transistor MN5A of an output voltage detecting circuit 14 turns on. The potential of the gate terminal for a p-type MOS transistor MP6A in a digital output circuit 16 is pulled to the level of the output voltage V.sub.OUT via the transistor MN5A that was turned on, and said p-type MOS transistor MP6A is turned on in the saturated area more or less perfectly.

Abstract: A parabolic current generator is provided for use with a waveshaping circuit for producing a sinusoidally increasing bus output voltage signal in response to the rising edge of a data input signal, and a sinusoidally decreasing bus output voltage signal in response to a falling edge of the data input signal. The parabolic current generator provides a current that increases parabolically in response to the rising or falling edge of the data input signal and that decreases parabolically when the bus output voltage signal reaches one-half of its intended full voltage swing or falls below one-half of the full voltage swing to respectively produce the sinusoidally increasing and decreasing voltage at the bus output. The parabolic current generator includes an operational amplifier having an integrating capacitor connected between its non-inverting input and its output. A field effect transistor is connected to its inverting input and has an impedance sized to minimize the capacitor value.

Abstract: A circuit includes a first transistor M.sub.1 ; a second transistor M.sub.2 having a gate coupled to a gate of the first transistor M.sub.1 and a source coupled to a source of the first transistor M.sub.1 ; a third transistor M.sub.3 having a source coupled to a drain of the first transistor M.sub.1 and a drain coupled to a current input I.sub.b, the drain of the third transistor M.sub.3 is coupled to the gate of the first transistor M.sub.1 ; a fourth transistor M.sub.4 having a source coupled to a drain of the second transistor M.sub.2, a gate coupled to a gate of the third transistor M.sub.3, and a drain coupled to a supply node V.sub.DD ; and a variable voltage input V.sub.x coupled to the gate of the third transistor M.sub.3.

Abstract: A power supply isolation and switching circuit formed in a semiconductor structure which eliminates a parasitic diode effect. The switching circuit receives a first power source and a second power source, and selects between the two sources to provide the selected power source to a load device. The switching circuit includes a first transistor, and second and third transistors. The first transistor is connected to the first power source for selecting the first power source as the supply voltage of the load device. The second and third transistors are connected in series to the second power source for selecting the second power source. The second and third transistors are formed in two separate wells of a first conductivity type that are spaced apart and isolated from each other by a semiconductor region of a second conductivity type different from the first conductivity type.

Abstract: An improved power interface device suitable for managing power for a PCMCIA card is disclosed which includes internal charge pumps, to gradually turn on the device's internal N-channel MOSFETs, and a first discharge circuit for gradually turning off the N-channel MOSFETs. The first discharge circuit includes an MOS capacitor that incrementally discharges the gates of the N-channel MOSFETs such that the turn-off speed of each N-channel MOSFET is controlled by the ratio of the capacitances of the capacitor and the MOSFET's gate. A second discharge circuit includes a capacitor and is used to gradually turn on the interface device's internal P-channel MOSFET by incrementally charging its gate. The turn-on speed of the P-channel MOSFET is controlled by the ratio of the capacitances of this capacitor and the MOSFET's gate. In another embodiment, diode clamps are provided to protect the interface device's N-channel MOSFETs against time dependent breakdown.

Abstract: A method for minimizing power consumption in a circuit is accomplished by identifying, based on the test parameters and topology information for the circuit, potential excessive power consuming sites. Next, the potential excessive power consuming sites, or potential leakage current sites, are monitored, based on the test parameters, for indeterminate logic states which result in leakage current and excessive power consumption. A report is generated detailing the locations of any leakage current sites, whereby the circuit may be modified to eliminate the leakage current sites prior to fabrication.

Abstract: A clamping circuit clamping a boost signal supplied on a boost line includes a p-channel MOS transistor and an n-channel MOS transistor. These MOS transistors are serially connected between an internal power supply line and the boost line. p-channel MOS transistor receives a clamping level control signal from a clamp control circuit at its gate. In accordance with the clamping level control signal a clamping level given by clamping circuit is varied. Therefore, by decreasing the clamping level of the boost line during an overvoltage-applied mode such as burn-in test, deterioration of components due to an overvoltage can be prevented.

Abstract: A bias circuit supplies a predetermined current to a next-stage circuit. The bias circuit comprises a first node having a first potential, a second node having a second potential, an output node electrically connected to the next-stage circuit, a main bias circuit electrically connected to the first node and the output node and for supplying the predetermined current from the first node to the output node, and an auxiliary bias circuit electrically connected to the first and second nodes and the output node and for equalizing the value of a current flowing from the first node to the output node to the value of a current flowing from the output node to the second node.

Abstract: A bias generation and distribution system in which bias potentials are generated at one main location within a logic circuit and then distributed throughout the logic circuit to MOS load devices, MOS load networks, other bias voltage conversion centers, and logic circuits is disclosed. The system generates a first bias voltage that provides a temperature compensated voltage that is utilized to bias MOS load devices and parallel MOS load networks. The first bias voltage generator includes either a reference MOS load device or a reference parallel MOS load network which determines the value of the first bias voltage. The reference MOS load network includes a switching network responsive to a first set of control signals. The first set of control signals may be adjusted to vary the value of the first bias voltage to compensate for process variations. The first bias voltage is distributed to either remote single load MOS devices or to remote parallel MOS load networks.

Abstract: A semiconductor integrated circuit used at a dropped external power voltage, comprises a voltage dropping circuit for receiving an external power voltage V.sub.CC and generating an internal power voltage V.sub.DD, a voltage comparison circuit for detecting the level of the internal power voltage V.sub.DD and controlling the operation of the power voltage dropping circuit based on the detected result, a switch circuit operating when the level of the internal power voltage V.sub.DD decreases, to forcibly generate the internal power voltage V.sub.DD from the external power voltage V.sub.CC, and a control circuit for activating the switch circuit.

Abstract: A reset circuit asserts, de-asserts and re-asserts a reset signal in response to a voltage applied between first and second nodes to which the reset circuit is connected. The reset signal includes a plurality of transistor switches connected together with positive feedback to achieve latching of the reset signal in either a high or a low state. The different inherent conductivity characteristics of the transistor switches causes the switches to begin closing when the applied voltage is at a first predetermined level and causes the transistor switches to begin opening when the applied voltage achieves a second predetermined lower level. The conductivity characteristics of the transistor switches cause the first and second predetermined levels to slightly vary over temperatures in the range of approximately -50.degree. C. to 150.degree. C., allowing reliable operation over a wide range of temperatures. The reset circuit may be integrated with the circuit which it resets.

Abstract: Improved controller circuitry for a switching power supply is disclosed. The switching power supply is of the type having a transformer having primary and secondary windings for generating an output voltage at the secondary winding, a power switch for driving the primary winding, and controller circuitry for activating the power switch. The improved controller circuitry includes an oscillator and frequency shift means. The oscillator generates PWM pulses having a predetermined frequency for use in activating the power switch. The frequency shift means gradually shifts the frequency of the PWM pulses at a shift rate in response to the output voltage decreasing to below a threshold level. In another embodiment, a controller for use in a switching power supply includes an oscillator for generating PWM pulses having a predetermined frequency which determine the switching condition of the supply.

Abstract: A MOS-type semiconductor clamping circuit includes a semiconductor substrate receiving a substrate potential, a well isolated electrically from the substrate potential, and MOS-type transistors formed in the well. Those transistors are connected with each other in series, each transistor has its gate connected to its drain, and a stable potential different from the substrate potential is applied to the well.

Abstract: A small and easy to fabricate programmable current source correction circuit. The correction circuit consists of a first current division circuit for establishing a reference current; a programmable correction current circuit for establishing the amount of correction current required; a second current division circuit for further reducing the reference current into smaller step or resolution; and a source-sink controlling circuit for determining whether the present invention is to operate as a current sink or current source. The present invention consists of substantially less number of circuit modules and can be fully integrated into a single chip which requires substantially smaller chip area and can operates at a substantially higher frequency compared to prior art.

Abstract: The output circuit according to this invention includes a first transistor (output transistor) provided between a first power terminal and an output terminal and receiving a first input signal into its gate via a voltage boosting circuit, a second transistor provided between a second power terminal and the output terminal and receiving a second input signal into its gate, a third and a fourth transistors connected in series between the gate of the first transistor and the output terminal with their respective gates connected to the second power terminal, and a fifth transistor provided between the first power terminal and the node of the third and fourth transistors with its gate connected to the gate of the output transistor.

Abstract: A wideband current multiplying divider circuit that produces an output current of any ratio to the input current has a first bipolar transistor and a first reference current source connected in series between a supply voltage and ground. A second bipolar transistor and a second reference current source are also connected in series between the supply voltage and around. A summation current source is connected at one side to ground and at the other side to a divided current path. A first resistor is connected in series with the station current source between a base of the first bipolar transistor and ground, and through which an input current can be connected to flow. A second resistor is connected in series with the summation current source between a base of the second bipolar transistor and ground, and through which an output current can be connected to flow.

Abstract: A voltage step-down circuit to be built in a highly integrated semiconductor IC chip, including a voltage divider and a voltage comparator. A divided output voltage V.sub.INT of the voltage divider and a comparison reference voltage V.sub.REF are applied to respective input terminals (-) and (+) of the voltage comparator. An output signal of the voltage comparator is supplied to a control signal generator section of the voltage divider to generate control pulses and to control the connection of capacitors of a voltage divider section of the voltage divider with the control pulses so as to supply the divided output voltage V.sub.INT to a load circuit. In this case, the capacitors are used as a voltage divider for generating a voltage for an internal circuit from an external power source voltage. Thus, power loss can be reduced and utilization efficiency of the capacitors is raised. Hence, the voltage step-down circuit is suitable for highly integrated semiconductor IC chip.

Abstract: A semiconductor device for a liquid crystal panel driving power supply in which a first reference voltage is converted in impedance by an operational amplifier to output it as a second reference voltage, comprising control means wherein, in a suitable fixed period during a period of displaying a liquid crystal, the current supply capacity of said operational amplifier is enhanced, and, in another period during said period of displaying a liquid crystal, the current supply capacity of said operational amplifier is lowered.

Abstract: A semiconductor integrated circuit device includes an aging mode control circuit, which detects the times of toggle of an external supply voltage (external Vcc) with a predetermined amplitude and generates an aging mode enable signal, and an internal voltage reduction circuit transmitting a voltage, which changes in accordance with change of the external supply voltage (external Vcc), onto an internal supply line in response to the aging mode enable signal. The semiconductor integrated circuit device enters an aging mode only when the external supply voltage oscillates a predetermined number of times with an amplitude not less than the predetermined amplitude. The semiconductor integrated circuit device does not unnecessarily enter the aging mode for an aging test, and facilely and surely enters the aging mode without utilizing a special timing relationship of external control signals.

Abstract: An internal supply voltage generation circuit, producing an internal supply voltage during a normal mode of operation and an external supply voltage during a burn-in mode of operation. The circuit including a plurality of fuses, the operation of which establishes the burn-in mode of operation, and controls a variable burn-in voltage level.

Abstract: In a code setting circuit wherein pad terminals are supplied with a voltage pulse to burn out corresponding thin-film resistors, first transistors of first conductivity type are adapted to be turned on in response to a turn-on pulse and second transistors of the first conductivity type are provided. The channel of each second transistor is connected in parallel with the channel of each first transistor between a voltage source and one of circuit nodes at which desired potentials are developed and a digital setting signal is generated corresponding thereto. Inverters are connected between the nodes and the gate terminals of the second transistors to keep the nodes at the desired potentials. Third transistors of second conductivity type are provided to prevent the voltage source from being coupled through the second transistors to the pad terminals. Blocking means are provided respectively corresponding to the third transistors and the pad terminals.

Abstract: An output driver that has and output current that is independent of supply voltage, load capacitance, temperature and processing variables as long as their variation from the norm is limited. This current limited output driver is specially adapted for gate array integrated circuits. The output driver uses two reference voltages to limit the output current and a pulldown transistor to ensure that logic low is achieved despite voltage, load capacitance, temperature and processing variations.

Abstract: A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

Abstract: An integrated circuit for generating a reset signal includes a circuit part having two first transistors being connected in series between terminals for a first and a second supply potential and each having a respective one of first and second mutually complementary channel types. A serial network acting as a voltage divider circuit is connected between the terminals for the first and the second supply potentials. The serial network includes at least two second transistors each having a respective one of the mutually complementary channel types and at least one element having a voltage drop during operation. The sources of the transistors of the first channel type are connected to the terminal for the first supply potential. The sources of the transistors of the second channel type are connected to the terminal for the second supply potential. The drains of the two first transistors form a first circuit node at which a reset signal is created in operation.

Abstract: The CMOS integrated circuit includes an oscillator including a capacitor having a polysilicon gate of one of several transistors as an electrode thereof and a diffused resistor located adjacent to the polysilicon gate, a counter circuit for calculating a frequency of the oscillator, a power-supply voltage control circuit for selecting an optimal power-supply voltage for transistors in accordance with the frequency, and a power-supply circuit for generating the optimal power-supply voltage.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.

Abstract: In a memory unit having a sense amplifier for reading data, the dependence of the memory cell current detection level of the sense amplifier on the power source voltage is restrained. A memory-unit sense amplifier includes a bias circuit (20, 21, 22) for generating an output which mitigates fluctuations in the power source voltage VDD; and a detection result output section (10, 15) which outputs a memory cell current detection result obtained for the purpose of obtaining the value of memory cell data and which has a Pch (P-channel transistor), to the gate of which the output of the bias circuit (20, 21, 22) is connected, whereby fluctuations in the source/gate voltage of the Pch 10 are mitigated so as to restrain the dependence of the memory cell current detection level on the power source voltage.

Abstract: A simple CMOS voltage reference circuit develops a reference voltage from the sum of the threshold voltages of a pair of complementary devices. In a p-type substrate a p-channel device is formed in an isolated n-type well, with the well tied to the source at the reference node. The drain is coupled to the drain of a complementary n-channel device. An additional p-channel device functions as a current source. The voltage reference circuit may be advantageously cascaded to improve stability and insensitivity to the power supply voltage.

Abstract: A dynamic random access memory in which data are successively read out responsive to a read command signal is provided with a boosting circuit device. The boosting circuit device has a pumping circuit operable with a first electric power source at a first voltage and responsive to a control clock signal for producing a second electric power at a second voltage boosted higher than the first voltage of the first electric power. A one-shot pulse generator is provided for generating a single pulse from which a pre-pumping pulse is produced to be included in the control clock signal. Thus, the control clock signal contains a pre-pumping pulse and a plurality of clock pulses following the pre-pumping pulse, so that the second voltage of the second electric power has been boosted higher than the first voltage of the first electric power by the pre-pumping pulse in advance of a successive readout of data.

Abstract: A push-pull output driver including two transistors in series, one transistor having its body bias controlled by logic circuitry commanded by the driver input. The driver has a pair of transistors in series, the transistor inputs being complementary to create a push-pull amplifier. A switching transistor is controlled by the inverse of the driver input signal and acts as a switch at the pull-up transistor well-tie. When the driver input is high, the switching transistor is off allowing the well-tie to the pull-up transistor to be connected to the driver output. When the input is low, the switching transistor turns on, switching the well-tie of the pull-up transistor to ground. By controlling the body bias of the pull-up transistor in this way, the switching speed of the output driver is significantly increased. When the output driver is in a disabled tri-state mode, the series transistors, and the switching transistor, are turned off.

Abstract: A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initialization, the logic circuit's input signal line is recoupled for normal operation.

Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.

Abstract: An input buffer particularly suitable for a semiconductor device includes a CMOS inverter for buffering an input signal which varies between first and second logic levels and producing an output signal at an output node thereof which is the logical inverse of the input signal, and a compensation circuit for compensating the output signal for fluctuations thereof which are due to fluctuations of a supply voltage. The CMOS inverter preferably includes a pull-up MOS transistor having a gate, a first electrode coupled to a supply voltage, and a second electrode, and a pull-down MOS transistor having a gate, a first electrode coupled to a reference voltage, and a second electrode.

Abstract: The low-power two-stage data output buffer (20,70) includes a two-stage switching circuit (50, 72) that drives an n-channel pull-up transistor (24) in two stages, thus only using current from the pumped high voltage supply during the second stage of the operation. The two-stage switching circuit (50, 72) first drives the pull-up transistor (24) with the supply voltage, V.sub.DD, then drives it with the pumped high voltage supply, V.sub.PP. A feedback circuit, coupled between the output node (28) and the two-stage switching circuit (50, 72), generates a path from the high voltage supply, V.sub.PP, to the n-channel pull-up transistor (24) in response to the supply voltage level appearing on the output node (28), and blocks the path from the high voltage supply, V.sub.PP, to the supply voltage.

Abstract: An apparatus and method for adjusting the effective threshold voltage of a MOS transistor is disclosed. Reference voltage generation circuitry is used for generating a first voltage signal. Threshold voltage monitoring circuitry that includes the MOS transistor is used for measuring the effective threshold voltage of the MOS transistor and for generating a second voltage signal. Feedback circuitry compares the first voltage signal to the second voltage signal and adjusts the effective threshold voltage of the MOS transistor so that the first voltage signal is substantially equal to the second voltage signal. The effective threshold voltage of the MOS transistor is adjusted by adjusting its source-body voltage potential.

Abstract: A constant voltage generator having a substrate voltage pumping circuit, a voltage pumping circuit and a single oscillator for generating pulses to which the substrate voltage pumping circuit and the voltage pumping circuit are commonly responsive, reducing current consumption of a semiconductor memory device during a stand-by state thereof.

Abstract: An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.

Abstract: A method and apparatus for transitioning between power supply levels. In one form, the present invention uses a circuit (22) in a data processing system (10) to smoothly and gradually transition a Power Output signal from a first power supply level to a second power supply level during operation. This transition from a first power supply level to a second power supply level must be smooth and gradual so that a circuit, such as oscillator circuit (12), which is receiving its power from Power Output, may continue to function properly during the transition. A Control signal, which can change back and forth between a first logic level and a second logic level, is used to select which power supply level will be provided as the Power Output.