Abstract: An integrated circuit comprises an assembly of switched capacitors operated under control of a system clock signal. It further comprises a signal driver for generating a binary output signal at an output pad. The system clock signal is suppressed for a certain time period after each transition of the output signal, thereby preventing voltage droop generated by the transition to introduce noise in the signals of the assembly of switched capacitors.

Abstract: A switch-capacitor loop filter is used to generate a control voltage for a voltage-controlled oscillator (VCO) in a phase lock loop (PLL). The switch-capacitor circuit works in a multi-phase manner including at least two non-overlapping phases: a sampling phase and a transfer phase. During the sampling phase, the current representing the phase difference between the reference clock and the feedback clock of the PLL is integrated by a sampling capacitor. During the transfer phase, the charge stored on the sampling capacitor is transferred to a load capacitor. The timing for controlling the switch-capacitor function is derived from the reference clock.

Abstract: The present invention provides an apparatus for enhancing Q factor of an inductor. The apparatus includes a negative resistance generator coupled to the inductor for providing a negative resistance, and a bias circuit coupled to the negative resistance generator for biasing the negative resistance generator.

Abstract: An example embodiment provides a method for calibrating an active RC filter and RC time constant calibrator for an active RC filter. The RC time contact calibrator includes a RC timer and a calibration code generator. The RC timer outputs a holding signal based on a comparison of a first output signal and a second output signal. The holding signal output by the RC timer causes a digital count value to be compared to a digital target value. The calibration code generator generates a slope control code and a flag signal based on the comparison of the digital count value and the digital target value and outputs the slope control code as a calibration code based on the flag signal. The slope control code controls the slope of the first output signal and the slope of the second output signal.

Abstract: According to an aspect of an embodiment, an apparatus comprises: a first current source and a second current source; a resistor connected between the first current source and a reference potential portion; a switched capacitor circuit having a variable capacitor, first switch and a second switch, the first switch and second switch alternately switching capable of charging a voltage to the variable capacitor and capable of discharging a electric charge of the variable capacitor; an integrating circuit having an output terminal and a first input terminal which is connected a portion between the second current source and the switched capacitor circuit, an integrating circuit for integrating a current from the portion and for exchanging into an output voltage of the output terminal; and a comparator for comparing the voltage between two end of the resistor and an output voltage of the integrating circuit.

Abstract: Provided is a switched capacitor resonator including at least one integrator circuit having a differential operational amplifier and a sub feedback circuit configured with a switched capacitor circuit. A main feedback circuit connecting main input and output terminals of the switched capacitor resonator to each other may be configured with the switched capacitor circuit. The main feedback circuit may be connected to the sub feedback circuit included in one of the integrator circuits. A capacitor of the main feedback circuit can serve as an integration capacitor connected between the input and output terminals of the differential operational amplifier. Consequently, it is possible to improve an operating speed by reducing a settling time constant of the integrator circuit.

Abstract: An analog buffer used in a source driver is provided. The analog buffer havs an input end, an output end, a transistor, first and second capacitors, first, second, third, fourth and fifth switches. The source and the drain of the transistor is coupled to the output end and receives a first voltage respectively. The first end of the first and the second capacitors are coupled to the gate of the transistor. The second end of the first and the second capacitors are coupled to the first end of the first, second and fourth switches and the first end of the third and fifth switches respectively. The second end of the first switch receives a second voltage. The second end of the second and third switches are coupled to the input end. The second end of the fourth and fifth switches are coupled to the output end.

Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: A switched capacitor circuit includes a capacitor that performs sampling, a first switch that is provided between the capacitor and an input terminal, and a second switch that is provided between the capacitor and an output terminal. The first switch and the second switch receive an input of a clock signal and turn on and off. The capacitor is a variable capacitance element in which the value of the capacitance changes in synchronization with the clock signal.

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: There is provided a charge domain filter device including a plurality of transconductors each of which converts an input voltage to a current and outputs the current and a filter unit that filters output signals from said plurality of transconductors by repeatedly charging and discharging a plurality of capacitors, wherein an impulse response of the charge domain filter device is obtained through convolution of a first impulse corresponding to a charge time length over which said capacitors are charged and a second impulse corresponding to each of said plurality of transconductors.

Abstract: The semiconductor integrated circuit device includes a plurality of decoupling cells that suppress power noise respectively, a plurality of power switches that connect the decoupling cells to a power line respectively, and a control circuit that controls the number of power switches selected from among the plurality of power switches and to be turned on according to power noise to be changed according to the operation state of each of internal circuits driven by a power supplied from the power line.

Abstract: A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A transconductance filtering device with a flexible architecture that can selectively present a different topology and/or order beginning with the same initial structure is disclosed. For example, depending on the communications standard detected, the elementary cells of the filtering circuit required to form the adapted filter are selected and connected in such a manner as to obtain the configuration desired for the filtering means. As an example, the filter may be for use with a wireless communications system forming, in particular, a cellular mobile telephone. The filter is configurable by means of at least two elementary cells of the same structure and of controllable interconnection means each having an open or closed state.

Abstract: A filter is configured to receive a filter charging signal and to produce a filter output signal based on the filter charging signal. The filter includes an element array with one or more switched elements which include an element and a switch configured to connect the element to or disconnect the element from the array, thereby altering a time constant of the filter. A comparator is configured to receive the filter output signal and a reference signal corresponding to a value of the filter output when the time constant has a defined value, and to generate a comparator output signal based on a comparison of the filter output signal to the reference signal. A controller is configured to receive the comparator output signal and, based on the comparator output signal, output an array control signal configured to adjust one or more switches of the one or more switched elements of the element array to alter the time constant such that a value of the time constant approaches the defined value.

Abstract: A filter circuit includes a voltage amplifier, a resistor, a capacitor, and an analog switch connected between the voltage amplifier and the capacitor. When the voltage amplifier is turned on, the analog switch is opened so that the capacitor is disconnected from the voltage amplifier. Thus, an output voltage of the voltage amplifier sharply increases to its steady state value, as soon as the voltage amplifier is turned on. When the output voltage of the voltage amplifier is fully stabilized, the analog switch is closed so that the capacitor is connected to the voltage amplifier. During the period of time when the analog switch is closed, the filter circuit is configured as an imperfect integrator circuit with filter characteristics that depend on a capacitance of the capacitor and a resistance of the resistor.

Abstract: A switched capacitor circuit employs a single operational amplifier to implement both an integrator and a summer. One input signal is routed to the input of the operational amplifier through (1) one or more integration branches, and (2) one or more first summing branches. A second input signal is routed to the input of the operational amplifier through one or more second summing branches. Each of the branches includes a capacitor and a number of switches controlled by different clock phases. The switched capacitor circuit may be single-ended or differential. The circuit may be used in an access terminal of a cellular communication system. The access terminal may operate under a code division multiple access (CDMA) communication standard.

Abstract: Provided is a switched capacitor type filter device having a steep characteristic with a small number of taps. The filter device includes positive polarity selecting switches (1311 to 1354), negative polarity selecting switches (1411 to 1454), positive read-out switches (1711 to 1754), negative polarity read-out switches (1811 to 1854), and a timing control unit (5). Thus, it is possible to read out a negative charge by controlling the polarity upon write-in and the polarity upon read-out to be identical or different. Accordingly, it is possible to set a negative coefficient as a filter weighting coefficient. This can realize an FIR filter having a steep characteristic.

Abstract: Switched capacitor notch filter circuits are disclosed.

Abstract: A filtering apparatus includes a main filter, a variation detection circuit, and a variation correction circuit. The variation detection circuit includes a reference filter having at least one resistor and at least one capacitor, detects a variation of CR-product based on the resistor and the capacitor of the reference filter in response to each of a plurality of reference signals having different frequencies from each other, and then outputs a variation detection signal indicating a detected result. The variation correction circuit corrects frequency characteristics of the main filter on the basis of the variation detection signal.

Abstract: There is provided a signal processing apparatus including a variable capacitor and a switching portion for switching the circuit mode between a sampling mode, in which the variable capacitor samples an input signal, a holding mode, in which a charge gained by sampling the input signal is held in the variable capacitor, and an output mode for outputting the charge stored in the variable capacitor, wherein the variable capacitor is provided with an input terminal through which the input signal is inputted in the sampling mode, a control terminal to which a first control signal which decreases the capacitance of the variable capacitor to a value below the capacitance in the sampling mode is inputted in the output mode, and a second control signal having a predetermined reference voltage is inputted in the holding mode, where an insulating layer is provided between the control terminal and the input terminal.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.

Abstract: This disclosure relates to techniques and architecture for summing, sampling, and converting signals associated with a capacitive feedforward filter using a quantizer.

Abstract: A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end amplifier is connected to receive a signal. The passive switched capacitor filter is connected to receive the amplified signal and has an output for providing a filtered signal. The switched capacitor filter has at least two sections that are each operable as a pole, wherein a first section of the at least two sections has sets of at least two stacked capacitors interconnected with a set of switches operable to amplify in input voltage provided to an input of the first section in response to operation of the set of switches; and a back end section connected to the output of the switched capacitor filter to receive the filtered signal.

Abstract: Tuning circuits and related method for tuning transconductance in a transconductor-capacitor (Gm-C) filter system are provided. In the tuning circuit, a periodic input signal with constant amplitude triggers a transconductor cell to charge/discharge a capacitor for building an output signal across the capacitor, and a magnitude-detection feedback circuit provides feedback to tune a transconductance of the transconductor cell according to a magnitude of the output signal, such that the magnitude of the output signal can be locked within a predetermined magnitude range. When the magnitude of the output signal is locked, the ratio between transconductance and capacitance is also locked to a predetermined value because the magnitude of the output signal is determined by a ratio between transconductance and capacitance.

Abstract: A loop filter (30) includes a first capacitor (31) provided between an input terminal for a current signal and a reference voltage, a switched capacitor circuit (32) provided between the input terminal and the first capacitor (31) and a second capacitor (33) provided in parallel to the first capacitor (31) and the switched capacitor circuit (32). In the switched capacitor circuit (32), when a third capacitor (321) is connected to the first capacitor (31), a fourth capacitor (322) is connected to the second capacitor (33). In the loop filter (30) having the above-described configuration, a capacitance value of the second capacitor (33) is set to be larger than respective capacitance values of the third and fourth capacitors (321 and 322).

Abstract: An object of the present invention is to provide a filter circuit which improves NF of a Gm-C filter. The filter circuit comprises a filter comprising at least one first operational transconductance amplifier whose mutual conductance varies depending on a first control signal and a first capacitor, a second operational transconductance amplifier whose mutual conductance is controlled by the first control signal, a third operational transconductance amplifier whose mutual conductance is controlled by a second control signal, and a second capacitor connected to output terminals of the first and second operational transconductance amplifiers and input terminals of the filter.

Abstract: Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers (OTAs), having a controllable transconductance Gm from a differential voltage input having first and second differential voltage input terminals to a single current output carrying a single phase current output signals, said first and second OTAs being provided with first and second control inputs, respectively, said filter input being coupled to the first differential voltage input terminal of said first OTA.

Abstract: A low pass filter includes a switchable resistor bank, a gain stage, and a capacitor bank. The resistors and capacitors switched into the circuit determine a cutoff frequency of the low pass filter. Frequency programmability may be obtained using the switchable resistor bank implemented as a parallel bank of binary weighted resistors. Further frequency programmability may be obtained using the switchable capacitor bank in conjunction with the switchable resistor bank. The resistor and capacitor processes in a semiconductor wafer are sufficiently accurate and repeatable so as to minimize any necessary calibration.

Abstract: A sample and hold circuit architecture samples using two capacitors that are cyclically switched between charge and discharge modes. The sample and hold circuit includes a buffer to receive an input signal to be sampled, a first sampling capacitor, a second sampling capacitor, and an amplifier. The first sampling capacitor is connected to the output of the buffer during the positive phase of a clock and across the feedback path of the amplifier during the zero phase of the clock. The second sampling capacitor is connected to the output of the buffer during the zero phase of the clock and across the feedback path of the amplifier during the positive phase of the clock. Neither the first sampling capacitor nor the second sampling capacitor is simultaneously connected to the buffer, the amplifier, or to each other.

Abstract: Disclosed is a calibration apparatus and method for programmable response frequency selecting elements. The calibration apparatus comprises a basic reference source, a programmable counter, a control logic unit, and a frequency to time constant converter. The programmable counter generates plural different frequency signals required by the frequency selecting elements with different frequency responses. The frequency to time constant converter determines a calibrated capacitance through the timing control signals generated by the control logic unit. This invention makes the process, temperature, and power supply variation for frequency selecting elements free. It allows the frequency selecting elements to have a high accurate, stable, and wide range programming of frequency responses. It is suitable for multi-standard applications. It greatly reduces the chip size, and significantly lowers down the cost for the applications.

Abstract: The invention provides a filter automatic adjustment apparatus and method, and a mobile telephone system, which realizes low power consumption while adjusting a characteristic frequency of a main filter having an adjustment function to a target frequency. The filter automatic adjustment apparatus includes: a phase difference detector 104 which outputs a signal having a duty ratio corresponding to a phase difference between an input signal and an output signal of a reference filter 103; a comparator 105 which converts the output signal of the phase difference detector into a rectangular wave; a counter 106 which consecutively counts a predetermined interval of the rectangular wave plural times; and a determination circuit 107 which selects a count value satisfying a predetermined criterion from the plural time count values, and the filter automatic adjustment apparatus adjusts the characteristic frequency of the main filter based on the selected count value.

Abstract: A method for tuning a tunable filter includes inputting a control signal to the tunable filter and tuning the configuration of the tunable filter according to the control signal. When the control signal is at any one of a plurality of predetermined states, a step size of a characteristic frequency of the tunable filter is positively correlated with the characteristic frequency of the tunable filter.

Abstract: Balanced offset compensation is provided for a differential amplifier circuit. Two sets of three switches are employed between respective inputs and outputs of the differential amplifier to shunt the outputs to the input terminals during auto-zeroing phase. By opening and closing different combinations of the switches during auto-zeroing and operation phases, differential degradation due to unbalanced leakage currents is substantially reduced.

Abstract: A voltage jitter suppression circuit and a method thereof are disclosed. The circuit is utilized for alleviating the voltage jitter phenomenon of an IC. Regardless of the circuit frequency and voltage, the voltage jitter phenomenon of the circuit can be improved significantly by utilizing the present invention.

Abstract: An analog switch used in a switched capacitor filter has N-channel and P-channel MOS FETs connected in parallel between input and output switch terminals, with capacitor charge currents being periodically produced from the output terminal. The filter derives an output signal with respect to a reference voltage and maintains the switch input and output terminal at the reference voltage, while respective substrate potentials of the N-channel and P-channel MOS FETs are fixed at the reference voltage, so that the analog switch does not produce an external flow of leakage current that can affect the output signal of the filter during each interval when the switch is open.

Abstract: A switched capacitor circuit includes an amplifier, a charging unit, an offset unit, and an integrating unit. The charging unit is coupled between an input node and a first node, and is for accumulating charge corresponding to an input signal during a sampling mode. The offset unit is coupled between the first node and an input of the amplifier, and is for maintaining the first node to be a virtual ground during an integrating mode. The integrating unit is coupled between the first node and an output of the amplifier, and is for receiving charge from the charging unit during the integrating mode.

Abstract: Provided is a poly-phase filter capable of removing an image frequency of a terrestrial digital multimedia broadcasting (T-DMB) receiver in a low intermediate frequency (IF) structure applied to a mobile communication terminal and a receiver having the poly-phase filter. The poly-phase filter includes: a calibration control block for generating first and second filter characteristic control signals which determine electrical characteristics of the filter in response to a control signal including instructions for changing the characteristics of the poly-phase filter and holding the changed values; and a poly-phase filter block for performing filtering on a plurality of input signals having different phases from each other in response to the first and second filter characteristic control signals. Accordingly, the poly-phase filter has advantages of having constant electrical characteristics regardless of changes in a manufacturing process and temperature and a high-performance image rejection function.

Abstract: A loop filter which is a component of a PLL circuit includes a switching element for switching a capacitance value which connects and disconnects a second capacitive element to a first capacitive element according to a natural angular frequency switching signal, and a switching element for switching a resistance value which short-circuits and opens between both ends of a resistance element according to a natural angular frequency switching signal in order to keep a damping factor at a constant value. It further includes an operational amplifier for charging the second capacitive element at the same potential as the first capacitive element when the second capacitive element is isolated from the first capacitive element.

Abstract: An apparatus and method are provided for tracking the poles of an integrated RC filter as well as the absolute value of a current source. A single tracking oscillator contains integrated elements such as a programmable resistor and fixed capacitor or a programmable capacitor and fixed resistor. The programmable element is programmed such that a particular response from the RC filter is achieved and the word used to program the programmable element is then supplied to other integrated RC filters having components that were fabricated at the same time as the RC filter in the tracking oscillator. A highly accurate external capacitor or resistor is supplied to determinate the absolute value of the programming element, which is used to program one or more current sources containing the programmable resistor.

Abstract: In one embodiment, a differential filter is configured using a differential operational amplifier (op-amp) with two feedback RC networks, each RC network coupled between a respective input and a respective output of the op-amp. Two capacitive elements may each provide mid-band positive feedback from a respective output of the op-amp to the midpoint of a respective corresponding resistive element, where each resistive element is coupled to a respective input of the op-amp. The mid-band positive feedback may operate to convert a first-order response of the filter to a second-order response. In one set of embodiments, dielectric absorption (DA) cancellation may be implemented with positive RC feedback from a divided version of a respective one of the op-amp outputs. For cascaded filters, DA cancellation may be implemented with positive RC feed-forward.

Abstract: A switched capacitor filter comprises three switched capacitor circuits. Each switched capacitor circuit has a capacitance. A first state that the capacitance is connected to an input end of a current signal, a second state that the capacitance is connected to an output end of a voltage signal, and a third state that the capacitance is connected to a side of a filter capacitance, are cycled. These three switched capacitor circuits are operated under an interleave control so that the first to third states do not each overlap between the three switched capacitor circuits.

Abstract: An integrated circuit providing high equivalent capacitance ranging from a few tens of picofarads to a few nanofarads is presented. The integrated circuit includes active integrated circuit components, requires no external capacitor, and is substantially insensitive to transistor current gain variations. The high capacitance integrated circuit can be advantageously used to provide, for example, timing delay and servo loop compensation.

Abstract: Gain control for delta sigma analog-to-digital converter. A method is disclosed for driving the input of an integrator in a delta-sigma converter having an amplifier with a non-inverting input, an output and a positive input connected to a reference voltage and an integration capacitor connected between the non-inverting input and the output. An input voltage is sampled at a first rate onto an input sampling capacitor and then charge is dumped from the input sampling capacitor to the non-inverting input of the amplifier at a second time and at the first rate. A reference voltage is sampled onto a feedback sampling capacitor at substantially the first rate, and charge stored on the feedback sampling capacitor is dumped to the non-inverting input of the amplifier at a second rate different than the first rate.

Abstract: A filter circuit includes a voltage amplifier, a resistor, a capacitor, and an analog switch connected between the voltage amplifier and the capacitor. When the voltage amplifier is turned on, the analog switch is opened so that the capacitor is disconnected from the voltage amplifier. Thus, an output voltage of the voltage amplifier sharply increases to its steady state value, as soon as the voltage amplifier is turned on. When the output voltage of the voltage amplifier is fully stabilized, the analog switch is closed so that the capacitor is connected to the voltage amplifier. During the period of time when the analog switch is closed, the filter circuit is configured as an imperfect integrator circuit with filter characteristics that depend on a capacitance of the capacitor and a resistance of the resistor.

Abstract: An integrating capacitor circuit for an integrating amplifier and related methods are disclosed that allow for efficient detection of currents or charges, particularly those produced by pixel cells in a detector image array. By placing a capacitor-connected field-effect-transistor (FET) in parallel with an integration capacitor and setting its gate voltage to a selected voltage level, the current or charge from the detector depletes the charge on the gate of the FET capacitor while integrating on the capacitor. In addition, the gate voltage level can be adjusted to modify the current depleting characteristics of the capacitor-connected FET. The resulting operation of this integrating circuitry provides significant resulting advantages for the integrating amplifier.

Abstract: A semiconductor device includes a memory and a power voltage interrupter configured to interrupt an external power voltage applied to circuitry of the semiconductor device responsive to a Deep Power Down (DPD) command signal generated in a DPD mode of the memory. A power voltage shifter is configured to shift a power voltage in the circuitry to a specific level responsive to the DPD command signal.

Abstract: A switched-capacitor ripple-smoothing filter includes a first pair of capacitors. The filter is configured such that either capacitor in the first pair may be reset and have a terminal coupled to a first input port and such that the remaining capacitor in the first pair is isolated from the first input port and has the terminal coupled to a first output port while the other capacitor is being charged. The filter further includes a second pair of capacitors, the filter being configured such that either capacitor in the second pair may be reset and have a terminal coupled to a second input port and such that the remaining capacitor in the second pair is isolated from the second input port and has the terminal coupled to a second output port while the other capacitor in the second pair is being charged. Advantageously, the filter is configured such that the capacitors in the first and second pair are reset responsive to the assertion of a single reset signal.

Abstract: A circuit for selectively controlling signal baseline and frequency emphasis. An amplifier with selectively controllable feedback circuitry allows higher frequency components of a signal to be emphasized over lower frequency components while also allowing control over the baseline of the signal. Additionally, a multiplexed video signal interface provides a multiplexed component video signal which includes component video signals with OSD data and user-controllable contrast, video gain and signal baseline, along with the ability to individually control such signal components.