Abstract: A level shifter including a differential input stage including first and second transistors having respective first terminals, respective control terminals configured to receive a differential input signal, and respective second terminals connected in common to a first voltage; a breakdown voltage controller including third and fourth transistors having respective first terminals, respective second terminals connected to respective first terminals of the first and second transistors, and respective control terminals configured to receive a bias signal, and a load stage comprising fifth and sixth transistors having respective first terminals connected to respective first terminals of the third and fourth transistors, respective control terminals that are cross coupled, and respective second terminals connected to a second voltage is disclosed. A bias voltage applied to bulks or bodies of the first through the fourth transistors equals or substantially equals the first voltage.

Abstract: The present disclosure relates to a differential sense amplifier comprising first and second cross-coupled inverters with first and second complimentary storage nodes. A first current control element changes a current through the first cross-coupled inverter based upon an output of a second cross-coupled inverter, and a second current control element changes a current through the second cross-coupled inverter based upon an output of the first cross-coupled inverter. Other devices and methods are also disclosed.

Abstract: The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit.

Abstract: A sense amplifier is provided. The sense amplifier comprises a first and second cross-coupled transistor pairs, a first and second current sources, a first digital input transistor, and a second digital input transistor. The first and second ends of the first cross-coupled transistor pair are coupled to an operating voltage, the first and second back gate ends of the first cross-coupled transistor pair are coupled to a first and second output ends respectively. The first and second back gate ends of the first cross-coupled transistor pair are coupled to a first and second output ends respectively, and the first and second ends of the first cross-coupled transistor pair are coupled to a first digital input end and second digital input end respectively.

Abstract: An input/output sense amplifier includes: a data input unit configured to amplify data using a driving voltage and to output the amplified data, and a latch unit configured to latch and output an output signal of the data input unit to an output terminal.

Abstract: Disclosed is a comparator including a switching element, a differential pair, and a positive feedback part, the positive feedback part including a first CMOS inverter and a second CMOS inverter, the first CMOS inverter including a first element for providing a potential difference between a first PMOS transistor and a first NMOS transistor, the second CMOS inverter including a second element for providing a potential difference between a second PMOS transistor and a second NMOS transistor, a higher potential side of the first element being connected to a gate of the second NMOS transistor, a lower potential side of the first element being connected to a gate of the second PMOS transistor, a higher potential side of the second element being connected to a gate of the first NMOS transistor, and a lower potential side of the second element being connected to a gate of the first PMOS transistor.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.

Abstract: Sense amplifiers including bias circuits are described. Examples include bias circuits having an adjustable width transistor. A loop gain of the bias circuit may be determined in part by the adjustable width of the transistor. Examples of sense amplifiers including amplifier stages configured to bias an input/output node to a reference voltage.

Abstract: Apparatus and methods for voltage comparison are provided. In one embodiment, a comparator includes a first input transistor having a gate configured to receive a first input voltage and a second input transistor having a gate configured to receive a second input voltage. The first and second input transistors can be used to compare the first input voltage to the second input voltage. Additionally, the comparator further includes a first Miller capacitor electrically connected to a drain of the first input transistor and a second Miller capacitor electrically connected to a drain of the second input transistor. Furthermore, first and second inverting amplification circuits are electrically connected across the first and second Miller capacitors, respectively, so as to increase the effective capacitance of the capacitors. The first and second Miller capacitors can be used to extend the comparator's integration time, thereby enhancing the performance of the comparator.

Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-bold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: A constant switching current flip-flop includes a latch circuit that provides latch outputs of the flip-flop, whereby the latch outputs are reset to zero at the beginning of each clock cycle to eliminate pattern dependent switching currents. The latch circuit is reset responsive to control signals provided without significant delay.

Abstract: A sense amplifier circuit includes a first transistor and a second transistor of a first type, a first transistor and a second transistor of a second type, a first resistive device, and a second resistive device. A first end of the first resistive device is coupled to a first data line. A second end of the first resistive device is coupled to a drain of the first transistor of the second type and a gate of the second transistor of the first type. A first end of the second resistive device is coupled to a second data line. A second end of the second resistive device is coupled to a drain of the second transistor of the second type and a gate of the first transistor of the first type.

Abstract: A reference voltage circuit corrects for bandgap voltage shifts induced during fabrication. The reference voltage circuit generates a reference voltage using first and second base-emitter pairs. The reference voltage circuit sums the voltage across the first base-emitter pair with a difference voltage. During a first time period, the difference voltage is the voltage across the first base-emitter pair minus the voltage across the second base-emitter pair, and during a second time period, the difference voltage is the voltage across the second base-emitter pair minus the voltage across the first base-emitter pair.

Abstract: A semiconductor device includes a first driver circuit for supplying a first potential to a first power supply node of the sense amplifier, second and third driver circuits for supplying a second potential and a third potential to a second power supply node of the sense amplifier, and a timing control circuit for controlling operations of the first to third driver circuits. The timing control circuit includes a delay circuit for deciding an ON period of the third driver circuit. The delay circuit includes a first delay circuit having a delay amount that depends on an external power supply potential and a second delay circuit having a delay amount that does not depend on the external power supply potential, and the ON period of the third driver circuit is decided based on a sum of the delay amounts of the first and second delay circuits.

Abstract: A signal operating circuit includes: a loading device, having a loading value, wherein the loading value is deviated from a predetermined loading value by a loading deviation value; an input stage coupled to the loading device, for converting an input signal into an output signal according to a controlling signal; a latching stage coupled to the loading device and the input stage for latching the output signal according to the controlling signal; and a controlling circuit coupled to the latching stage for adjusting an operating current flowing through the latching stage and an operating current flowing through the input stage to compensate the loading deviation value according to the loading deviation value of the loading device.

Abstract: Sense amplifier-type latch circuits are provided which employ static bias currents for enhancing operating frequency. For example, a sense amplifier-type latch circuit includes a latch circuit that captures and stores data during an evaluation phase of the sense amplifier-type latch circuit, and outputs the stored data to differential output nodes. An input differential transistor pair has drains connected to the latch circuit and sources commonly connected to a coupled source node. A static bias current circuit is connected to the coupled source node to provide a static bias current which flows through the differential transistor pair and cross-coupled inverters of the latch during a precharge phase. A switch device, which is connected to the coupled source node, is turned off during the precharge phase and turned on during the evaluation phase by operation of a clock signal to increase current flow through the differential transistor pair.

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract: An apparatus for comparing differential input signal inputs is provided. The apparatus comprises a CMOS sense amplifier (which has having a first input terminal, a second input terminal, a first output terminal, and a second output terminal), a first output circuit (which has a first load capacitance), a second output circuit (which has a second load capacitance), and an isolation circuit. The isolation circuit is coupled between the first output terminal of the CMOS sense amplifier and the first output circuit and is coupled between the second output terminal of the CMOS sense amplifier and the second output terminal of the CMOS sense amplifier. The isolation circuit isolates the first and second load capacitances from the CMOS sense amplifier.

Abstract: A sense amplifier for use in a memory array having a plurality of memory cells is provided. The sense amplifier provides low power dissipation, rapid sensing and high yield sensing operation. The inputs to the sense amplifier are the differential bitlines of an SRAM column, which are coupled to the sense amplifier via the sources of two PMOS transistors. A CMOS latching element comprised of two NMOS transistors and the aforementioned PMOS transistors act to amplify any difference between the differential bitline voltages and resolve the output nodes of the sense amplifier to a full swing value. The latching element is gated with two additional PMOS transistors which act to block the latching operation until the sense amplifier is enabled. One or more equalization transistors ensure the latch remains in the metastable state until it is enabled. Once the latch has resolved it consumes no DC power, aside from leakage.

Abstract: Determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: A switching circuit includes a first input stage having an input for receiving a first input signal, an output, and a power terminal for receiving an increasing analog current, a second input stage having an input for receiving a second input signal, an output, and a power terminal for receiving a decreasing analog current, and an output node coupled to the outputs of the first input stage and the second input stage for providing a switched output signal. An output stage is coupled between the first and second input stages and the output node. The first and second input stages are operational amplifiers.

Abstract: An apparatus includes a first sensing circuit operative to drive a node with a first sample of an input signal during a first phase of a clock signal. The apparatus includes a second sensing circuit operative to drive the node with a second sample of the input signal during a second phase of the clock signal. An output signal on the node includes the first and second samples and has a bit rate that is N times the rate of the clock signal. N is an integer greater than one. In at least one embodiment of the apparatus, during the second phase of the clock signal, the first sensing circuit provides a high impedance to the node, and during the first phase of the clock signal, the second sensing circuit provides a high impedance to the node.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.

Abstract: A current-sense amplifier with low-offset adjustment and a low-offset adjustment method thereof are disclosed. The current-sense amplifier includes a sensing unit, an equalizing unit and a bias compensation unit. The sensing unit includes a sense amplifier, a latch circuit, a first precharged bit line, and a second precharged bit line. The equalizing unit is electrically connected to the first and the second precharged bit line for regulating a voltage of the first precharged bit line and a voltage of the second precharged bit line to the same electric potential. The bias compensation unit is electrically connected to the sense amplifier for compensating an input offset voltage of the current-sense amplifier.

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Abstract: A dynamic comparator with background offset calibration is provided. The dynamic comparator includes at least one input differential pair, a first back-to-back inverter, a second back-to-back inverter, and an integrator. The input differential pair includes two current branches, wherein one of the current branches has an input referred offset. The first back-to-back inverter determines which one of the two current branches has the input referred offset in response to a first clock signal and generates two control signals accordingly. The integrator generates two calibration voltages for the input differential pair in response to the two control signals, so as to calibrate the input referred offset. The second back-to-back inverter determines a difference between two input signals received by the input differential pair after the input referred offset is calibrated in response to a second clock signal and outputs two comparison signals accordingly.

Abstract: An example of a circuit for generating high-voltage switching at an output terminal of the circuit includes a pair of n-type metal oxide semiconductor (NMOS) transistors responsive to input signals to generate a first voltage signal in a preset mode. The circuit also includes a predefined number of n-type cascode stages coupled between the output terminal and the pair of NMOS transistors to enable propagation of the first voltage signal to the output terminal. Further, the circuit includes a predefined number of p-type cascode stages coupled to the output terminal to enable propagation of the first voltage signal to an input voltage supply to the circuit. Furthermore, the circuit includes a first pair of cross-coupled p-type metal oxide semiconductor (PMOS) transistors coupled to the input voltage supply. The circuit includes a pair of PMOS transistors, coupled between the first pair of cross-coupled PMOS transistors and the p-type cascode stage.

Abstract: A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.

Abstract: The present invention is directed for a comparator circuit used in an analog-to-digital converter, and more particularly, for a low power consumption low kick-back noise comparator circuit for an analog-to-digital converter, which can significantly reduce kick-back noise generated in a signal input stage due to a signal regeneration method employed in a signal comparing operation and can efficiently reduce power consumption.

Abstract: A driving apparatus having driving circuits formed to correspond to driven circuits arranged on a circuit board. Each driving circuit includes a driving control unit for driving the corresponding driven circuit, a reference voltage generation unit for generating a reference voltage according to a temperature of the corresponding driven circuit, a control voltage generation unit for generating, based on the reference voltage supplied from the reference voltage generation unit, a control voltage for driving the corresponding driven circuit, the control voltage generation unit supplying the generated control voltage to the driving control unit, a switch device formed between the control voltage generation unit and the reference voltage generation unit, and a switch control unit for driving the switch device based on an inputted control signal. The control voltage generation unit is connected to the reference voltage generation unit of another of the driving circuits via the switch device.

Abstract: The present disclosure relates to reduction in the effect of kickback in comparators by means of charge injection implemented by means of voltage controlled switches with attributes similar to those of an input differential pair. The voltage controlled switches produce charge to neutralize the charge loss during latching of inputs in the comparator.

Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Abstract: A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the latched comparator circuit. Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors operatively connected between the first and the second output terminal for providing a positive feedback in the latched comparator circuit. In addition, the latched comparator circuit comprises a reset terminal for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal.

Abstract: A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.

Abstract: During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

Abstract: Described herein are methods and apparatuses for achieving a desired duty cycle on an output of a PLL. According to one embodiment, a method is described, including generating a single ended clock signal from a differential common mode clock signal using a limiting differential amplifier, wherein the single ended clock signal has a duty cycle, generating a differential bias current signal in response to the duty cycle of the single ended clock signal, and correcting the duty cycle of the single ended clock signal to a desired duty cycle by applying the differential bias current signal to the limiting differential amplifier.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: A receiver circuit for sensing and transmitting input data in sync with a plurality of clock signals having mutually different phase sequentially enabled comprising a sense amplifier configured to receive, as offset voltages, first signals which can be obtained by amplifying the input data in sync with a first clock signal of the plurality of clock signals, being driven in sync with a second clock signal enabled subsequently to the first clock signal, and outputting second signals, and a discharging controller configured to control a discharging speed of the sense amplifier according to the offset voltages to control a driven speed of the sense amplifier.

Abstract: A circuit includes a differential circuit that generates a differential output signal at first and second output nodes. The circuit also includes a first variable capacitor coupled to the first output node of the differential circuit, and a second variable capacitor coupled to the second output node of the differential circuit. A control circuit controls capacitances of the first and the second variable capacitors in response to a measurement of the differential output signal.

Abstract: A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down input signal, respectively, converts the first current and the second current into an up compensating signal and a down compensating signal having electric potentials compensating the offset voltage, and amplifies the up compensating signal and the down compensating signal to output an up output signal and a down output signal.

Abstract: A comparator used in a parallel-type A/D converter, wherein a comparator 100 includes reset transistors mra and mrb. When the comparator 100 is in the Reset state, the inverted signal /CLK of the clock signal is given to the PMOS reset transistors mra and mrb so as to forcibly reset both of the voltages at two internal nodes Va and Vb being a differential pair to a predetermined reset voltage by the reset transistors mra and mrb. The inverted signal /CLK of the clock signal is produced with a predetermined delay. Thus, when the comparator 100 is in the Reset state, the point in time at which to cancel the reset of the internal nodes Va and Vb is delayed from that at which the comparator performs a comparison operation. Therefore, even if the frequency of the clock signal and the frequency of the analog input signal are high, the voltages at the internal nodes forming a differential pair are well-balanced when the comparator is in the Reset state, thus improving the voltage comparison precision.

Abstract: A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input buffer which is synchronized with and enabled by the clock signal, senses a difference between a second reference voltage and the input data signal, and amplifies the sensing result; and a phase detector which detects a difference between a phase of output signals of the first and second input buffers, and outputs a signal corresponding to the detection result. The first and second reference voltages may respectively be higher and lower than a median voltage of the input data signal. Thus, a single input data signal is advantageously used and a wide input data eye is provided.

Abstract: One embodiment of the present invention sets forth a sense amplifier flop design that is tolerant of process variation. Specific staging of signal transitions through the sense amplifier flop circuit eliminate operational phases involving short-circuit currents between n-channel field-effect transistors (N-FETs) and p-channel field effect transistors (P-FETs) in a complementary-symmetry metal-oxide semiconductor process. By eliminating short-circuit currents between N-FETs and P-FETs within the sense amplifier flop, a large variation in conductivity ratio between N-FETs and P-FETs may be tolerated by the sense amplifier flop. This tolerance to conductivity ratio translates to a tolerance for process variation by the sense amplifier flop circuit.

Abstract: A flip-flop includes a sense amplifier stage and a latch stage. The sense amplifier includes a first P type transistor and generates a first sensed signal and a second sensed signal in a first node and a second node, respectively. When the first P type transistor is turned on, the first node is connected to the second node. The latch stage generates a first output signal and a second output signal according to the first and the second sensed signals.

Abstract: The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched digital control signals in the conventional art. In addition, embodiments of the invention implement each equalizer with a single sense amplifier based flip flop (SAFF) to reduce circuit size and power consumption.

Abstract: In a comparator, a differential amplifier has a pair of transistors receiving a signal to be compared for differential amplification, and a current mirror load circuit for outputting a differential output signal in accordance with the relationship in magnitude of the signal to be compared. A latch circuit has inversion amplifiers for amplifying the differential output signal. One inversion amplifier has its input interconnected to an output of the other inversion amplifier and vice versa. The comparator still further includes a transistor for equalizing signals of the differential amplifier, a transistor for enabling the inversion amplifiers to be active, and a constant current source for reducing a current flowing from a supply voltage to the ground when the inversion amplifiers are active.