Abstract: A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals.

Abstract: System for generating a reference current in a semiconductor device. The reference current is compared to an internal device current generated by an internal device circuit to verify operation of the device. The system includes a current generator that generates the reference current and is located within the semiconductor device, and a bias generator that is coupled to the internal device circuit. The bias generator generates a back bias current to offset variations to the reference current.

Abstract: A mixer driver circuit including a differential pair, a differential current supply and a switched current sink. The differential pair has a differential input for receiving a differential input signal. The differential current supply provides a differential output and switches in response to switching of the differential pair to provide a differential output current. The switched current sink biases the differential current supply and sinks current to drive the differential output signal. The differential pair may be a resistive-loaded differential pair of transistors biased by a constant current sink. The differential current supply may include a pair of emitter follower buffers. The mixer driver may further include a pair of constant current sinks and a second pair of emitter follower buffers, where the second pair of emitter follower buffers is biased by the pair of constant current sinks and provides a voltage level shifting drive for the switched current sink.

Abstract: A comparator comprises a cross-coupled regenerative latch, a circuit connected to the cross-coupled regenerative latch and a clocking circuit. The cross-coupled regenerative latch regenerates, during a latching mode, a signal which is indicative of a difference between two input signals. The circuit connected to the cross-coupled regenerative latch operates as a voltage follower during an acquisition mode and as a cascode amplifier stage during the latching mode. The clocking circuit switches the comparator from the acquisition mode to the latching mode and vice versa. The comparator eliminates the extraneous loading from the positive feedback when the regeneration takes place, so that a very fast regeneration time constant is obtained.

Abstract: A sense amplifier that eliminates or substantially attenuates transients at its output node by isolating the output node from the bitline. The sense amplifier incorporates a sense line transistor between the bitline and the output latching circuit in order to strengthen the voltage value at the output node such that it is not affected by the impedance of the bitline. The sense amplifier also consumes less power and is faster because the bitline does not have to be discharged or precharged by the output driver.

Abstract: A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs.

Abstract: A rectifier circuit with a transistor having first and second electrodes coupled between an input and output of the rectifier circuit. A latch has an output connected to a control node of the transistor, and has first and second inputs connected to the input and output of the rectifier circuit, respectively. The invention provides a self-contained, self-powered, self-regulated low turn-on voltage diode-rectifier with maximum current (on-state conductance) when forward-biased. This circuit can be inserted between any two nodes and behaves like a Schottky diode.

Abstract: A system for minimizing the effect of clock skew in a bit line write driver includes a first control circuit coupled to the bit line write driver; and a second control circuit coupled to the bit line write driver. The bit line write driver outputs a first output signal and a second output signal. A method of minimizing the effect of clock skew in a bit line write driver includes outputting a first signal and a second signal from the bit line write driver; controlling the outputting of the second signal from the bit line write driver based on a feedback of the first signal; and controlling the outputting of the first signal from the bit line write driver based on feedback of the second signal.

Abstract: A CMOS cross-coupled sense amplifier circuit that detects and amplifies data of memory cells is disclosed. The sense amplifier having a favorable sense margin even if a mismatch occurs in transistors constructing the sense amplifier in the fabricating process. The sense amplifier includes voltage control transistors that control the voltage between drain and source of the NMOS transistors in the inverters connected in a latch type between output nodes at an identical phase during a pre-charge step and during an initial operation step. The channels of the voltage control transistors are connected between the drain and source of the NMOS transistors in the inverters for being controlled by a sense amplifier signal.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: A sense-amplifying circuit 10 which comprises a pair of inverters (TP0, TN0, TP1 and TN1), wherein an output of each inverter is connected to an input of the other inverter, drains of sensing transistors TN2 and TN3 are respectively connected to each source of the pair of inverters in series, the gates of both sensing transistors TN2 and TN3 are connected to differential input signal lines 12 and 14, and the sources of both sensing transistors TN2 and TN3 are connected through a common node with a transistor TN4, which works not only as a constant current source but also as an operation switch for the sense-amplifying circuit.

Abstract: The present invention provides a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.

Abstract: A CMOS cross-coupled sense amplifier circuit that detects and amplifies data of memory cells is disclosed. The sense amplifier having a favorable sense margin even if a mismatch occurs in transistors constructing the sense amplifier in the fabricating process. The sense amplifier includes voltage control transistors that control the voltage between drain and source of the NMOS transistors in the inverters connected in a latch type between output nodes at an identical phase during a pre-charge step and during an initial operation step. The channels of the voltage control transistors are connected between the drain and source of the NMOS transistors in the inverters for being controlled by a sense amplifier signal.

Abstract: A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: A differential circuit to be used as a latch-up for asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) devices. The differential circuit includes an asymmetric-DGCMOS device having the weak gates tied to input circuitry and strong gates that are used in cross-coupling.

Abstract: An input circuit according to the present invention has a data input means for the input of input data; a data latch means for latching the input data; a reset means for resetting the data latch means; a clock synchronization means for synchronizing the input of the input data to the data input means; and a latch enhancement means for blocking feedthrough current by functioning complementarily to the reset means, and enhancing the latching operation of the data latch means.

Abstract: A sense amplifier includes a pair of differential input terminals and a pair of differential output terminals. Each of a pair of precharge circuits connects a respective one of the differential output terminals to precharge potential and has a clocking input. The precharge circuits maintains the respective differential output terminals at ground in response to a precharge state of a signal at the clocking input. The sense amplifier also may include a pair of evaluation circuits, each connecting a respective one of the differential output terminals to an evaluation potential and coupled to a respective one of the differential input terminals. The evaluation circuits may transition the respective output terminal to an evaluation voltage in response to an evaluation state of a signal at the respective differential input terminal.

Abstract: An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an “on” state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.

Abstract: A sense amplifier in which its output nodes provide a full voltage swing between the supply and return nodes. The sense amplifier further includes a reset circuit to selectively equalize the first and second output nodes. An output of the sense amplifier is coupled to either a digital logic gate or a flip-flop to receive the full swing. Each field effect transistor (FET) of the input pair in the sense amplifier is either zero body biased or forward body biased, so that a bulk-source junction of each FET is either zero biased or forward biased.

Abstract: The present invention provides a single-ended signal detection circuit (sense-amplifier) which exhibits a little power consumption and performs a high speed operation. A sense-amplifying circuit (100) detects a signal on one signal line to amplify the detected signal. A sensing switch composed of first and second switches (13, 14), each of which is connected to a source terminal of the sense-amplifying circuit and to a constant current source (15), the first switch being connected to a signal line (10) and the second switch being connected to a reference potential (Vref), wherein a driving force of the first switch is larger than that of the second switch.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: A high-speed sense amplifier includes a pair of cross-coupled inverters coupled to intermediate nodes and then to differential inputs nodes by a control circuit. The intermediate nodes are coupled together by a accelerator transistor that forms a current path when the sense amplifier is placed in a sensing state to provide parallel discharge paths for one or the other of output nodes. During precharge, the accelerator transistor operates to equalize the intermediate nodes to ready them for the next sense phase.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: A semiconductor memory device which comprises a memory cell array having a plurality of memory cells, complementary data bus lines connected to said memory cells in said memory cell array and a sense amplifier. The sense amplifier is connected to the memory cells through the complementary data bus lines and amplifies a difference between current values on said complementary data bus lines associated with a logical value stored in the memory cell. The sense amplifier has a positive feedback circuit having a plurality of differential pairs constructed by transistors.

Abstract: According to an embodiment of the invention, a circuit is provided that includes a first differential set and a second differential set each having a first and a second input node and a first and a second output node. The first differential set is referenced to a first supply node, and the second differential set is referenced to a second supply node. The first input node of the first differential set is coupled to the first input node of the second differential set. The second input node of the first differential set is coupled to the second input node of the second differential set. A first load element is cross coupled between the second output node of the second differential set and the first output node of the first differential set. A second load element is cross coupled between the second output node of the first differential set and the first output node of the second differential set.

Abstract: A high voltage switch circuit according to the present invention includes PMOS transistors having one conductive terminals receiving a high voltage, NMOS transistors having one conductive terminals receiving a ground voltage, and transistors for voltage control. The transistors for voltage control have their gates supplied with gate control signals of which potential change in accordance with the level of the high voltage. Thus, a high voltage switch circuit which can normally operate independent of the voltage level can be provided.

Abstract: The input buffer circuit includes an input stage providing a switching point voltage based on a predetermined switching point set between a first and second reference voltages that maximizes the high and low noise margins of the input buffer. The input buffer circuit further includes an output stage. The output stage is coupled to the input stage. The output stage receives the switching point voltage from the input stage and amplifies the switching point voltage to a full logic level voltage.

Abstract: A device to sense changes in current level almost instantaneously and convert those current levels, almost instantaneously, into voltage levels that may be used by a microprocessor for logical and mathematical operations. This device employs a current conveyer to receive two inputs representing current levels. Once a sufficient difference in current levels is detected by the current conveyer, the current from each input is passed to a P-sense amplifier that converts the current to an equivalent voltage level and amplifies that voltage level. Thereafter, two outputs are generated reflecting an amplified voltage of the current input.

Abstract: A differential receiver circuit includes: a current source 20; a differential pair 22 and 24 coupled to the current source 20; a first transistor 26 coupled to a first branch of the differential pair 22 and 24; a second transistor 28 coupled to a second branch of the differential pair 22 and 24, the first and second transistors 26 and 28 are cross coupled; a third transistor 54 coupled in series with the first transistor 26; a fourth transistor 56 coupled in series with the second transistor 28; a fifth transistor 30 coupled in parallel with the first and third transistors 26 and 54; and a sixth transistor 32 coupled in parallel with the second and fourth transistors 28 and 56.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: Integrated circuit memory devices according to the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor is included that has a source electrically connected to a drain of the second sensing transistor and a gate of the first sensing transistor. A switching transistor is responsive to an enable signal and has a source electrically coupled to a drain of the first load transistor and a drain of said second load transistor. A first load circuit provides a variable impedance across the source and the drain of the first load transistor in response to at least a first sense signal.

Abstract: A clocked sense amplifier flip flop includes at least one keeper unit to prevent the occurrence of a floating data node.

Abstract: A common-mode detection circuit for measuring a common-mode signal between two complementary signals is disclosed. The common-mode detection circuit includes a first signal divider circuit and a linearizer. The signal divider circuit includes a pair of impedances coupled to define a measurement node and respective first and second inputs. The divider further includes a pair of active buffer amplifiers having respective first and seconds outputs for coupling to the signal divider first and second inputs. The linearizer includes respective first and second inputs cross-coupled to the respective second and first buffer amplifier outputs and is operative to maintain both of the buffer amplifiers in a relatively constant operational state.

Abstract: A comparator circuit includes a regenerative stage that uses a relatively small quiescent current combined with a relatively large dynamic current to charge a common-source node in the regenerative stage. The quiescent current helps maintain the common-source node in the regenerative stage near a desired charged level. The comparator circuit can also include an input isolation circuit to eliminate charge kick-back to the input signal lines.

Abstract: The present invention provides a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.

Abstract: Single input receivers and “pseudo differential” amplifiers can conserve scarce chip surface area and still provide fast response times in a low power CMOS environment. A first embodiment includes a single ended receiver. The single ended receiver includes a pair of cross coupled inverters. Each of the inverters includes a pair of output transmission lines. A single signal input node coupled to a source region for one of the pair of cross coupled inverters and to a current mirror such that the single ended receiver is able to convert a single ended input current received at the single signal input node into a differential input signal. A second embodiment includes a pseudo differential amplifier. The pseudo differential amplifier includes a pair of cross coupled transistors. The pseudo differential amplifier includes a pair of signal output nodes.

Abstract: An output circuit is driven by a first differential amplification circuit having an N-channel differential amplification stage that compares a reference voltage VREF with an input signal IN, and a second differential amplification circuit having a P-channel differential stage. An output of the first differential amplification circuit is given as the gate voltage of P-channel MOS transistors in the output circuit, and an output of the second differential amplification circuit is given as the gate voltage of N-channel MOS transistors in the output circuit. This realizes an input buffer with reduced error operations even under threshold voltage variations caused by process variations and others.

Abstract: A low voltage differential circuit is described herein including a complementary logic tree having first, second and third inputs and two outputs, the logic tree for performing a desired logical function on signals received the the first input, thereby opening a pathway for current flow between at least one of the following: the second input and the first output, the second input and the second output, the third input and the first output, the third input and the second output.

Abstract: A high voltage CMOS switch circuit having an arrangement of device connections such that the individual transistor devices are substantially the same size, improving performance while reducing size and providing breakdown protection. The circuit switches a high voltage to the output based on a low voltage input. The circuit is ratio-less and self-biased, capable of operating a very low supply voltage compared to the state of the art.

Abstract: A data transfer arrangement. The data transfer arrangement includes two active pull up/active pull down bus drivers and a voltage precharge source. A differential bus is coupled to the bus drivers and to the voltage precharge source. A latching sense amplifier is coupled to the differential bus and serves as the bus receiver. The bus drivers operate in a precharge phase and a data transfer phase. The bus receiver operates in an analogous but opposite manner, i.e., when the bus drivers are in the precharge phase, the bus receiver is in the data transfer phase and when the bus drivers are in the data transfer phase, the bus receiver is in a precharge phase.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: An electronic circuit configuration having two lines and a detector device which is allocated to the two lines. The circuit configuration detects a potential difference on the lines and controls a change in the line potentials in response to this. Each line is allocated a switch that is driven by the detector device and, after actuation by the detector device, connects the potential of an associated line to a reference-ground potential that is coupled to the switch.

Abstract: In a current comparison type latch, during a reset mode of the current comparison type latch where the clock signal is at the “L” level, transistors which are disposed along the current path extending from the high potential power supply line to the low potential power supply line are turned OFF while transistors which connect the high potential power supply line to two output terminals are turned ON, so as to bring the potential of each of the two output terminals to a logic level (the “H” level or the “L” level), thereby preventing a through current from flowing from the high potential power supply line to the low potential power supply line. Therefore, a high-speed and high-precision current comparison is made while reducing the through current during a reset mode.

Abstract: A sensor with a dynamic latch comprising having a sensor coupled to a gain amplifier, a delay circuit connected to the gain amplifier and a summing circuit coupled through first and second nodes to the gain amplifier. The sensor with a dynamic latch further comprises an output stage coupled to a comparator circuit and the summing circuit and to third and fourth nodes and first and second energy storing devices coupled to the comparator circuit.

Abstract: A charge-redistribution low-swing differential logic circuit combining a differential logic network and a charge-redistribution circuit so as to provide a pair of complementary signals having only a small difference, thereby avoiding a time delay. Further, after a sense amplifier is used to amplify the signals, the resulting signals are outputted to sequential differential logic network, wherein the output swing can be reduced by a threshold voltage Vtn (Vtp) on a transistor. In addition, a pipeline is formed by the series connection structure controlled by a true-single-phase clock or by pseudo-single-phase clock, thereby achieving a designed circuit having high-speed and low power dissipation.

Abstract: A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and an complementary input signal, a full differential amplifier for amplifying the output of the sense amplifier, and a latch for latching the output of the full differential amplifier and outputting the latched output.