Abstract: A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Abstract: An input circuit includes a data input unit for the input of input data, a data latch for latching the input data, a reset unit for resetting the data latch, a clock synchronization unit for synchronizing the input of the input data to the data input unit, and a latch enhancement unit for blocking feedthrough current by functioning complementarily to the reset unit, and enhancing the latching operation of the data latch.

Abstract: A latch-type level converter has a signal-input transistor, a latch, and a clock-input transistor. The signal-input transistor, which is a high-voltage transistor, receives an input signal, and the latch holds data of the input signal received by the signal-input transistor. The clock-input transistor controls the operation in accordance with a clock. According to the latch-type level converter, not only can low-amplitude signals be accurately amplified, but also input signals having a common-mode voltage higher than the supply voltage can be received.

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

Abstract: Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.

Abstract: To prevent a resistive delay in a bitline disconnecting circuit, an NMOS latch composing a part of a CMOS latch is composed of four series NMOS transistors, two of which have respective gate electrodes cross-coupled directly to a pair of bitlines without the interposition of the bitline disconnecting circuit therebetween and the other two of which have respective gate electrodes cross-coupled to a pair of first-stage output nodes in a stage subsequent to the bitline disconnecting circuit.

Abstract: A low power latch sense amplifier for electrically being coupled to a bit line of a memory cell array is disclosed. The low power latch sense amplifier comprises a source follower sense amplifier and an activated latch register. The source follower sense amplifier comprising a current source and a biased metal-oxide semiconductor is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the source follower sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter responses to the sensing signal, and the first inverter outputs a first inverter output signal. The first switch is controlled by a first set of control signal, and the first inverter output signal is corresponding to the sensing signal when the first switch is turned on.

Abstract: A semiconductor memory device of which the data output circuit scale is reduced and the data read speed is improved. An output control signal generation portion receives first and second output data determination signals from a sense amplifier and a level shift enable signal. The first and second output data determination signals have complementary logical levels, a maximum internal voltage, and a minimum ground voltage. The maximum voltage of the level shift enable signal is an external voltage and the minimum voltage is the ground voltage. An output portion connected with the output control signal generation portion through respective nodes outputs an output signal from another node. The maximum voltage of the output signal is the external voltage and a minimum voltage is the ground voltage.

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay.

Abstract: A selection circuit is provided for first and second latch circuits which operate in response to first and second operation timing signals, respectively. By the selection circuit, a first operation of transmitting a signal corresponding to a first output signal of the first latch circuit to a third output terminal, and a second operation of transmitting a second output signal in place of the first output signal to the third output terminal when the first output is different from the second output signal of the second latch circuit are performed. The second operation timing signal is generated behind the first operation timing signal, and the operation period of the second latch circuit is shortened as necessary in the first operation.

Abstract: Complementary data line driver circuits conserve power by evaluating data on complementary data lines and providing conditional charge recycling in the event the new data to be provided to the complementary data lines differs from the old data residing thereon. These devices and circuits include first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair. The driver control circuit compares the old data on the data line pair against new data to be provided to the data line pair. Based on the comparison and determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data in two steps. The first of the two steps includes transferring charge from the more positively biased one of the first and second data lines to the other data line in the data line pair, preferably for a duration sufficient to substantially equilibrate voltages on the first and second data lines.

Abstract: Structures and methods for high speed signaling over single sided/ended current sense amplifiers are provided. Embodiments introduce hysteresis within a pseudo-differential current sense amplifier and provide it with adjustable thresholds for the detection of valid signals coupled with the rejection of small noise current transients or reflections and ringing when using low impedance interconnections and/or current signaling. The circuit provides a fast response time in a low power CMOS environment. Integrated circuits, electrical systems, methods of operation and methods of forming the current sense amplifier are similarly included. The pseudo differential current sense amplifier circuit facilitates the introduction of hysteresis which provides the added ability to differentiate true signals from noise transients, and conserves circuit design space by allowing for single sided/ended sensing.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: A sense amplifier inverts the output from the pass transistor to control a pre-charge transistor. The combination of the inverter and pre-charge transistor pre-charges the output to a level just below the flip level of the following data latch circuit. If the data cell read is a low threshold cell (conductive or “1”), the output level does not significantly change, and the data is rapidly latched and read. If the data cell is a high threshold cell (non-conductive or “0”), the pass transistor shuts off and the output is pulled up above the flip level of the data latch circuit through a pull-up path. The pre-charge level is near the flip level, so the output does not have to be pulled up very far, thus reading a “0” is also fast. In one embodiment, the pull-up transistor is a p-channel MOSFET with the gate grounded, thus providing more constant current than a diode-connected configuration.

Abstract: A sense amplifier circuit has two inputs for connection to complementary bit lines and an output terminal. The circuit comprises control circuitry responsive to control input for selectively tristating the output terminal.

Abstract: Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a CMOS latch.

Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.

Abstract: An input receiver capable of sensing and amplifying an external signal having a very small swing input signal. The input receiver comprises a clock sampled amplifier for receiving a clock signal and a reference signal, respectively, in response to a first state of a clock signal and a delayed sampling clock signal, and for amplifying and sampling the voltage difference between the external signal and the reference signal, respectively, in response to a transition of the clock and delayed sampling clock signals to a second state; and a pulse generator for pre-charging a power source voltage and selectively pulling down the pre-charged signals to produce a pulse signal, in response to the second state of the delayed sampling clock signal and outputs of the clock sampled amplifier.

Abstract: A rectifier circuit with a transistor having first and second electrodes coupled between an input and output of the rectifier circuit. A latch has an output connected to a control node of the transistor, and has first and second inputs connected to the input and output of the rectifier circuit, respectively. The invention provides a self-contained, self-powered, self-regulated low turn-on voltage diode-rectifier with maximum current (on-state conductance) when forward-biased. This circuit can be inserted between any two nodes and behaves like a Schottky diode.

Abstract: A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series.

Abstract: A differential amplifier circuit has a latch unit and a differential input portion. A minute current is kept to flow through the differential input portion. Therefore, the differential amplifier circuit can accurately amplify even a signal high in speed and small in amplitude.

Abstract: An input-output line sense amplifier of a semiconductor memory device that consumes a small amount of current and direct current (DC), includes a current sensing circuit for sensing only a portion of the current through the input-output line and the complementary input-output line, a first amplifier operating from another portion of the sensed current and of the complementary current to amplify and invert a first detected output signal of the current sensing circuit, a second amplifier operating from yet another portion of the sensed current and of the complementary current to amplify and invert a second detected output signal of the current sensing circuit.

Abstract: The present invention provides a current sense amplifier including first and second sense transistors having cross-coupled gates and drains. The current sense amplifier further includes first and second load devices having first terminals connected to respective drains of the first and second sense transistors and a latch having first and second inputs connected to respective drains of the first and second sense transistors. The amplifier still further includes an enable device that is responsive to an enable signal and has a first terminal connected to second terminals of the first and second load devices and a first output of the latch.

Abstract: A computer system employs a sense amplifier having set and reset functions incorporated therein. Those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A CMOS cross-coupled sense amplifier circuit that detects and amplifies data of memory cells is disclosed. The sense amplifier having a favorable sense margin even if a mismatch occurs in transistors constructing the sense amplifier in the fabricating process. The sense amplifier includes voltage control transistors that control the voltage between drain and source of the NMOS transistors in the inverters connected in a latch type between output nodes at an identical phase during a pre-charge step and during an initial operation step. The channels of the voltage control transistors are connected between the drain and source of the NMOS transistors in the inverters for being controlled by a sense amplifier signal.

Abstract: A receiver circuit in a communication system receives a complementary potential signal having a ground level or a floating level from a transmitter circuit through a pair of transmission lines. The receiver circuit includes first and second switching transistors for supplying a complementary current signal based on the complementary potential signal, a current detection transistor for detecting the current flowing through the switching transistors, and a potential control unit for controlling the gate potentials of the switching transistors based on the detected current for implementing a negative feedback loop. The negative feedback loop compensates the influence by a fluctuation of the potential of the transmitter circuit or the receiver circuit.

Abstract: The inverter functioning as a comparator, dummy inverter having the same electric characteristics as the inverter, and control circuit are provided. Vth detecting input voltage output from the control circuit is input into the dummy inverter, Vth detecting output voltage output from the dummy inverter is input into the control circuit, and the threshold voltage of the dummy inverter is detected. The threshold voltage of the inverter is controlled by controlling the back gate voltages of the MOS transistors of the dummy inverter and the inverter in such a manner that the threshold voltage of the dummy inverter coincide with an external reference voltage.

Abstract: An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an “on” state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract: An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.

Abstract: The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

Abstract: A differential comparison circuit capable of easily obtaining desired circuit accuracy and comparing differential signals with reduced influences of fluctuation of a power source voltage. Input/output terminals I/O1 and I/O2 of a latch circuit 1 are connected to the drain terminals of MOS transistors M1 and M2 having the same characteristics. Input terminals IN1 and IN2 are provided to the gate and source terminals of the MOS transistor M2, and input terminals IN3 and IN4 are provided to the gate and source terminals of the MOS transistor M2. A bias circuit 2 brings the MOS transistors M1 and M2 into the same bias state. The difference of the input signals supplied to the input terminals IN1 and IN2 is compared with the difference of the input signals supplied to the input terminals IN3 and IN4. Since the comparison result is outputted from the first and second input/output terminals I/O1 and I/O2, the input offset voltage does not affect the differential comparison circuit.

Abstract: A high-speed sense amplifier includes a pair of cross-coupled inverters coupled to intermediate nodes and then to differential inputs nodes by a control circuit. The intermediate nodes are coupled together by a accelerator transistor that forms a current path when the sense amplifier is placed in a sensing state to provide parallel discharge paths for one or the other of output nodes. During precharge, the accelerator transistor operates to equalize the intermediate nodes to ready them for the next sense phase.

Abstract: Providing an active signal that increases the gate overdrive voltage of the driver of a sense amplifier enables the use of smaller drivers. This facilitates more efficient layouts and/or smaller sense amplifiers, thereby reducing the chip size.

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed

Abstract: A sense amplifier for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.

Abstract: A semiconductor memory device which comprises a memory cell array having a plurality of memory cells, complementary data bus lines connected to said memory cells in said memory cell array and a sense amplifier. The sense amplifier is connected to the memory cells through the complementary data bus lines and amplifies a difference between current values on said complementary data bus lines associated with a logical value stored in the memory cell. The sense amplifier has a positive feedback circuit having a plurality of differential pairs constructed by transistors.

Abstract: To reduce current consumption in a sense amplifier circuit in a semiconductor integrated-circuit device, in particular, in a semiconductor integrated-circuit having a non-volatile memory as a memory element thereof. A Switching element for cutting off a direct current at the end of data reading from a memory is arranged in a path through which the direct current flows. In this way, the switching element cuts off the direct current at the moment of completion of the data reading from the memory, thereby substantially reducing current consumption.

Abstract: Set and reset functions are corporated in a sense amplifier such that those functions can be performed by the sense amplifier rather than by circuits connected to the sense amplifier. The set and reset functionality is added to the sense amplifier in a manner that minimally impacts the sense amplifier's performance. Accordingly, the sense amplifier includes a number of discharge paths for discharging charges that develop on its output terminals. The set and reset circuit includes a number of high conductance paths that are turned-on in response to an assertion of a set control signal or a reset control signal. When either of those control signals is asserted, the corresponding output terminal is discharged. Accordingly, the output terminals can be either set or reset, responsive to which of the control signals is asserted. When the control signals are de-asserted, the sense amplifier performs in a normal sense amplifier manner.

Abstract: A clocked sense amplifier flip flop includes at least one keeper unit to prevent the occurrence of a floating data node.

Abstract: Integrated circuit memory devices according to the present invention include a current sense amplifier having first and second cross-coupled sensing transistors. First and second data lines are electrically coupled to the source of the first sensing transistor and the source of the second sensing transistor, respectively. The current sense amplifier includes a first load transistor that has a source electrically connected to a drain of the first sensing transistor and a gate of the second sensing transistor and a second load transistor is included that has a source electrically connected to a drain of the second sensing transistor and a gate of the first sensing transistor. A switching transistor is responsive to an enable signal and has a source electrically coupled to a drain of the first load transistor and a drain of said second load transistor. A first load circuit provides a variable impedance across the source and the drain of the first load transistor in response to at least a first sense signal.

Abstract: A comparator circuit includes a regenerative stage that uses a relatively small quiescent current combined with a relatively large dynamic current to charge a common-source node in the regenerative stage. The quiescent current helps maintain the common-source node in the regenerative stage near a desired charged level. The comparator circuit can also include an input isolation circuit to eliminate charge kick-back to the input signal lines.

Abstract: A semiconductor memory device includes two power feed lines. An overdriving scheme is applied to one of the power feed lines in the sensing amplifying operation, and no overdriving scheme is applied to the other power feed line in the sensing operation. According to the overdriving scheme, the power feed line is overdriven to a potential level higher than a potential corresponding high level data stored in a memory cell. Thus, the overdriving of the power feed line is applied as an auxiliary function to prevent application of an excess potential to a memory cell capacitor. Such a semiconductor memory device can be achieved that improves both the speed of sensing amplifying operation and the reliability of memory cell capacitors, while conforming to low voltage operation requirement.

Abstract: A data transfer arrangement. The data transfer arrangement includes two active pull up/active pull down bus drivers and a voltage precharge source. A differential bus is coupled to the bus drivers and to the voltage precharge source. A latching sense amplifier is coupled to the differential bus and serves as the bus receiver. The bus drivers operate in a precharge phase and a data transfer phase. The bus receiver operates in an analogous but opposite manner, i.e., when the bus drivers are in the precharge phase, the bus receiver is in the data transfer phase and when the bus drivers are in the data transfer phase, the bus receiver is in a precharge phase.

Abstract: An amplifier in a semiconductor integrated circuit includes a current-mirror typed differential amplifier and a cross-coupled differential amplifier, whereby a minute voltage difference from a bit line signal or a data bus signal is amplified. The amplifier for generating an amplified signal includes a load for coupling to a first voltage potential, a first sense amplifier responsive to a first data signal, and a second sense amplifier responsive to a second data signal. The first and second sense amplifiers are commonly coupled to the load, and the amplified signal of the first or second data signal is generated.

Abstract: An electronic circuit configuration having two lines and a detector device which is allocated to the two lines. The circuit configuration detects a potential difference on the lines and controls a change in the line potentials in response to this. Each line is allocated a switch that is driven by the detector device and, after actuation by the detector device, connects the potential of an associated line to a reference-ground potential that is coupled to the switch.

Abstract: A dual threshold voltage sense amplifier that is capable of separating the rise time threshold from the fall time threshold, creating a dual sensing threshold voltage. In one embodiment of the invention, the dual threshold voltage sense amplifier is capable of providing a lower threshold for the rise time and a higher threshold for the fall time, thereby reducing the fall time and improving the read speed in asynchronous static memory without substantially increasing the core cell dimension or the overall design size.

Abstract: A circuit and method for reducing noise in a memory circuit is disclosed. In one embodiment, the circuit includes an amplifier, a first transistor and a second transistor. The first transistor is capable of pulling up a first input port of the amplifier in response to a complement of the second memory signal. The second transistor is capable of pulling of a second input port of the amplifier in response to a complement of the first memory signal. In one embodiment, the method includes receiving a first memory signal at a first input port of an amplifier, receiving a second memory signal at a second input port of the amplifier, and pulling up the second input port in response to a complement of the first memory signal.