Maximum And Minimum Amplitude Patents (Class 327/62)
  • Patent number: 11863189
    Abstract: An integrated circuit includes an upper threshold circuit, a lower threshold circuit, and a control circuit. The upper threshold circuit is configured to set a logic level of a first enabling signal based on comparing an input voltage signal with an upper threshold voltage. The lower threshold circuit is configured to set a logic level of a second enabling signal based on comparing the input voltage signal with a lower threshold voltage. The control circuit is configured to change an output voltage signal from a first voltage level to a second voltage level when the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Kai Tsai, Chia-Hui Chen, Chia-Jung Chang
  • Patent number: 10921341
    Abstract: A magnetic field sensor for detecting motion of an object includes one or more magnetic field sensing elements configured to generate a magnetic field signal in response to a magnetic field associated with the object. A motion detector responsive to the magnetic field signal and to a threshold signal is configured to generate a detector output signal having edges occurring in response to a comparison of the magnetic field signal and the threshold signal. A speed detector responsive to the detector output signal generates a speed signal indicative of a speed of motion of the object. A delay processor is responsive to the speed signal and configured to determine a delay for the detector output signal based on the speed of motion of the object.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: February 16, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventor: Devon Fernandez
  • Patent number: 10868528
    Abstract: Provided is a signal output device capable of appropriately outputting a signal even when a received signal amount is low. A signal output device is provided with: a high-side comparator; a low-side comparator; a high-side AC coupling unit which is connected to one end of the input terminal of the high-side comparator, and removes a DC component from either a high signal or a low signal; a low-side AC coupling unit which is connected to one end of the input terminal of the low-side comparator, and removes a DC component from either a high signal or a low signal; and a threshold output unit which outputs high-side threshold DC voltage to be combined with the output of the high-side AC coupling unit, and also outputs low-side threshold DC voltage to be combined with the output of the low-side AC coupling unit.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 15, 2020
    Assignee: ULTRAMEMORY INC.
    Inventor: Naoki Ogawa
  • Patent number: 9729132
    Abstract: A squelch detector, including: an input configured to receive an input signal; a peak detector connected to the input configured to detect a maximum value of the input signal wherein the peak detector includes a refresh input configured to receive a refresh signal to refresh the output of the peak detector, a valley detector connected to the input configured to detect a minimum value of the input signal wherein the valley detector includes a refresh input configured to receive the refresh signal to refresh the output of the valley detector, and a comparator including a first signal input connected to an output of the peak detector, a second input connected to an output of the valley detector, and a first reference input, wherein the comparator is configured to compare a difference between an output of the peak detector and an output of the valley detector and a reference value received at the first reference input and configured to produce an output based upon the comparison.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 8, 2017
    Assignee: NXP B.V.
    Inventors: Xu Zhang, Siamak Delshadpour, Ahmad Yazdi
  • Patent number: 9225247
    Abstract: A boost converter includes a comparator having first and second gain stages that operate in compare and auto-zero modes. The comparator measures voltage drop across a P-channel transistor to determine when current through an inductor reaches zero. When the inductor current reaches zero, the P-channel transistor becomes inactive to prevent a reduction in efficiency caused by allowing negative inductor current to draw current from a load. The comparator is then placed in a low power state. When the comparator is not in a compare mode, the comparator can operate in an auto-zero mode to cancel offset when measuring the input of the comparator.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 29, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Michael T. Berens
  • Patent number: 9144126
    Abstract: An electronic circuit for driving a plurality of light emitting diode (LED) channels coupled to a common voltage node includes a priority queue for tracking a dominant LED channel. A queue manager may be provided to keep the priority queue updated during LED drive operations based on operating conditions associated with the LED channels.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 22, 2015
    Assignee: Allegro Microsystems, LLC
    Inventors: Pranav Raval, Gregory Szczeszynski, David Toebes
  • Patent number: 8901938
    Abstract: A measure initialization path for a delay line structure includes: a forward path, comprising a plurality of delay stages coupled in series; a first output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path; and a second output path coupled to at least an output of a delay stage of the forward path, where at least an output of a delay stage is fed forward to the forward path. When a signal is propagated through the measure initialization path, the signal successively propagates through a delay stage of the forward path, a delay stage of the first output path and a delay stage of the second output path for performing measure initialization.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Aaron Willey, Yantao Ma
  • Patent number: 8829987
    Abstract: The invention relates to modulation and demodulation circuits, such as envelope detectors used to demodulate amplitude-modulated (AM) signals. By coupling an analog circuit to a port of a digital component, a compact envelope detector can be obtained, which achieves demodulation of AM signals for direct coupling into a digital input port. Accordingly, a compact envelope detector may be used in the data receiving part of a sealed device requiring post-manufacturing data transfer, in combination with additional components that provide electromagnetic coupling, such as inductive, capacitive, or radiative. An example of such a device is a credit card sized authentication token.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: September 9, 2014
    Assignee: Vasco Data Security, Inc
    Inventor: Dirk Marien
  • Patent number: 8761300
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 24, 2014
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8713500
    Abstract: A computer executes a signal delay evaluation program to determine whether reference levels used to define slew rates of a first circuit block are different from those used for a second circuit block that receives an output signal from the first circuit block. The computer corrects an output slew rate of the output signal supplied from the first circuit block to the second circuit block, based on a difference in the reference levels that is found between the first and second circuit blocks.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Mitsuru Onodera
  • Publication number: 20140062533
    Abstract: Various embodiments of a method and apparatus for performing adaptive voltage adjustment based on temperature value are disclosed. In one embodiment, and integrated circuit (IC) includes logic circuitry having at least one temperature sensor therein. The IC also includes a power management circuit coupled to receive temperature readings from the temperature sensor. The power management circuit is configured to determine a temperature of the IC based on a temperature reading received from the temperature sensor. The power management circuit may compare the determined temperature to a temperature threshold. If the temperature exceeds a temperature threshold value, the power management circuit may cause the operating voltage to be reduced by an amount equivalent to a voltage guard band.
    Type: Application
    Filed: September 5, 2012
    Publication date: March 6, 2014
    Inventor: Toshinari Takayanagi
  • Patent number: 8625683
    Abstract: A serial data transmission system, includes a transmitting terminal for transmitting a data, a receiving terminal for receiving the data transmitted by the transmitting terminal, a first connecting capacitor connected between the transmitting terminal and the receiving terminal, and a second connecting capacitor connected between the transmitting terminal and the receiving terminal, wherein the transmitting terminal comprises a transmitting terminal driver unit and an amplitude detection unit connected with the transmitting terminal driver unit, the transmitting terminal driver unit outputs a pair of differential signals, the amplitude detection unit detects an amplitude variation of the differential signals output by the transmitting terminal driver unit, and outputs an indication signal indicating whether the transmitting terminal and the receiving terminal are properly connected with each other. A serial data transmission method is further provided.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: January 7, 2014
    Assignee: IPGoal Microelectronics (SiChuan) Co., Ltd.
    Inventors: Zhaolei Wu, Lei Li
  • Patent number: 8604837
    Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8604836
    Abstract: A detector circuit, has a first diode, to an anode of which an AC signal is input and to which a constant voltage is supplied, a second diode, to an anode of which the constant voltage is supplied, and a difference current generation circuit, which generates the difference current between a first current flowing in the first diode and a second current flowing in the second diode.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Publication number: 20130002305
    Abstract: A method and an associated apparatus for a signal rectification and timing circuit. A variable amplitude input signal is generated. An upper threshold level is determined and a lower threshold level is determined. The variable amplitude input signal and the upper threshold level are input into a first comparator. The variable amplitude input signal and the lower threshold level are input into a second comparator. A first digital output signal is generated in the first comparator using a hysteresis circuit and a second digital output signal is generated in the second comparator using a hysteresis circuit. The first digital output signal and the second digital output signal are input into a logic array. A digital level pulse output signal is generated in the logic array that has a digital transition where the variable amplitude input signal passed through a threshold level.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Applicant: General Electric Company
    Inventor: Steven Thomas Clemens
  • Patent number: 8325848
    Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: December 4, 2012
    Assignee: Broadcom Corporation
    Inventors: Ahmad Mirzaei, Hooman Darabi
  • Patent number: 8310277
    Abstract: A high linear fast peak detector having a variable bias current and/or a variable bias voltage is described. In an exemplary design, the peak detector includes a transistor, a variable current source, a capacitor, and a feedback circuit. The transistor receives the input signal and provides a source current. The variable current source receives the input signal, provides high bias current when the input signal is low, and provides low bias current when the input signal is high. The capacitor is charged by the source current when the input signal is high and is discharged by the high bias current when the input signal is low. The feedback circuit receives a detected signal from the capacitor and provides higher bias voltage for the transistor when the input signal is high, which results in higher source current from the transistor.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: November 13, 2012
    Assignee: QUALCOMM, Incorporated
    Inventors: Wenjun Su, Aristotele Hadjichristos, Marco Cassia, Chiewcharn Narathong
  • Patent number: 8278970
    Abstract: A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: October 2, 2012
    Assignee: ST-Ericsson SA
    Inventors: Calogero Davide Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
  • Patent number: 8238477
    Abstract: In an embodiment, set forth by way of example and not limitation, a data slicer includes a signal input node, a comparator having a first input of a first polarity, a second input of a second polarity which is the opposite of the first polarity, and an output coupled to a data out node, the first input of the comparator being coupled to the signal input node, and a multi-mode threshold generator including a first threshold generator and second threshold generator, whereby the first threshold generator is selected firstly and the second threshold generator is selected secondly.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: August 7, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Andrew Zocher, Luiz Antonio Razera, Jr.
  • Patent number: 8207782
    Abstract: A circuit to minimize thermally generated offset voltages includes a differential pair of transistors having a first transistor and a second transistor and coupled to a current source, a differential input having a first input coupled to the first transistor and having a second input coupled to the second transistor, a pair of bypass transistors having a first bypass transistor and a second bypass transistor, the first bypass transistor coupled in parallel with the first transistor and the second bypass transistor coupled in parallel with the second transistor, wherein the pair of bypass transistors is coupled to the current source, and control circuitry coupled to the pair of bypass transistors for controlling current through the pair of bypass transistors.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: June 26, 2012
    Assignee: HRL Laboratories, LLC
    Inventor: Albert E. Cosand
  • Patent number: 8138802
    Abstract: A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 20, 2012
    Assignee: Standard Microsystems Corporation
    Inventor: Scott C. McLeod
  • Patent number: 8129862
    Abstract: A scalable highest available voltage selector circuit determines the highest of n input voltages and connects the highest voltage to an output. The circuit has at least n circuit branches, each of which comprises n?1 “comparator” FETs connected between an input voltage and an output node, and a diode-connected FET connected between the output node and a current source. The junction of the diode-connected transistor and current source provides a control signal used by the other branches. Each of a branch's comparator FETs have their gates connected to a respective one of the other branches' control signals, such that they are driven on regeneratively when the applied input voltage is the highest of the n input voltages. Each branch also includes n?1 “shorting” FETs connected across the diode-connected transistor, arranged to be driven off when the applied input voltage is the highest, but which are otherwise driven on.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Mark Audy
  • Patent number: 8120209
    Abstract: A voltage sensing device with which high-precision voltage sensing is possible without the need to obtain a unique correction constant for each device. A pair of voltage input nodes NCk and NCk-1 is selected from voltage input nodes NC0-NCn in switch part 10, and they are connected to sensing input nodes NA and NB in two types of patterns with different polarity (forward connection, reverse connection). Sensing input nodes NA and NB are held at reference potential Vm by voltage sensing part 20, and current Ina and Inb corresponding to the voltage at voltage input nodes NCk and NCk-1 flows to input resistors RIk and RIk-1. Currents Ina and Inb are synthesized at different ratios in voltage sensing part 20, and sensed voltage signal S20 is generated according to the synthesized current Ic. Sensed voltage data S40 with low error is generated according to the difference between the two sensed voltage signals S20 generated in the two connection patterns.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Toru Tanaka, Akio Ogura, Kazuya Omagari, Nariaki Ogasawara
  • Patent number: 8115538
    Abstract: The invention relates to the field of modulation and demodulation circuits, such as envelope detectors used to demodulate amplitude-modulated (AM) signals. By coupling an analog circuit to a port of a digital component, an envelope detector can be obtained, which achieves demodulation of AM signals for direct coupling into a digital input port. Accordingly, an envelope detector may be used in the data receiving part of a sealed device requiring post-manufacturing data transfer, in combination with additional components that provide electromagnetic coupling, such as inductive coupling, capacitive coupling, or radiative coupling. An example of such a device is a credit card sized authentication token.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: February 14, 2012
    Assignee: Vasco Data Security, Inc.
    Inventor: Dirk Marien
  • Patent number: 8044686
    Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: October 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Yamamoto, Tsuneo Suzuki, Yuusuke Maeda, Souichi Honma
  • Patent number: 8026743
    Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: September 27, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chiung-Ting Ou
  • Patent number: 8022734
    Abstract: A power detection system is disclosed that includes a detector circuit and a comparator circuit. The detector circuit includes a first transistor, a second transistor that is not identical to the first transistor, and a third transistor that is substantially identical to the first transistor. Each of the transistors is commonly coupled to a current source and is coupled to a differential input voltage. The comparator circuit is for providing an output that is representative of whether the input voltage is above or below a threshold voltage responsive to a difference between the first transistor and the second transistor.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: September 20, 2011
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Broughton
  • Patent number: 7990182
    Abstract: A low-current differential signal activity detector circuit may be configured to reject large common mode signals on differential input lines, while still detecting smaller differential signals applied to the same set of differential input lines. The detector circuit may comprise a translinear buffer that is driven at the buffer input and at the buffer output by the differential input signals. The differential signal thereby driving the inputs of the detector circuit may be half-wave rectified through the buffer output devices and may be filtered to provide the detected output. When applying a common mode signal, the buffer's input and output may track each other, and no current may be rectified in the output devices, thus providing common-mode signal rejection. The detector circuit may also be configured with two buffers having their outputs coupled to a common node, each buffer input driven by a respective one of the differential input signals.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: August 2, 2011
    Assignee: Standard Microsystems Corporation
    Inventor: Scott C. McLeod
  • Patent number: 7880509
    Abstract: A wired signal receiving apparatus including a signal receiver, a signal peak detector, and a signal comparator is disclosed. The signal receiver includes an operation current detecting circuit for detecting an operation current. The signal receiver further receives a transmission signal. The signal peak detector receives the operation current, detects a peak thereof, and generates a peak current. The signal comparator compares a reference signal and the peak current to generate an output current for regulating the operation current.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: February 1, 2011
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Hung Chen, Tsun-Tu Wang, Wing-Kai Tang
  • Patent number: 7880508
    Abstract: A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: February 1, 2011
    Assignee: ST-Ericsson SA
    Inventors: Calogero Davide Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
  • Publication number: 20110012605
    Abstract: With batteries or cells, particularly lithium ion cells, it is important to determine when one or more cells have entered a fault condition (i.e., overvoltage or undervoltage). Conventional circuits employ measuring circuits that use multiple bandgap circuits and high voltage components. These conventional circuits, however, consume a great deal of area because of the use of these multiple bandgap circuits and the high voltage components. Here, a circuit is provided that reduces the number of bandgap circuits and reduces the number of high voltage components, reducing the area consumed and reducing the overall cost of production compared to conventional circuits.
    Type: Application
    Filed: December 21, 2009
    Publication date: January 20, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Umar J. Lyles, Karthik Kadirvel, John H. Carpenter, JR.
  • Patent number: 7863939
    Abstract: A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: January 4, 2011
    Assignee: Fujitsu Limited
    Inventors: Tetsuji Yamabana, Satoshi Ide
  • Patent number: 7863940
    Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: January 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chiung-Ting Ou
  • Patent number: 7852122
    Abstract: A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for operating on the basis of the differential signal by receiving the differential signal by the potential difference between the two transmission lines; and a connecting resistor for electrically connecting the two transmission lines. Further, a connecting MOS transistor may be provided near a receiving end of the driven unit.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: December 14, 2010
    Assignee: Advantest Corporation
    Inventors: Kazuhiro Yamamoto, Toshiyuki Okayasu
  • Patent number: 7839182
    Abstract: A circuit for detecting noise peaks on the power supply of an electronic circuit, including at least a first transistor having its control terminal connected to a terminal of application of a first potential of a supply voltage of the circuit and having a first conduction terminal connected to a terminal of application of a second potential via at least one first resistive element, the second conduction terminal of the first transistor providing the result of the detection.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: November 23, 2010
    Assignee: STMicroelectronics S.A.
    Inventors: Alexandre Malherbe, Benjamin Duval
  • Patent number: 7839208
    Abstract: An integrated circuit and a method for operating an integrated circuit is disclosed. One embodiment provides a semi-conductor component, an electronic system, and a method for operating an integrated circuit. A method for operating an integrated circuit provides applying a voltage to a line or a connection in accordance with data to be input. A current is applied to the line or the connection in accordance with data to be output.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: November 23, 2010
    Assignee: Infineon Technologies AG
    Inventors: Michael Hausmann, Axel Reithofer
  • Patent number: 7795929
    Abstract: Provided is a voltage detection circuit that outputs a detection result when a voltage to be measured exceeds a predetermined voltage or falls below the predetermined voltage at a speed higher than that of a conventional case. The voltage detection circuit according to the present invention includes an input buffer that outputs a detection voltage to be input as an input voltage, and a voltage detection section that accelerates a rising of the input voltage in a transient state where the input voltage exceeds a predetermined threshold value, and accelerates a dropping of the input voltage in a transient state where the input voltage falls below the predetermined threshold value. The voltage detection circuit accelerates a change in the input voltage to output the detection result from an output buffer at high speed.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 14, 2010
    Assignee: Seiko Instruments Inc.
    Inventor: Masakazu Sugiura
  • Patent number: 7772894
    Abstract: Aspects of the present invention include a method, apparatus and device for generating a power on reset (POR) signal in relation to the crossing point of two currents wherein at least one current is a quadratic function and the other is an exponential function, where each has a mathematical correlation to a function of a predetermined power supply voltage.
    Type: Grant
    Filed: November 13, 2006
    Date of Patent: August 10, 2010
    Assignee: Atmel Corporation
    Inventors: Frederic Demolli, Thierry Soude, Daniel Payrard, Michel Cuenca
  • Patent number: 7746150
    Abstract: A fail-safe differential receiver having a differential amplifier adapted to receive first and second differential input signals and generate a differential voltage. A peak detector is coupled to the differential amplifier for generating a detect signal and a comparator is coupled to the peak detector for comparing the detect signal to a threshold voltage and providing a comparison signal. A directing circuit is coupled to the differential amplifier for receiving the first and second differential input signals and is coupled to the comparator for receiving the comparison signal. An output amplifier is coupled to the directing circuit. The directing circuit selectively directs the first and second differential input signals to the output amplifier as a function of the value of the comparison signal from the comparator.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: June 29, 2010
    Assignee: Micrel, Incorporated
    Inventors: Thomas S. Wong, Uwe Biswurm, Bernd Neumann
  • Patent number: 7683676
    Abstract: An amplifying unit performs a differential amplification with a highest level or a lowest level of an input signal and a previous input signal. A semiconductor element transfers a signal level output from the amplifying unit from a second terminal to a third terminal by using a current conducted from the second terminal to the third terminal in response to a voltage applied to a first terminal. A control unit controls the voltage applied to the first terminal of the semiconductor element based on a voltage or a current related to a reference semiconductor element. A holding unit holds a signal level output from the third terminal of the semiconductor element.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 23, 2010
    Assignee: Fujitsu Limited
    Inventor: Satoshi Ide
  • Publication number: 20100039141
    Abstract: An envelope detecting circuit is provided. The envelope detecting circuit comprises a source degeneration circuit that amplifies an input differential signal, a differential gain stage that supplies a voltage proportional to the amplified signal, a potential hold circuit that holds the voltage supplied from the gain stage, a comparator circuit that compares the voltage held by the potential holding circuit with a reference potential to output a detect signal, and envelope level adjustment and selection unit that responds to the detect signal and outputs a control signal to the source degeneration circuit.
    Type: Application
    Filed: August 15, 2008
    Publication date: February 18, 2010
    Inventor: Chiung-Ting Ou
  • Patent number: 7663423
    Abstract: A signal level shifting circuit, including an input stage circuit and an output signal latching circuit. The input stage circuit receives an input signal, wherein a voltage level of the input signal falls within a first predetermined voltage range. The output signal latching circuit is cascoded with the input stage circuit, and includes: a latching circuit for generating an output signal according to the input signal, wherein a voltage level of the output signal falls within a second predetermined voltage range, and the second predetermined voltage range is different from the first predetermined voltage range; and an activating circuit, coupled to the latching circuit, for selectively enabling or disabling the latching circuit, wherein when a level transition appears to the input signal, the activating circuit disables the latching circuit.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: February 16, 2010
    Assignee: Ili Technology Corp.
    Inventor: Chih-Kang Cheng
  • Publication number: 20090212826
    Abstract: Disclosed herein is a hysteresis comparator for performing a binarization determination with respect to an input signal having a consecutively varying voltage level based on two threshold voltages having different voltage levels and generating an output signal based on a result of the determination.
    Type: Application
    Filed: January 23, 2009
    Publication date: August 27, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Sunao MIZUNAGA
  • Patent number: 7570715
    Abstract: A delayed peak detector detects a peak level of an input signal IN at timing lagged behind a peak detector, and a peak difference detector detects a peak difference PLD between a delayed peak level DPL and a peak level PL. A reset portion outputs a reset signal BRS for a bottom detector when a level difference between the peak level PL and a bottom level BL exceeds a predetermined value comparable with the amplitude of the input signal IN and the peak difference PLD exceeds an allowable peak difference PLM. It is thus possible to replace the bottom level BL outputted from the bottom detector with a bottom level based on a latest input signal IN.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: August 4, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventors: Sunao Mizunaga, Tadamasa Murakami
  • Patent number: 7557633
    Abstract: A high speed analog transmission envelope (data-validity) detector for detecting the validity or invalidity of received data by generating (and comparing) first through fourth level-shifted signals based on a pair of differential input signals that are externally applied (received). Each of the first through fourth level-shifted signals has voltage levels different from (e.g., higher than) the differential input signals. After comparing the first through fourth level-shifted signals with each other, the comparison results are used in determining the validity of the differential input signals (data). The analog transmission envelope (data) detector flexibly adapts to variations in common mode voltage, and simplifies the circuit architecture because it does not require an additional reference voltage for determining the validity of received data.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: July 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Suk Yu
  • Publication number: 20090121790
    Abstract: An electronic signal level detection system and method are provided. The method receives an analog input signal having a variable voltage and compares the input signal voltage to a threshold. A detection signal is generated for input signal voltages exceeding the threshold in a periodic first time frame. In a second periodic time frame (following the first time frame), a count is updated in response to the generated detection signals. The count is used to create a metric representative of the difference between the input signal voltage and the threshold. The count is incremented in response to the generating a detection signal (“1”) in the first time frame, and decremented in response to not generating a detection signal (“0”) in the first time frame.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 14, 2009
    Inventors: Matthew Douglas Brown, Sheldon James Hood, Guy Jacque Fortier, Stan Harry Blakey
  • Patent number: 7528634
    Abstract: A voltage comparator contains low voltage devices (e.g., bipolar or MOS transistors) and high voltage devices (e.g., DMOS transistors). The low voltage devices, which cannot sustain a voltage greater than a relatively small range of variation that is substantially less than the range of potential variation of the input voltage, are connected in a differential amplifier configuration to perform precision differential measurements on the input voltage. The high voltage devices are interconnected with the low voltage devices in a manner that enables operating levels of the low voltage devices to move up/down, or ‘slide’, with variations in the input voltage, so that the low voltage devices are effectively immune to high levels of the input voltage.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: May 5, 2009
    Assignee: Intersil Americas Inc.
    Inventor: Sumer Can
  • Patent number: 7525347
    Abstract: Differential peak detection for outputting a signal indicative of a peak value of an input signal. The input signal is differentially amplified using common mode feedback and a common mode output is thereby output, wherein common mode level of the common mode output is substantially the same as a common mode voltage. The common mode output of such differential amplification is coupled to an input of a first common source input pair, and the common mode voltage and a feedback from the output signal across a sampling capacitor is coupled to an input of a second common source input pair. A summation of respective outputs of the first and second common source input pairs is coupled to an input of a transconductance stage, wherein an output of the transconductance stage controls charging of the sampling capacitor. In this manner, a more accurate output signal is provided.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: April 28, 2009
    Assignee: Marvell International Ltd.
    Inventor: Qiang Luo
  • Patent number: 7512823
    Abstract: Disclosed is a semiconductor device capable of detecting levels of an external supply voltage, which includes a plurality of signal receivers for simultaneously receiving external input signals, wherein a driving voltage is applied to only one of the signal receivers according to the levels of the external supply voltage.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: March 31, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Han Kwon
  • Publication number: 20090072866
    Abstract: A method for controlling amplified signals in a medical diagnostic device having an amplifier system that is adapted to amplify input signals having a baseline and filter means for filtering the amplified signals, comprising the detection of the presence of an amplified signal having an amplitude that is above an upper voltage threshold or below a lower voltage threshold, and freezing the baseline of the amplified signal upon the detection thereof.
    Type: Application
    Filed: September 19, 2007
    Publication date: March 19, 2009
    Inventor: Neil Edward Walker