Abstract: A pixel circuit may comprise: a first transistor having a first terminal connected to a data line and to which a data signal is applied and a gate terminal connected to a scan line and to which a scan signal is applied; a third transistor having a gate terminal connected to a second terminal of the first transistor and a second terminal connected to a light emitting device; a capacitor having a second terminal commonly connected to the second terminal of the first transistor and the gate terminal of the third transistor; and a second transistor having a second terminal commonly connected to a first terminal of the capacitor and a first terminal of the third transistor, a first terminal connected to a first power supply voltage, and a gate terminal connected to an emission line to which an emission signal is applied.

Abstract: A comparator including: first and second input transistors connected to control signals at first and second nodes of the comparator; latch circuitry; at least one controllable offset-correction component having an input terminal and connected to control the signal at one of the first and second nodes based on an offset-correction signal provided at its input terminal; for each controllable offset-correction component, an offset correction circuit configured to provide the offset-correction signal provided at its input terminal; and control circuitry.

Abstract: A comparator circuit has a pre-charging and early reset output stage. The comparator circuit includes: a first pre-charging transistor and a second pre-charging transistor. A gate of the first pre-charging transistor is connected to a pre-charging signal, and a gate of the second pre-charging transistor is connected to a main clock signal, wherein the pre-charging signal is enabled earlier than the main clock signal. At a pre-charging phase, there is a small electric current, and a comparator slowly amplifies an input small signal to reduce noise; and the electric current is increased after a certain time delay, such that on the basis of pre-charging, the comparator rapidly completes a pre-amplification phase and then enters a regeneration phase.

Abstract: A memory device and a slew rate detector are provided. The slew rate detector includes a clock signal generator, a pulse signal generator, a plurality of sampling comparators, and a detection result generator. The clock signal generator multiplies a frequency of a base clock signal to generate clock signals. The pulse signal generator generates first pulse signals and second pulse signals according to the clock signals. Each of the sampling comparators samples each of transmission signals to generate a reference signal according to the first pulse signals, and samples each of the transmission signals to generate a comparison signal according to the second pulse signals. The sampling comparators compare the reference signals with the comparison signals to generate comparison results. The detection result generator performs an operation on the comparison results to generate detection results.

Abstract: Provided is a comparison circuit to which a negative voltage to be compared can be input directly. The comparison circuit includes a first input terminal, a second input terminal, a first output terminal, and a differential pair. The comparison circuit compares a negative voltage and a negative reference voltage and outputs a first output voltage from the first output terminal in response to the comparison result. The negative voltage is input to the first input terminal. A positive reference voltage is input to the second input terminal. The positive reference voltage is determined so that comparison is performed. The differential pair includes a first n-channel transistor and a second n-channel transistor each having a gate and a backgate. The first input terminal is electrically connected to the backgate of the first n-channel transistor. The second input terminal is electrically connected to the gate of the second n-channel transistor.

Abstract: A semiconductor device includes: a pair of input terminals or receiving a first input signal and a second input signal each of which changes between potentials in a predetermined range via a pair of transmission paths which include a first transmission path and a second transmission path; a first reception circuit which compares in potential the first input signal with the second input signal, and generates a first output signal based on a comparison result therebetween; a second reception circuit which generates a second output signal based on a comparison result of comparing in potential at least one of the first input signal and the second input signal with a reference potential.

Abstract: One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

Abstract: A solid-state imaging device that is capable of improving an imaging characteristic by enhancing a dynamic range of an ADC is provided. A solid-state imaging device that includes a pixel array including a plurality of pixels outputting a pixel signal by photoelectric conversion, and an AD conversion processing unit that performs AD conversion with respect to the pixel signal, and in which the AD conversion processing unit includes a comparator having a first amplifying unit that includes a pair of first differential pairs constituted of P-type transistors and a pair of second differential pairs constituted of N-type transistors, and a second amplifying unit that amplifies an output of the first amplifying unit, and in which a P-type transistor and an N-type transistor are connected in series is provided.

Abstract: A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit.

Abstract: A temperature-sensing device configured to monitor a temperature includes: a first conductive line; a second conductive line, wherein the first and second conductive lines have respective different cross-sectional dimensions; a sensing circuit, coupled to the first and second conductive lines, and configured to determine a logic state of an output signal based on a difference between respective signal levels present on the first and second conductive lines; and a control circuit, coupled to the sensing circuit, and configured to determine whether the monitored temperature is above or below a pre-defined threshold temperature based on the determined logic state.

Abstract: A differential amplifier includes: first and second input nodes; first and second output nodes; first and second supply nodes; first and second offset compensation nodes; first and second amplifier staged configured to generate first and second output voltages at the first and second output nodes as a function of first and second input voltages of the first and second input nodes and first and second offset compensation voltages of the first and second offset compensation nodes; and a feedback circuit configured to generate the first and second offset compensation voltages as a function of the first and the second output voltages. The feedback circuit includes: a coupling circuit coupled between the first and second offset compensation nodes, wherein the coupling circuit comprises one or more passive electric components.

Abstract: A method of operation in an analog-to-digital converter (ADC) includes performing a calibration operation. The calibration operation includes sampling an input analog reference voltage. A sequence of charge sharing transfers is then performed with a charge sharing regulator to transfer an actual amount of charge between a charge source and a charge load based on the input analog reference voltage. The transferred actual amount of charge is compared to a reference charge value corresponding to the reference voltage. A control input to the charge sharing regulator is adjusted to correspondingly adjust charge sharing of a subsequent amount of charge based on the comparing.

Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Abstract: Provided is a zero-crossing detection circuit capable of detecting zero-crossing with high accuracy without being influenced by noise. The zero-crossing detection circuit includes a first comparison circuit, a second comparison circuit having a hysteresis function, and a logic circuit. The first comparison circuit is configured to output a zero-crossing detection result of a first input signal and a second input signal. The second comparison circuit is configured to output a comparison result of the first input signal and the second input signal. The logic circuit includes a unit configured to determine whether to reflect the zero-crossing detection result to output of the logic circuit based on the zero-crossing detection result and the comparison result.

Abstract: Circuits and methods for reducing and cancelling out kickback noise are disclosed. In one example, a circuit for a comparator is disclosed. The circuit includes: a first transistor group, a second transistor group, and a first switch. The first transistor group comprises a first transistor having a drain coupled to a first node, and a second transistor having a source coupled to the first node. Gates of the first transistor and the second transistor are coupled together to a first input of the comparator. The second transistor group comprises a third transistor having a drain coupled to a second node, and a fourth transistor having a source coupled to the second node. Gates of the third transistor and the fourth transistor are coupled together to a second input of the comparator. The first switch is connected to and between the first node and the second node.

Abstract: A comparator includes a first constant current source, a first transistor having a drain connected to the first constant current source, a gate connected to a non-inverted input terminal, and a source connected to an inverted input terminal, a second constant current source connected between the inverted input terminal and a second power supply terminal, a second transistor having a source connected to a first power supply terminal, a gate connected to the drain of the first transistor, and a drain connected to an output terminal, and a third constant current source connected between the drain of the second transistor and the second power supply terminal. An oscillation circuit includes comparators in which at least one of the comparators is a comparator described above.

Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.

Abstract: A circuit and a method are described for generating differential voltages.

Abstract: A method for offset calibration of a voltage comparator is disclosed according to certain aspects of the present disclosure. The method includes applying a first bias voltage to a gate of a first compensation transistor, wherein the first compensation transistor is coupled in series with a first input transistor of the voltage comparator. The method also includes applying a second bias voltage to a gate of a second compensation transistor, wherein the second compensation transistor is coupled in series with a second input transistor of the voltage comparator. The method further includes sensing a logic value at an output of the voltage comparator, and adjusting the first bias voltage and the second bias voltage based on the sensed logic value.

Abstract: A loss of signal (LOS) detector may include a comparator including a first input, a second input and an output indicating a LOS status. The LOS detector further includes circuitry to compare a first signal on the first input generated by differential input signals and a threshold signal common mode with a second signal on the second input generated by differential threshold signals at a first level and an input signal common mode. The circuit further configured to generate a LOS indicator on the output based on the compare.

Abstract: Data and power are transmitted a master to a peripheral, with power communicated from a controller circuit board to the peripheral circuit board across data lines. Power is transmitted from the voltage regulator of the controller circuit board to an SPI or SSI master. Power over Synchronous Serial Interface (SSI) and Serial Peripheral Interface (SPI) uses Ethernet cable or custom 2 to 4-pair cable to move power high speed data between a microprocessor and a peripheral.

Abstract: A transmission circuit includes a current output circuit that outputs a current to a first node, a first switch element provided between the first node and a first signal line, and a second switch element provided between the first node and a second signal line. When a transmission signal is at a first logic level, the first switch element is ON and the second switch element is OFF. When the transmission signal is at a second logic level, the first switch element is OFF and the second switch element is ON. The current output circuit outputs a second current in an n-bit period after the logic level of the transmission signal is inverted, and outputs a first current after the n-bit period.

Abstract: A semiconductor device includes a first signal outputting portion; a second signal outputting portion; and a voltage outputting portion. The first signal outputting portion compares a first voltage output from a first power source and a second voltage output from a second power source, and to output a comparison result. The second signal outputting portion determines whether the second voltage is greater than a threshold voltage, and to output a determination result. The voltage outputting portion outputs the second voltage from an output terminal when the second voltage is greater than the threshold voltage. Further, the voltage outputting portion outputs one of the first voltage and the second voltage from the output terminal when the second voltage is smaller than the threshold voltage.

Abstract: A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

Abstract: A single-ended Class-A amplifier includes an amplification component (e.g., a vacuum tube) having at least an output terminal, a reference terminal and a control terminal. The control terminal receives a time-varying input signal. The amplification component responds to the time-varying input signal to vary an output voltage on the output terminal and to vary a current flowing between the output terminal and the reference terminal. A load is AC-coupled to the output terminal. A steered current source has a voltage input coupled to the output terminal and has a steered current output coupled to the output terminal. The steered current source is configured to increase the steered current to provide current to the load when the output voltage on the output terminal of the amplification component increases and to decrease the steered current when the output voltage on the output terminal of the amplification component decreases.

Abstract: A loss of signal (LOS) detector may include a comparator including a first input, a second input and an output indicating a LOS status. The LOS detector further includes circuitry to compare a first signal on the first input generated by differential input signals and a threshold signal common mode with a second signal on the second input generated by differential threshold signals at a first level and an input signal common mode. The circuit further configured to generate a LOS indicator on the output based on the compare.

Abstract: According to embodiments, a semiconductor device includes a first switching element in which a first reference voltage is input to a gate; a second switching element in which a first voltage is input to a gate; a third switching element to which the first switching element is in Darlington connection; a fourth switching element to which the second switching element is in Darlington connection; a first current mirror circuit to regulate currents flowing in the third and fourth switching elements; a fifth switching element switched between ON and OFF states based on a difference between the first reference and the first voltages; a constant current circuit; a second current mirror circuit; and a voltage setting resistance element between a source of the first switching element and a gate of the third switching element or between a source of the second switching element and a gate of the fourth switching element.

Abstract: A track and hold circuit includes a primary sampling capacitor, a primary switching transistor, and a cancellation transistor. The primary switching transistor is configured to provide a track state that connects an input signal to the primary sampling capacitor and a hold state that isolates the input signal from the primary sampling capacitor. The cancellation transistor is coupled to the primary sampling capacitor. The cancellation transistor is configured to inject a charge onto the primary sampling capacitor that cancels a charge injected onto the primary sampling capacitor by the primary switching transistor while the primary switching transistor is in the hold state.

Abstract: An on-chip AC coupled receiver with offset calibration. The receiver includes AC coupling circuitry to couple a differential input signal into a coupled differential signal having a first signal and a second signal. The receiver includes a first comparator to generate a first error signal indicative of whether a first reference signal is greater or smaller than a signal derived from the coupled differential signal. The receiver includes a second comparator to generate a second error signal indicative of whether a second reference signal is greater or smaller than the signal derived from the coupled differential signal. The receiver further includes feedback circuitry to adjust a voltage offset between the first signal and the second signal of the coupled differential signal based on the first error signal and the second error signal.

Abstract: A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.

Abstract: A current measurement circuit may include unbuffered inputs, and the current may be sampled directly from the input pins. The input current created from each sample may be cancelled by injecting opposite charge on the subsequent sample. This direct sampling from the pins increases the common mode input range of the sense path without having to build high linearity rail-to-rail input buffers, hence lowering cost and power consumption of the current measurement path. It also allows for high-impedance input sampling. The measurement circuit may include multiple sampling stages, with a first sampling stage implemented as a switched-capacitor based circuit. A compensator circuit coupled in a feedback loop from the output of the first sampling stage to the input pins may be operated to provide the equivalent charge back to the input pins every cycle to cancel the input current required to charge the sampling capacitors of the first sampling stage.

Abstract: A field effect transistor current mode differential logic circuit comprising load transistors for converting the current output of each differential leg current to voltage output, and means for configuring the bulk of each differential leg's load transistor to be connected to the drain of the load transistor for use the logic circuit in Subthreshold Source Coupled Logic (STSCL) mode, and means for configuring the bulk of each leg load transistor to be connected to a voltage or to source of the same transistor for use in MOS current more logic (MCML) operation.

Abstract: The present disclosure relates to implementations of a method and a system for calibrating the system that includes analog-to-digital converters (ADCs). The method, performed on the system's corresponding components include, providing, from a signal generator, a first signal during a calibration mode. Parallel ADCs provide ADC outputs associated with the first signal. First parallel filters provide derivative signals associated with the ADC outputs. Second and third parallel filters provide first and second band-stop filtered signals associated with the ADC outputs and the derivative signals, respectively. The disclosure includes multiplying the first and the second band-stop filtered signals and selecting a portion of the multiplied signals that are accumulated for storage. The system incorporating these components performing these features is, accordingly, calibrated.

Abstract: A rail-to-rail comparator circuit includes NMOS and PMOS differential input stages with associated loads that are coupled to a shared-load stage. The shared-load stage is coupled to an output stage that includes two active devices. By sharing the load stage between the two input stages, the comparator has a relatively small circuit area, low power draw, and low propagation delay with rail-to-rail input common-mode voltage range.

Abstract: A comparator may include: a first comparison unit suitable for generating a comparison voltage by performing a comparison operation between a pixel signal and a ramp signal; a time point detection unit suitable for detecting specific timing points of the comparison operation in response to the comparison voltage and a reference voltage, and generating a detection signal corresponding to the specific timing points; a period determination unit suitable for determining an additional supply period in response to the detection signal and a period determination control signal; and an additional current supply unit suitable for supplying an additional current to the first comparison unit during the additional supply period.

Abstract: Embodiments of a differential driver circuit and a method for controlling a differential driver circuit are described. Embodiments of a differential driver circuit may include a current steering circuit configured to determine a current direction through differential output terminals of the differential driver circuit, two resistors connected between the differential output terminals of the differential driver circuit and first and second semiconductor circuits connected to a point between the two resistors. The first and second semiconductor circuits are of different types. The source terminals of the first and second semiconductor circuits are connected to the point between the two resistors.

Abstract: Systems, apparatuses, and methods are provided for analog-to-digital converters (ADCs), such as successive-approximation-register (SAR) ADCs and pipelined ADCs that utilize distributed virtual-ground switching (DVS). DVS circuits and systems receive reference signal inputs that are provided to input signal buffers at the input side of the buffers via reference switches. The input signal buffers and corresponding switches are distributed into scaled replicas that each receive an analog input signal via input signal switches during a first operational phase and are connected to top plates of corresponding distributed capacitors. The bottom plates of the capacitors are sampled to provide analog input signal representations.

Abstract: A fault detecting circuit in a string of LEDs D1-Dc containing comparing operational amplifiers IC1/IC2 connected to a current source is divided into sections, D1-Da, D2-Db, and D3-Dc, wherein the common between the Da cathode and the D2 anode is connected to the noninverting-input of IC1, while the common between the Db cathode and the D3 anode is connected to the noninverting-input of IC2, and to the string D1-Db is connected in parallel to a divider comprising R1/R2, while the string comprising D2-Dc is connected in parallel to a divider comprising R3/R4, and the common of R1/R2 is connected to the inverting-input of IC1 and the common of R3/R4 is connected to the inverting-input of IC2, while the outputs of IC1/IC2 are connected to the bases of corresponding transistors T1/T2, whose emitters are connected to ground and collectors are connected to the voltage source and also to the output terminal.

Abstract: An integrated circuit is disclosed. The integrated circuit includes an equalizer circuit that may provide high-frequency signal amplification. The equalizer circuit also has adjustable impedance circuitry, which may receive digital control signals to adjust the effective impedance of the equalizer circuit. Furthermore, a method of operating the equalizer circuit is also disclosed.

Abstract: A rail-to-rail input hysteresis comparator includes: an input hysteresis comparator module, a transmission module, an output comparator, a switching signal module and a bias module. Compared to the conventional device, the rail-to-rail input hysteresis comparator of the present invention can turn off an output of the N-type input hysteresis comparator of the input hysteresis comparator module when the common mode input voltage is relatively low and turn off an output of the P-type input hysteresis comparator of the input hysteresis comparator module when the common mode input voltage is relatively high, thereby avoiding operating in a linear mode and hence achieving a stable CMRR.

Abstract: A pre-emphasis circuitry that includes (1) a pre-emphasis voltage variation compensation (PVVC) engine having a transition detection circuit and (2) a compensation driver coupled to the PVVC engine is described. In one embodiment, the compensation driver reduces data dependent voltage variations in pre-emphasis provided by the pre-emphasis circuitry. In one embodiment, in response to a predetermined data pattern detected by the PVVC engine, the compensation driver provides an additional boost to performance critical capacitive nodes of the pre-emphasis circuitry. The additional boost causes the performance critical capacitive nodes to charge or discharge more rapidly. In one embodiment, the PVVC engine further includes a digital finite impulse response (FIR) filter coupled to the transition detection circuit.

Abstract: Embodiments of comparator circuits are disclosed. A comparator circuit may include a differential input circuit, an output circuit, a positive feedback circuit operably coupled between the differential input circuit and the output circuit, and a hysteresis control circuit operably coupled with the positive feedback circuit. The hysteresis control circuit includes a switching device and a transistor. The comparator circuit provides sub-hysteresis discrimination and high speed discrimination.

Abstract: A latching comparator includes a switching logic circuit coupled to receive a latching signal, a first signal and a second signal. An output circuit having an input terminal is coupled to the switching logic circuit. The input terminal of the output circuit is coupled to receive both the first and second signals through the switching logic circuit in response to the latching signal being in a first state. The input terminal of the output circuit is coupled to receive only one of the first and second signals through the switching logic circuit in response to a signal representative of an output terminal of the output circuit and in response to the latching signal being in a second state.

Abstract: This disclosure provides systems, methods and apparatus for improving the reliability of dual actuator light modulators by equalizing voltages provided to the two actuators of the light modulator. A pixel circuit for driving the dual actuator light modulator can include a data loading circuit coupled to an actuation circuit. The data loading circuit is utilized to store data received from a controller for a pixel associated with the light modulator. The actuation circuit is utilized to control a first actuator and a second actuator of the dual actuator light modulator based on the data stored by the data loading circuit. The actuation circuit includes a first stabilization capacitor and a second stabilization capacitor for stabilizing voltages provided to the first and second actuators. The actuation circuit also includes an equalization switch for equalizing voltages provided to the first and second actuators.

Abstract: The invention discloses a current detecting circuit, a temperature compensating device and a display device, and relates to the field of display technology, which resolves the problem of image flicker in the display screen or abnormal display due to changes in the turn-on voltage of the thin film transistors in the display panel caused by changes in the temperature in the prior art. The current detecting circuit includes a voltage source, a first mirror current source for supplying a reference current, a second mirror current source for obtaining a difference between a current output from the first mirror current source and a current output from a unit to be detected and converting the difference into a voltage signal, and an inverter for amplifying the voltage signal and output a detection result. A temperature compensating device including the foregoing current detecting circuit. A display device including the above temperature compensating device.

Abstract: Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Abstract: An apparatus relating generally to voltage conversion includes an amplifier coupled to receive an input voltage and a reference voltage. First and second converters are coupled to the amplifier to receive a bias voltage. The first converter includes a first transconductor coupled to receive the bias voltage to adjust a first tail current, and a first differential input. A first inverter of the first converter has a first feedback device coupled input-to-output to provide a first transimpedance amplifier load. The first inverter is coupled to the first transconductor. The second converter includes a second transconductor coupled to receive the bias voltage to adjust a second tail current, and a second differential input. A second inverter of the second converter has a second feedback device coupled input-to-output to provide a second transimpedance amplifier load. The second inverter is coupled to the second transconductor.

Abstract: The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit.

Abstract: Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal.

Abstract: Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.