Including Details Of Sampling Or Holding Patents (Class 327/91)
  • Patent number: 8368430
    Abstract: A sample and hold circuit includes an operational amplifier; a sampling capacitor configured to sample input voltages at a plurality of different timings; an adding/subtracting unit configured to perform an adding or subtracting operation of the input voltages sampled by the sampling capacitor; and an offset voltage removing unit configured to remove an input offset voltage component of the operational amplifier from a voltage obtained by the adding or subtracting operation. The operational amplifier is configured to produce an output by holding the voltage from which the input offset voltage component of the operational amplifier has been removed by the offset voltage removing unit.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: February 5, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hikaru Watanabe
  • Patent number: 8344759
    Abstract: A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: January 1, 2013
    Assignee: CSR Technology Inc.
    Inventors: Rolf Sundblad, Staffan Gustafsson
  • Patent number: 8319527
    Abstract: Methods and systems for analog to digital converter and systems incorporating the same are provided. Specifically, an analog sampler that has a reduced input current is disclosed. According to the present teaching, an apparatus for sampling an input voltage includes a first switch having its first terminal connected to an input voltage, and a first pre-charging circuit, coupled to a second terminal of the first switch, that provides a first pre-charged voltage that is substantially equal to the input voltage. The first pre-charged voltage is provided at the first terminal of the first switch before the first switch is turned on. The apparatus further includes a second pre-charging circuit coupled to both the first pre-charging circuit and the second terminal of the first switch, where the second pre-charging circuit charges the first pre-charged voltage prior to the first switch being turned on.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: November 27, 2012
    Assignee: Linear Technology Corporation
    Inventor: Todd Stuart Kaplan
  • Patent number: 8305114
    Abstract: A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert F. Payne
  • Patent number: 8305131
    Abstract: A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: November 6, 2012
    Assignee: Maxim Integrated, Inc.
    Inventor: Hae-Seung Lee
  • Publication number: 20120268304
    Abstract: A switched-capacitor circuit which comprises a first sampling capacitor, a second sampling capacitor, an op-amp, a third capacitor, and a fourth capacitor is provided. The first sampling capacitor is disposed to sample an input signal in a sampling phase. The second sampling capacitor is disposed to sample the input signal in the sampling phase. Wherein, in a first amplify phase, the third capacitor stores an offset voltage of the op-amp, the fourth capacitor stores the electric charges which are flowed from the first sampling capacitor and the second sampling capacitor, and in a second amplify phase, the fourth capacitor gives the stored electric charges back to the first sampling capacitor and the second sampling capacitor.
    Type: Application
    Filed: April 25, 2011
    Publication date: October 25, 2012
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: JIN-FU LIN, CHIA-HSUAN HUANG
  • Patent number: 8294648
    Abstract: A grayscale current generating circuit and an organic light emitting diode (OLED) display using the same, and a display panel and a driving method thereof. An exemplary display device according to an embodiment of the present invention includes a display unit having a plurality of data lines for transmitting a data current, a plurality of scan lines for transmitting a selection signal, and a plurality of pixel areas defined by the data lines and the scan lines. The display device includes a data driver for transforming a plurality of grayscale data into the data current and applying the data current to the data lines. In addition, the display device may include a scan driver for sequentially applying the selection signal to the plurality of scan lines. The data driver includes a first current generator for generating a plurality of first currents and a plurality of digital/analog (D/A) converters.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: October 23, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventor: Oh-Kyong Kwon
  • Patent number: 8258819
    Abstract: Traditionally, latched comparators have suffered from performance problems related to exposure of the latch to load capacitances. Even attempts to isolate the latch from the load capacitances by way of resistors has resulted in performance problems (namely, voltage swing degradation). Here, however, a latched comparator is provided that employs inductors to generally provide isolation from load capacitances, which generally improves performance. Moreover, the latch has been modified to accommodate the inductors during a track period (namely, provision of grounding paths).
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: September 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Vaibhav Tripathi, Marco Corsi, Venkatesh Srinivasan
  • Patent number: 8258850
    Abstract: A general-purpose Analog Signal Processing System (ASPS) is disclosed. An ASPS can be realized though an array of Configurable Integrator Blocks (CIBs). The CIBs can be identical to each other, and arranged in rows and columns. A CIB can merge multiplication, integration, and sample-and-hold functions into a single programmable circuit block. Within the ASPS, CIBs are interconnected in a manner that allows CIB inputs to be a combination of external signals and outputs of other CIBs, and allows CIB outputs to be combined to produce system (external) outputs or inputs to other CIBs. This networked architecture combined with the basic functionality of each CIB, enables implementation of a broad range of analog signal processing operations. The ASPS can be field programmable. The field programmability permits end users to be able to quickly and inexpensively fabricate customized analog integrated circuits.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: September 4, 2012
    Assignee: Interstate Electronics Corporation
    Inventors: Christopher Jude Pagnanelli, William W. Jones
  • Patent number: 8222926
    Abstract: A track and hold circuit (1) comprising a switch device (10) and a capacitive hold device (20). The track and hold circuit (1) comprises a track-voltage generating device (30) adapted to generate a control voltage based on a signal on an input terminal of the switch device (10) and supply the control voltage to the switch device (10) during track phases of the track and hold circuit (1). The control voltage provides a channel charge, which is the same for each track phase, in the switch device (10).
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: July 17, 2012
    Assignee: CSR Technology Inc.
    Inventors: Rolf Sundblad, Staffan Gustafsson
  • Publication number: 20120163794
    Abstract: A level transition determination circuit includes a multi-phase clock generator, an oversampling unit, and a state detection circuit. The multi-phase clock generator is used for receiving an input clock signal and generating S×N clock signals, in which S and N are integers. Each clock signal is synchronized to the input clock signal and has a different delay time. The oversampling unit is used for performing N-times oversampling on M bit periods of the serial input data according to the clock signals, so as to generate M×N sampled values in parallel during the M bit periods. The state detection circuit is used for receiving (M×N)+1 sampled values and generating N detection signals by detecting level transitions between adjacent sampled values of the (M×N)+1 sampled values and the level transition results.
    Type: Application
    Filed: July 27, 2011
    Publication date: June 28, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jung Mao LIN, Ching Yuan Yang
  • Patent number: 8183889
    Abstract: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: May 22, 2012
    Assignee: Kenet, Inc.
    Inventors: Lawrence J. Kushner, Michael P. Anthony, John S. Fisher
  • Patent number: 8179165
    Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: May 15, 2012
    Assignee: Oracle America, Inc.
    Inventors: Hanh-Phuc Le, Robert P. Masleid
  • Patent number: 8169251
    Abstract: A capacitor interface circuit is provided. A capacitor under test (CUT) is divided into a variable portion and an invariable portion, and the capacitance of an offset capacitor is designed to equal to or close to the fixed capacitance of the CUT. The offset capacitor is used to store the charges opposite to the invariable portion of the CUT for neutralizing the effect of the invariable portion of the CUT. Thereupon, the charge converter composed by the fully-differential amplifier and the feedback capacitors only responses for the variable portion of the CUT so as to increase the accuracy of the follow-up data processing.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: May 1, 2012
    Assignee: ITE Tech. Inc.
    Inventor: Ping-Pao Cheng
  • Patent number: 8164362
    Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.
    Type: Grant
    Filed: March 8, 2004
    Date of Patent: April 24, 2012
    Assignee: Broadcom Corporation
    Inventors: Morteza Cyrus Afghahi, Esin Terzioglu
  • Publication number: 20120081153
    Abstract: A system and methods for synchronizing quantized sampled data in a monitoring device. A variable frequency output signal is coupled to an analog to digital converter. A fixed frequency clock is coupled to the analog to digital converter. The analog to digital converter samples the output signal at a fixed frequency to produce high speed samples. A group of initial high speed samples is stored from the analog to digital converter over a fixed window of time. The group of initial high speed samples is interpolated to produce a group of fewer low speed samples from the initial group of high speed samples over the fixed window of time. The group of low speed samples is stored as a representation of the variable frequency output signal.
    Type: Application
    Filed: September 30, 2010
    Publication date: April 5, 2012
    Applicant: SCHNEIDER ELECTRIC USA, INC.
    Inventors: Ronald W. Carter, Kurt H. Copley
  • Patent number: 8145175
    Abstract: The sampling filter apparatus 100 includes the first sampling switch 130, the second sampling switch 131, the first integrator 1500 for integrating the charge input from the first sampling switch, the second integrator 1501 for integrating the charge input from the second sampling switch, a plurality of integrators connected to both of the first integrator and the second integrator via a charging switch, respectively, the control section 140, a plurality of charging switches, and a plurality of discharge switches. A charge input from the sampling switch 130, a charge accumulated in the capacitor 1500 and a charge accumulated in a capacitor 1510 are shared by the capacitor 1500, the capacitor 1510 and the capacitor 1530, and the charge accumulated in the capacitor 1530 is output.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: March 27, 2012
    Assignee: Panasonic Corporation
    Inventors: Kentaro Miyano, Yoshifumi Hosokawa, Katsuaki Abe, Noriaki Saito, Kiyomichi Araki
  • Patent number: 8143922
    Abstract: A sampling circuit for sequential sampling of a broadband periodic input signal having a field effect transistor as a nonlinear component to which a pulsed-shaped sampling signal is supplied, by which sampling is activated so that an output signal is produced. In this way, a sampling circuit is attained which is economical, technically durable and which can be used in a versatile and simple manner.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: March 27, 2012
    Assignee: Krohne S.A.
    Inventors: Michael Gerding, Burkhard Schiek, Thomas Musch
  • Patent number: 8120388
    Abstract: A comparator includes a sampling capacitor, a first switching unit which is connected to an input end of the sampling capacitor and which applies an input signal to the input end of the sampling capacitor, a second switching unit which is connected to the input end of the sampling capacitor and which applies a reference signal to the input end of the sampling capacitor, an output transistor connected to an output end of the sampling capacitor in a source follower connection manner or an emitter follower connection manner, and a third switching unit which is connected to an output end of the sampling capacitor and which maintains maintaining a voltage at the output end of the sampling capacitor to be constant. The input signal is compared with the reference signal.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: February 21, 2012
    Assignee: Sony Corporation
    Inventors: Yasuhide Shimizu, Shigemitsu Murayama, Yukitoshi Yamashita, Junji Toyomura
  • Patent number: 8115518
    Abstract: An integrated circuit allows for the correction of distortion at an input of a sampling network. The integrated circuit contains a first bootstrap circuit to drive a sampling network transistor and a second bootstrap circuit to separate the back-gate terminal of the transistor from a voltage input by a resistance inserted in series. The presence of the inserted resistance counteracts the effect of the nonlinear back-gate capacitance on the distortion at the input.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: February 14, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Ahmed Mohamed Abdelatty Ali
  • Patent number: 8089302
    Abstract: The present application relates to an apparatus comprising a first transistor element, with at least three terminals, and at least one switching unit. The present application relates also to a method, computer readable medium having a computer program stored thereon and a track and hold circuit comprising the apparatus. The apparatus comprises a first transistor element with at least three terminals, wherein a first terminal is supplied with a first voltage, and wherein a second terminal is supplied with a second voltage. The apparatus comprises a first switching unit, wherein a third terminal is connected to ground potential via the first switching unit. The transistor element comprises a predefined threshold voltage. The first voltage and the second voltage are predefined alternating voltages.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: January 3, 2012
    Assignee: NXP B.V.
    Inventors: Simon Minze Louwsma, Maarten Vertregt
  • Patent number: 8063667
    Abstract: A peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier. A source/emitter of the correction transistor is coupled to the operational amplifier. The peak hold circuit also includes a current detection circuit, which detects current flowing to the input transistor, and a peak current hold circuit, which holds the peak value of the current detected by the current detection circuit as a peak current and supplies the peak current to the correction transistor.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: November 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Kazuhiro Tomita
  • Patent number: 8049555
    Abstract: An electronic device includes a cascade of a plurality of transistors. Each transistor of the cascade receives an input voltage at a first terminal of its source/drain channel and receives a sampling clock signal at a control gate. The second terminal of the source/drain path of a first transistor drives a sampling capacitor. The second terminal of the source/drain channel of each subsequent transistor is connected to a backgate of a previous transistor. The backgate of the last transistor is connected to a supply voltage level. The second terminals of the subsequent transistors may be connected to corresponding buffer capacitors. The backgate of the last transistor may be supplied with the input during sampling and the supply voltage level at other times.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Matthias Arnold, Bernhard Ruck, Aymen Landoulsi
  • Patent number: 8044688
    Abstract: Various embodiments of the present invention provide systems and circuits that provide for out of band detection. As one example, an out of band detection circuit is disclosed that includes an input signal, a clock generation circuit, and a sampling circuit. The clock generation circuit receives the input signal and derives therefrom a sampling clock, and the sampling circuit is operable to sample the input signal at a time indicated by the sampling clock.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: October 25, 2011
    Assignee: Agere Systems Inc.
    Inventors: Mingdeng Chen, Ari Valero-Lopez, Weiwei Mao
  • Publication number: 20110254592
    Abstract: A sampling circuit samples an input signal by using at least one switch, at least one capacitor, an amplifier, and a clamp block connected between an output terminal and a negative input terminal of the amplifier. The clamp block prevents a difference between a voltage level of the output terminal of the amplifier and a voltage level of the negative input terminal of the amplifier during sampling from exceeding a maximum voltage difference.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 20, 2011
    Inventors: Min-sun KEEL, Young-kyun Jeong, Won-ho Choi, Ji-hun Shin
  • Patent number: 8035421
    Abstract: A charge sampling circuit, has a control signal generator for controlling an analog input signal to the charge sampling circuit to be integrated by an integrator during a sampling phase responsive to a sampling signal from the control signal generator. The current of the analog input signal is integrated to an integrated charge for producing a proportional voltage or current sample at a signal output at the end of the sampling phase.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: October 11, 2011
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventor: Jiren Yuan
  • Patent number: 8031097
    Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: October 4, 2011
    Assignee: Mediatek Inc.
    Inventors: Wei-Hsuan Tu, Tzung-Hung Kang
  • Publication number: 20110210763
    Abstract: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
    Type: Application
    Filed: August 26, 2010
    Publication date: September 1, 2011
    Applicant: Kenet, Inc.
    Inventors: Lawrence J. Kushner, Michael P. Anthony, John S. Fisher
  • Patent number: 7994968
    Abstract: A gated peak detector produces phase-independent, magnitude-only samples of an RF signal. Gate duration can span as few as two RF cycles or thousands of RF cycles. Response is linearly proportional to RF amplitude while being independent of RF phase and frequency. A quadrature implementation is disclosed. The RF magnitude sampler can finely resolve interferometric patterns produced by narrowband holographic pulse radar.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: August 9, 2011
    Assignee: McEwan Technologies, LLC
    Inventor: Thomas Edward McEwan
  • Patent number: 7990183
    Abstract: One of differential signals is inputted to a first input terminal. The other of the differential signals is inputted to a second input terminal. A first sample hold circuit samples the signal inputted to the first input terminal and hold it thereafter. A second sample hold circuit samples the signal inputted to the second input terminal and holds it thereafter. A comparison unit compares a signal corresponding to a difference between respective output signals from the first and the second sample hold circuits, with a predetermined threshold value. A latch circuit latches an output from the comparison unit. Sample timings of the first and the second sample hold circuits and a latch timing of the latch circuit can be adjusted independently.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 2, 2011
    Assignee: Advantest Corporation
    Inventor: Shoji Kojima
  • Patent number: 7986170
    Abstract: Noise is more effectively reduced in one circuit. When sampling and holding is performed, switching of an ON resistance of MOS transistors (MSH1 and MSH2) that are for sampling is made in two or more stages according to speed of sampling. Here, a level adjustment circuit (20) is provided that generates sample-and-hold pulse signals (?SH1S and ?SH2S), which vary voltage to enable switching the ON resistance of the MOS transistors (MSH1 and MSH2), to be provided to gates of the MOS transistors (MSH1 and MSH2).
    Type: Grant
    Filed: March 19, 2009
    Date of Patent: July 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshizumi Haraguchi
  • Patent number: 7982526
    Abstract: Exemplary embodiments of the disclosure include adaptively generating a bias current for a switched-capacitor circuit. An exemplary apparatus includes a first phase signal and a second phase signal operating at a sampling rate. An asserted time of the first phase signal and an asserted time of the second phase signal are separated by a predefined non-overlap time. The apparatus also includes a switched-capacitor circuit with a plurality of switched capacitors operably coupled to the first phase signal and the second phase signal. An amplifier is operably coupled to the switched-capacitor circuit and has a response time inversely proportional to an adaptive bias current. A bias generator is coupled to the amplifier and operates to modify the adaptive bias current responsive to the asserted time of the first phase signal.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: July 19, 2011
    Assignee: QUALCOMM, Incorporated
    Inventor: Chun C. Lee
  • Publication number: 20110170640
    Abstract: Disclosed are a sampling circuit and a receiver with which filter characteristics compatible with the reception of wideband signals can be realized with a high degree of freedom in the setting of the filter characteristics. More specifically, a sampling circuit capable of removing adjacent interfering wave signals while keeping in-band deviation small is disclosed. The sampling circuit (100) is equipped with a discrete-time analog processing circuit group (101) wherein multiple discrete-time analog processing circuits are connected in parallel, a synthesizer (102) which synthesizes the output signals from each of the circuit systems and outputs same, and a digital control unit (103) which outputs control signals.
    Type: Application
    Filed: December 3, 2009
    Publication date: July 14, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Yohei Morishita
  • Patent number: 7969203
    Abstract: An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: June 28, 2011
    Assignee: NXP B.V.
    Inventors: Qiong Wu, Kevin Mahooti
  • Patent number: 7969336
    Abstract: A sample-hold circuit includes a voltage-current converter, having a first input terminal pair to which an input differential signal is input and a first output terminal pair which outputs current according to the voltage of the input differential signal, a spreading switch having a switch group which switches the first output terminal pair to inverting or non-inverting states, and an integrator having a second input terminal pair coupled to the first output terminal pair via the spreading switch, an output amplifier which outputs to a second output terminal pair an output differential signal amplified according to the differential signal at the second input terminal pair, a capacitor pair which is provided respectively between the second input terminal pair and second output terminal pair, and which is charged or discharged by current input to the second input terminal pair, and a reset circuit which resets charge states of the capacitor pair.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Limited
    Inventor: Masato Yoshioka
  • Publication number: 20110148375
    Abstract: A power amplifying circuit includes a first field effect transistor and a second field effect transistor that are connected in series, are interposed between a high potential power line and a low potential power line, and drive a load; a predriver that generates, in response to an input signal, gate voltages applied to the first field effect transistor and the second field effect transistor respectively; and a variable power source that supplies source voltages to the high potential power line and the low potential power line respectively, and is configured to control the source voltages.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 23, 2011
    Applicant: Yamaha Corporation
    Inventor: Nobuaki Tsuji
  • Patent number: 7956917
    Abstract: The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.
    Type: Grant
    Filed: August 16, 2010
    Date of Patent: June 7, 2011
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Seiichiro Mizuno, Haruhiro Funakoshi
  • Patent number: 7956652
    Abstract: A semiconductor integrated circuit has a sampling circuit which samples a potential of an input terminal, a dynamic comparator having a standby and a comparison mode which compares the potential of the input terminal and a reference potential, a switch for input signals connected between the input terminal and the dynamic comparator, a capacitor for comparator having one end connected between the switch for input signals and the dynamic comparator and another end connected to a fixed potential, and a timing control circuit which controls a timing to sample by sampling circuit, a timing to switch modes of dynamic comparator, and a timing to make switch for input signals conducting or blocking state. The timing control circuit makes the switch for input signals blocking state from conducting state before the dynamic comparator switches from standby mode to comparison mode, and terminates sampling by sampling circuit after switching modes.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shigeki Tomisato
  • Patent number: 7940091
    Abstract: Methods and apparatus for sampling an input voltage and apparatus incorporating the same are disclosed. An input voltage sampling apparatus includes a voltage sampling circuit coupled to the input voltage and configured to produce a sampled input voltage at an output terminal, and a voltage charging circuit coupled to the voltage sampling device and producing a first charged voltage on a first charged voltage output terminal and a second charged voltage on a second charged voltage output terminal. A voltage charging enabling circuit is coupled to the voltage charging circuit, the voltage sampling device via the first connection, and a power supply voltage. Further, the input voltage sampling apparatus includes a control circuit coupled to the voltage sampling circuit, the voltage charging circuit, and the power supply voltage, ground, third and fourth pulse signals. The first and third pulse signals are non-overlapping with the second and fourth pulse signals.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: May 10, 2011
    Assignee: Linear Technology Corporation
    Inventors: Srikanth Govindarajulu, Andrew Joseph Gardner, Robert C. Chiacchia
  • Patent number: 7936187
    Abstract: A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: May 3, 2011
    Assignee: NXP B.V.
    Inventors: Qiong Wu, Kevin Mahooti
  • Publication number: 20110089978
    Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.
    Type: Application
    Filed: December 28, 2010
    Publication date: April 21, 2011
    Inventors: David Maes, Bharath Mandyam
  • Patent number: 7907004
    Abstract: There is provided a signal processing apparatus including a variable capacitor and a switching portion for switching the circuit mode between a sampling mode, in which the variable capacitor samples an input signal, a holding mode, in which a charge gained by sampling the input signal is held in the variable capacitor, and an output mode for outputting the charge stored in the variable capacitor, wherein the variable capacitor is provided with an input terminal through which the input signal is inputted in the sampling mode, a control terminal to which a first control signal which decreases the capacitance of the variable capacitor to a value below the capacitance in the sampling mode is inputted in the output mode, and a second control signal having a predetermined reference voltage is inputted in the holding mode, where an insulating layer is provided between the control terminal and the input terminal.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: March 15, 2011
    Assignee: Sony Corporation
    Inventors: Atsushi Yoshizawa, Sachio Iida
  • Publication number: 20110043256
    Abstract: Methods and devices for forming a series of samples of a filtered version of an input signal. Multiple tap current cells each generate a tap current from the signal. Multiple distribution means couple the tap current cells with multiple integrating means. The distribution means is controlled by a first clock signal. The multiple integrating means integrate tap currents that they receive and these integrating means form the samples. The tap currents generated are each sent to each integrating means in a predetermined sequence according to the first clock signal. The integrating means each use integrating and sampling phases controlled by a second clock signal. During the integrating phase an integrating means receives tap currents in sequence, while during the rest phase, no tap currents are received and the contents of the circuit are sampled and the integrator means is reset.
    Type: Application
    Filed: November 14, 2008
    Publication date: February 24, 2011
    Applicant: Kaben Wireless Silicon Inc.
    Inventors: Tom Riley, Qinghong Du, Sami Karvonon
  • Patent number: 7863943
    Abstract: In embodiments of the present invention a device, circuit, and method are described for sampling input signal voltages, which may include voltages below a negative supply voltage for the device or circuit, without requiring static current from the input. Various embodiments of the invention obviate the requirement of an external negative supply voltage or attenuation resistors to allow sampling between a positive and negative voltage range. These embodiments result in a lower power sampling solution as well as simplifying any driver circuitry required by the sampler. The embodiments of the invention may be applied to sampling processes within analog-to-digital converters and may also be applicable to various other types of circuits in which a sampling input having input voltages that are lower than its negative supply voltage.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 4, 2011
    Assignee: Maxim Integrated Products, Inc.
    Inventors: David Maes, Bharath Mandyam
  • Patent number: 7847600
    Abstract: Methods and apparatus are disclosed to track and hold a voltage. An example track and hold circuit comprises a first electronic switch, a second electronic switch, and a current mode logic amplifier.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: December 7, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Leslie, Antonio David Sebastio, Bhajan Singh
  • Patent number: 7847601
    Abstract: A comparator includes a plurality of switches, a capacitor, an amplifier, and a latch. The switches provide an input signal during a first period and provide a reference signal during a second period. A first switch among the switches is composed of a first transistor. The capacitor receives the input signal during the first period and receives the reference signal during the second period. The amplifier is coupled to the capacitor for receiving a difference voltage between the input signal and the reference signal and amplifies the difference voltage during the second period to generate an amplified result. The determining circuit provides a digital signal according to the amplified result.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: December 7, 2010
    Assignee: Mediatek Inc.
    Inventor: Yu-Kai Chou
  • Patent number: 7843233
    Abstract: A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.
    Type: Grant
    Filed: March 15, 2007
    Date of Patent: November 30, 2010
    Assignee: Cambridge Analog Technologies, Inc.
    Inventor: Hae-Seung Lee
  • Patent number: 7843232
    Abstract: A dual mode, single ended to fully differential converter structure is incorporated into a fully differential sample and hold structure which can be coupled with an ADC as a front end for mixed mode applications. The structure incorporates additional switches which allow negative and positive charges to be sampled on both negative and positive sides of the structure. By inverting the sampled charge on one side, single ended to fully differential conversion is obtained. The structure can be implemented in a compact, generic block which performs single ended to fully differential conversions as well as sample and hold functions, without compromising speed and accuracy in either mode.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: November 30, 2010
    Assignee: ATMEL Corporation
    Inventors: Bilal Farhat, Renaud Dura, Daniel Payrard
  • Publication number: 20100271076
    Abstract: A sampling circuit including a number of state elements or flip-flops. The state elements or flip-flops are each clocked by a signal that causes them to sample their inputs at a predetermined time. In sampling a plurality of digital inputs, a captured delay chain value is stored by the sampling circuit. Each flip-flop holds one bit and together the total number of bits represent this captured delay chain value. Each flip-flop is provided with a data and a data complement signal as an input, the data and data complement signal being substantially simultaneous. In operation each flip-flop includes a direct connection of the data and data complement signals to a pair of transistors that further operate to capture the logical value carried by the input.
    Type: Application
    Filed: April 27, 2009
    Publication date: October 28, 2010
    Applicant: Sun Microsystems, Inc.
    Inventors: Hanh-Phuc Le, Robert P. Masleid
  • Patent number: 7812646
    Abstract: An integrated electronic device includes a sample and hold stage. The sample and hold stage has a sampling capacitor (C) for an input voltage at an input node (Vin), a first switch (S1) coupled between the input node (Vin) and the sampling capacitor (C) for connecting the input node (Vin) to the sampling capacitor (C). There is also a voltage follower with an input coupled to the sampling capacitor (C). The first switch (S1) includes a first MOS transistor (NM1) coupled between the input node (Vin) and the sampling capacitor (C). The first MOS transistor has a bulk. The sample and hold stage is adapted to selectively couple the bulk to a node having a voltage level (V3) which is equal or close to the voltage level at the input node of the voltage follower.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: October 12, 2010
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Marcin K. Augustyniak, Bernhard Wicht, Ingo Hehemann