Including Details Of Sampling Or Holding Patents (Class 327/91)
  • Patent number: 7804336
    Abstract: A track-and-hold circuit is provided. This track-and-hold circuit is adapted to track an analog input signal and hold a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. Preferably, the track-and-hold circuit includes a bi-directional current source that sources and sinks current through a first output node and a second output node, a unity gain amplifier that is coupled to first and second output nodes of the bi-directional current source and that receives the analog input signal, a resistor coupled to an output of the unity gain amplifier, and a capacitor coupled between the resistor and ground. Of interest, however, is the bi-directional current source, which includes a differential input circuit that is adapted to receive the track signal and the hold signal and that is coupled to the first and second output nodes and an RC network that is coupled to the differential input circuit.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: September 28, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert F. Payne
  • Patent number: 7804337
    Abstract: A track-and-hold or sample-and-hold (S/H) circuit for an analog-to-digital converter (ADC) is provided. A difference between the disclosed S/H circuit and conventional S/H circuits is the use of a peaking circuit. This peaking circuit generally provides increased current to switching transistor when transitioning between track and hold which can increase the Spurious-Free Dynamic Range (SFDR) as low frequencies, by as much as 15dB.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: September 28, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Robert F. Payne, Marco Corsi
  • Patent number: 7795947
    Abstract: An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: September 14, 2010
    Assignee: ST-Ericsson SA
    Inventors: Marco Zamprogno, Germano Nicollini, Alberto Minuti
  • Publication number: 20100225358
    Abstract: A method and a device for canceling an offset voltage in an output of a comparator circuit include sampling a set of offset voltages; applying a set of correction voltages equal in magnitude and opposite in polarity to the set of offset voltages, the set of correction voltages being applied to an output generating arrangement of the comparator circuit; and enabling output of the output generating arrangement after the set of correction voltages is applied.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 9, 2010
    Inventors: Stephen Robert KOSIC, Eric John SIRAGUSA
  • Patent number: 7791380
    Abstract: A current sampling circuit including a current sampling transistor, a capacitor arrangement between the gate and source of the current sampling transistor and an amplifier provided in a feedback loop between the gate and source of the current sampling transistor. A switch controls the circuit to sample a gate-source voltage corresponding to a current being sampled onto the capacitor arrangement. The capacitor arrangement comprises a first capacitor circuit for sampling a gate source voltage in a first sampling phase and a second capacitor circuit, with the first and second capacitor circuits arranged for together sampling the gate source voltage in a second sampling phase. The operating point of the amplifier is shifted between the first and second phases based on the gate source voltage sampled in the first sampling phase.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: September 7, 2010
    Assignee: TPO Displays Corp.
    Inventors: Nicola Bramante, Martin John Edwards, John Richard Ayres
  • Patent number: 7786767
    Abstract: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode analog inputs, on a node ‘Vcmi’. An alternative, switched-capacitor-based sensing scheme is also possible. Using this measured Vcmi, adjustments are then made to the rest of the sampler/converter to take out any variations observed at Vcmi.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: August 31, 2010
    Assignee: Kenet, Inc.
    Inventors: Lawrence J. Kushner, Michael P. Anthony, John S. Fisher
  • Patent number: 7782096
    Abstract: A track-and-hold circuit capable of tracking an analog input signal and holding a sampled voltage of the analog input signal at a sampling instant for processing by other circuitry, in response to a track signal that alternates with a hold signal. A first capacitor is provided, having a first terminal connected to a power supply terminal. Tracking circuitry operates when in an on state to apply through a resistor a tracking voltage to a second terminal of the first capacitor that corresponds to the voltage of the analog input signal, by applying the tracking voltage to a first terminal of the resistor, the second terminal of the resistor being connected to the second terminal of the first capacitor. A switch, responsive to the track signal and the hold signal, operates to switch the tracking circuitry to an on state in response to the track signal and to an off state in response to the hold signal, the time of change from the track signal to the hold signal comprising the sampling instant.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: August 24, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert Payne
  • Patent number: 7772892
    Abstract: A main driver amplifier generates first differential signals (Vdp/Vdn) based on pattern data (PAT). A replica driver amplifier generates second differential signals (Vcp/Vcn) based on the pattern data (PAT). Two subtractors generate electric potential difference signals (HP=RP?Vep) and (HN=RN?Ven), respectively. Two sample hold circuits sample the electric potential difference signals (HP and HN), and hold them thereafter, respectively. A comparison unit compares a differential amplitude signal (DA=HHP?HHN) with a predetermined threshold value (VOH). A latch circuit latches an output from the comparison unit. Sampling timings of the two sample hold circuits and a latch timing of the latch circuit, can be adjusted independently.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: August 10, 2010
    Assignee: Advantest Corporation
    Inventor: Shoji Kojima
  • Patent number: 7773332
    Abstract: A sample and hold circuit is disclosed that provides longer hold times. The sample and hold circuit can be used in a disc drive to provide improved read-to-write and write-to-read mode transitions. The sample and hold circuit has an input and an output, and includes at least one capacitive element for retaining a charge. The capacitive element is connected to a node between the input and the output. The sample and hold circuit includes at least one input switch to selectively connect the capacitive element to the input and at least one output switch to selectively connect the capacitive element to the output. In addition, an amplifier is connected to the node and has an offset voltage. In this manner, a voltage drop across at least one of the input and output switches is limited to the offset voltage.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: August 10, 2010
    Assignee: Agere Systems Inc.
    Inventors: Jonathan H. Fischer, Michael P. Straub
  • Patent number: 7755398
    Abstract: A time constant calibration device includes: a first voltage generating circuit utilizing a first current passing through a capacitive component to generate a first voltage; a second voltage generating circuit utilizing a second current passing through a resistive component to generate a second voltage; and a comparing circuit for comparing the first voltage with the second voltage to generate a comparing signal, wherein the first voltage generating circuit comprises an analog adjusting component for adjusting the first voltage according to the comparing signal until the first voltage is equal to the second voltage, whereby an RC time constant defined by an equivalent capacitance corresponding to the first current passing through the capacitive component and an equivalent impedance corresponding to the second current passing through the resistive component reaches a predetermined value.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: July 13, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Song-Rong Han, Ming-Shih Yu
  • Patent number: 7750715
    Abstract: A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: July 6, 2010
    Assignee: AU Optronics Corporation
    Inventors: Chao-Ching Hsu, Mu-Lin Tung, Chung-Shen Cheng
  • Patent number: 7746260
    Abstract: A multiplying digital-to-analog converter includes an operational amplifier (OP-amp) operated under a first power supply voltage and a second power supply voltage; an OP-amp input switch block coupled to a common mode voltage for selectively coupling the common mode voltage to input nodes of the OP-amp, wherein all switches included in the OP-amp input switch block are implemented utilizing PMOS transistors only, and the common mode voltage is substantially equal to the first power supply voltage; a capacitor block coupled to the OP-amp input switch block; a sampling switch block coupled to the input signal for selectively coupling the input signal to the capacitor block; a reference voltage switch block coupled to the capacitor block for selectively coupling the reference signal to the capacitor block; and a feedback switch block coupled between the capacitor block and output nodes of the OP-amp.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: June 29, 2010
    Assignee: Mediatek Inc.
    Inventors: Wei-Hsuan Tu, Tzung-Hung Kang
  • Patent number: 7737732
    Abstract: A sample-data analog circuit includes a level-crossing detector. The level-crossing detector controls sampling switches to provide a precise sample of the output voltage when the level-crossing detector senses the predetermined level crossing of the input signal. A multiple segment ramp waveform generator is used in the sample-data analog circuits. The ramp waveform generator includes an amplifier, a variable current source, and a voltage detection circuit coupled to the current source to control the change in the amplitude of the current. The ramp generator produces constant slope within each segment regardless of the load condition. The sample-data analog circuit also utilizes variable bandwidths and thresholds.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: June 15, 2010
    Assignee: Cambridge Analog Technologies, Inc.
    Inventor: Hae-Seung Lee
  • Patent number: 7728650
    Abstract: Switches with passive bootstrap that can achieve good sampling performance are described. In one design, a sampling circuit with passive bootstrap includes first and second filters and a switch. The first filter filters an input signal and provides a filtered input signal. The second filter filters a clock signal and provides a filtered clock signal. The switch receives a control signal formed based on the filtered input signal and the filtered clock signal and either passes or blocks the input signal based on the control signal. The first filter may be a lowpass filter having a first corner frequency that is higher than the bandwidth of the input signal. The second filter may be a highpass filter having a second corner frequency that is lower than the fundamental frequency of the clock signal. The first and second filters may both be implemented with one resistor and one capacitor.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: June 1, 2010
    Assignee: QUALCOMM Incorporated
    Inventor: Jan Paul van der Wagt
  • Patent number: 7724043
    Abstract: A common mode controller circuit (60) for maintaining a common mode voltage (Vcm) at a first node (52) and a second node (54) in a sample-and-hold circuit receiving a pair of AC coupled differential input signals (Vinp, Vinn) includes first and second resistors (R1/R2) and third and fourth resistors (R3/R4), each set of resistors connected in series between the first and second nodes, and a differential amplifier (A1) having an inverting input terminal coupled to a third node (62) between the first and second resistors, a non-inverting input terminal coupled to a reference voltage (Vref) and an output terminal coupled to a fourth node (64) between the third and fourth resistors. The common mode voltage is sampled at the third node and the differential amplifier provides a sourcing output current indicative of the difference between the sampled common mode voltage and the reference voltage to drive the fourth node.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: May 25, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Robert J. LeBoeuf, II, Matthew Courcy
  • Patent number: 7724041
    Abstract: In a circuit arrangement including a sample-and-hold device, the sample-and-hold device includes a first, a second, a third and a fourth charge store, and also a first and a second input terminal for feeding in a differential input signal comprising a first and a second component. A differential output signal is output via a first and a second output terminal. The charge stores are charged with the first or the second component of the differential input signal in a first phase of a time segment. In a second phase of the time segment, the differential output signal is generated in a manner dependent on the charges of the first, second, third and fourth charge stores.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 25, 2010
    Assignee: Infineon Technologies AG
    Inventor: Dieter Draxelmayr
  • Patent number: 7724042
    Abstract: An input signal to be sampled by a sample and hold circuit is amplified separately by two amplifiers. The output of the first amplifier is provided to a boost circuit to maintain the impedance of a sampling switch contained in a signal dependent boost switch substantially constant. The output of the second amplifier is sampled via the sampling switch, and the sample is stored in a storage element. The second amplifier drives a reduced load, and may be implemented as a low bandwidth, low power amplifier to reduce overall power consumption.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: May 25, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sumeet Mathur, Ankit Seedher, Preetam Charan Anand Tadeparthy
  • Patent number: 7696792
    Abstract: A track and hold circuit is disclosed, including: a source follower coupled to a voltage supply; a MOS transistor with well structure, the MOS transistor having a gate terminal coupled to a gate terminal of the source follower, a drain terminal coupled to its body terminal and a source terminal of the source follower, and a source terminal coupled to a current source and an output terminal; a capacitive device having a terminal coupled to the gate terminal of the MOS transistor and another terminal coupled to a fixed voltage level; and a switch device coupled and disposed between an input signal and the gate terminal of the MOS transistor, wherein the switch device is controlled by a control signal.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: April 13, 2010
    Assignee: Realtek Semiconductor Corp.
    Inventor: Cheng-Chung Hsu
  • Publication number: 20100073040
    Abstract: There is provided a frequency divider using a latch structure including: a first latch sampling and latching an input signal in response to a first clock signal and a second clock signal having an inverse phase with respect to the first clock signal; a second latch toggled with the first latch, the second latch sampling and latching the input signal in response to the first and second clock signals; a bias adjustor generating a sampling bias current and a latching bias current to supply to the first and second latches, respectively and adjusting a relative ratio between the sampling bias current and the latching bias current to vary a minimum power point oscillating frequency of the first and second latches.
    Type: Application
    Filed: May 27, 2009
    Publication date: March 25, 2010
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byeong Hak JO, Yoo Sam NA
  • Patent number: 7683677
    Abstract: A sample-and-hold amplification circuit comprises an amplifier, a first sample-and-hold unit, and a second sample-and-hold unit. The amplifier has an input terminal and an output terminal. The first sample-and-hold unit is coupled to the input terminal and the output terminal. The second sample-and-hold unit is coupled to the input terminal and the output terminal. When the first sample-and-hold unit is arranged to perform a sampling operation, the second sample-and-hold unit performs a holding operation, and when the first sample-and-hold unit is arranged to perform the holding operation, the second sample-and-hold unit performs the sampling operation.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: March 23, 2010
    Assignee: Mediatek Inc.
    Inventor: Yu-Kai Chou
  • Patent number: 7680618
    Abstract: A calibration method for an oversampling acquisition system uses a digital calibration signal that has a period between edges that is unrelated to the period of a sample clock. The calibration signal in input in parallel to a plurality of samplers, each of which is clocked at a different time by a delayed version of the sample clock, to produce a plurality of sequential samples per sample clock period. Edge transitions of the calibration signal are counted that occur between adjacent ones of the samplers, and are accrued over an acquisition period to produce a plurality of edge counts. The edge counts are then processed to produce control signals to adjust the sample clock delay for each sampler so that the time intervals between the sequential samples are essentially uniform.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 16, 2010
    Assignee: Tektronix, Inc.
    Inventor: Kevin C. Spisak
  • Patent number: 7663424
    Abstract: A low charge injection, low clock feed-through switch (1) has an input signal (Vin) applied both to the sources of first (S1) and second (2) switching transistors. A first clock signal (P) having pulses of a first duration ts is applied to a gate of the first switching transistor, and a second clock signal (Pcoarse) having pulses of a second duration m×ts substantially less than the first duration is applied to a gate of the second switching transistor. A capacitor (C) is charged toward the input voltage through both the first and second switching transistors during the pulse of the second clock signal. The capacitor is charged further toward the input voltage during a remaining portion of the pulse of the first clock signal.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: February 16, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Paul Stulik
  • Patent number: 7656200
    Abstract: Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventor: Sami Hyvonen
  • Patent number: 7635996
    Abstract: The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter. The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E?) and a respective differential output (S, S?). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T1a, T1a?) powered by a voltage tapped off from the terminals of the storage capacitor (C?, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca?) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T2a, T3a, SC1a; T2?a, T3?a, SC1a?) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: December 22, 2009
    Assignee: Atmel Grenoble S.A.
    Inventor: Richard Morisson
  • Patent number: 7636075
    Abstract: A data current sample and hold circuit having an input terminal of a current source type and an output terminal of a current sink type. The sample and hold circuit includes a first transistor, a capacitor, and a plurality of switches, for sampling and holding the data current sunk to an output terminal of a data driver. When the sampled and held data current is applied to the data line, the data current is sunk to an output terminal of the sample and hold circuit. The sample and hold circuit is used together with a data driver having an output terminal of the current sink type.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: December 22, 2009
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventor: Dong-Yong Shin
  • Patent number: 7633327
    Abstract: A signal integrator and method for integrating a continuous current and a discrete charge in which the discrete charge is provided for integration during multiple overlapping time intervals.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: December 15, 2009
    Assignee: National Semiconductor Corporation
    Inventors: Zhenyong Zhang, Jian-Yi Wu
  • Patent number: 7626524
    Abstract: A multi-channel sample and hold circuit includes an operational amplifier, plural electric charge setting channels. Each of the electric charge setting channels includes an input terminal, an electric charge setting capacitor, an electric charge setting switch connected between the input terminal and the electric charge setting capacitor, a channel separating switch connected between the electric charge setting capacitor and the input terminal of the operational amplifier and a holding switch and a control circuit for selecting one of the electric charge setting channels to hold a signal that is inputted to the input terminal thereof.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: December 1, 2009
    Assignee: Denso Corporation
    Inventor: Masakiyo Horie
  • Publication number: 20090284285
    Abstract: A switched-capacitor decimator that can attenuate undesired signal components at odd harmonics of an output sample rate is described. In one design, the switched-capacitor decimator includes at least one sampling capacitor and multiple switches. For each sampling capacitor, the top plate is charged with a first input signal when the capacitor is selected for top charging, and the bottom plate is charged with a second input signal when the capacitor is selected for bottom charging. For each sampling capacitor, the top plate provides its stored charges to a first output signal and the bottom plate provides its stored charges to a second output signal when the capacitor is selected for reading. The switches couple the at least one sampling capacitor to the first and second input signals for charging and to the first and second output signals for reading.
    Type: Application
    Filed: May 13, 2008
    Publication date: November 19, 2009
    Applicant: QUALCOMM INCORPORATED
    Inventor: Russell Fagg
  • Patent number: 7612586
    Abstract: A low noise analog sampling circuit that includes a transistor connected to a first feedback loop and to a second feedback loop. During a second operational phase the second feedback loop provides the transistor a feedback signal that is responsive to an amplified error signal; wherein the error signal represents a difference between (i) a sampled signal representative of a state of the transistor short period before a first feedback loop was opened and (ii) a signal representative of a current state of the transistor; wherein at an end of the second operational phase the second feedback loop is opened and introduces a second noise that is attenuated by multiple capacitors.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: November 3, 2009
    Assignee: Advasense Technologies (2004) Ltd.
    Inventor: Vladimir Koifman
  • Publication number: 20090237119
    Abstract: A semiconductor integrated circuit has a sampling circuit which samples a potential of an input terminal, a dynamic comparator having a standby and a comparison mode which compares the potential of the input terminal and a reference potential, a switch for input signals connected between the input terminal and the dynamic comparator, a capacitor for comparator having one end connected between the switch for input signals and the dynamic comparator and another end connected to a fixed potential, and a timing control circuit which controls a timing to sample by sampling circuit, a timing to switch modes of dynamic comparator, and a timing to make switch for input signals conducting or blocking state. The timing control circuit makes the switch for input signals blocking state from conducting state before the dynamic comparator switches from standby mode to comparison mode, and terminates sampling by sampling circuit after switching modes.
    Type: Application
    Filed: March 13, 2009
    Publication date: September 24, 2009
    Inventor: Shigeki Tomisato
  • Publication number: 20090219058
    Abstract: A correlated double sampling circuit has a sampling capacitor equally divided into a plurality of portions. In the correlated double sampling circuit, an input signal is sampled at a plurality of sampling points and an averaging switch is closed to obtain an average value of a plurality of sampling values obtained by sampling. High frequency noise superimposed on the input signal is thus reduced and a difference between the average values of the plurality of sampling values obtained by sampling is output.
    Type: Application
    Filed: October 27, 2006
    Publication date: September 3, 2009
    Inventor: Makoto Ohba
  • Publication number: 20090212824
    Abstract: A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 27, 2009
    Inventor: Costantino Pala
  • Patent number: 7579896
    Abstract: A method and apparatus are disclosed for generating multiple separate analog signals using a single microcontroller output pin. The microcontroller generates a waveform that is used to concurrently generate multiple separate analog signals. The microcontroller outputs a waveform that includes a first signal from one of the microcontroller's output pins. The first signal is used to produce a first analog signal. The microcontroller then outputs a delineating signal, as part of the waveform, from the microcontroller's output pin. The delineating signal indicates the start of a next signal in the waveform. The microcontroller then outputs a second signal, as part of the waveform, from its output pin. The second signal is used to produce a second analog signal. The waveform includes the first signal that is followed by the delineating signal that is followed by the second signal.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: August 25, 2009
    Assignee: International Business Machines Corporation
    Inventors: Robert Allan Faust, John Daniel Upton
  • Publication number: 20090206885
    Abstract: A track and hold circuit (1) comprising a switch device (10) and a capacitive hold device (20). The track and hold circuit (1) comprises a track-voltage generating device (30) adapted to generate a control voltage based on a signal on an input terminal of the switch device (10) and supply the control voltage to the switch device (10) during track phases of the track and hold circuit (1). The control voltage provides a channel charge, which is the same for each track phase, in the switch device (10).
    Type: Application
    Filed: January 18, 2007
    Publication date: August 20, 2009
    Applicant: SICON SEMICONDUCTOR AB
    Inventors: Rolf Sundblad, Staffan Gustafsson
  • Patent number: 7564273
    Abstract: Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical ground. A first comparator input terminal in communication with the switched-capacitor network is configured to receive a node voltage therefrom during a first phase. The second input terminal is configured to receive one of the high-limit voltage and the low-limit voltage. The voltage-offset network provides a voltage shift at the first input terminal setting an input reference level at a mid-level voltage with respect to the high-limit voltage and the low-limit voltage.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: July 21, 2009
    Assignee: Massachusetts Institute of Technology
    Inventors: Matthew C. Guyton, Hae-Seung Lee
  • Patent number: 7545296
    Abstract: The invention relates to an interleaved track and hold circuit for tracking and holding a value of a continuous input signal and to provide discrete values thereof, wherein the circuit comprises a first and a second stage. To avoid tones caused by differences in the non-ideal elements when switching through several parallel second stages the circuit according to the invention comprises a single first stage and at least two second stages.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: June 9, 2009
    Assignee: Broadcom Corporation
    Inventors: Klaas Bult, Frank van der Goes
  • Patent number: 7541845
    Abstract: In the semiconductor integrated circuit, an apparatus for detecting a logic state represented by an input signal includes a reference signal generating circuit and a determining circuit. The reference signal generating circuit generates a reference voltage based on a previously received input signal voltage, and the determining circuit determines a logic state represented by a currently received input signal voltage based on the reference voltage.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: June 2, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwang-Sook Noh
  • Patent number: 7541846
    Abstract: A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: June 2, 2009
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Jen Yen, Chih-Yuan Hsieh, Chiu-Hung Cheng
  • Publication number: 20090128196
    Abstract: A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element.
    Type: Application
    Filed: November 13, 2008
    Publication date: May 21, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Taiki UEMURA, Yoshiharu TOSAKA
  • Patent number: 7532042
    Abstract: A sampling circuit includes an input voltage source; a first switch having an input operatively connected to the input voltage source; a sampling capacitor operatively connected to an output of the first switch; an operational amplifier having an inverting input operatively connected to the sampling capacitor; a second switch operatively connected across the inverting input of the operational amplifier and an output of the operational amplifier; and a second capacitor operatively connected to the output of the first switch. The first switch has a variable parasitic capacitance, and the second capacitor has a substantially more linear capacitance than the variable parasitic capacitance and is in parallel with the variable parasitic capacitance. A combined variable parasitic capacitance and capacitance of said switch capacitor is more linear than the variable parasitic capacitance of the first switch.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: May 12, 2009
    Assignee: Cambridge Analog Technologies, Inc.
    Inventor: Hae-Seung Lee
  • Patent number: 7501863
    Abstract: A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventors: Bruce Querbach, Randall B. Hamilton, Luke A. Johnson, Minyoung Kim
  • Patent number: 7499069
    Abstract: A light scanning device and a method thereof are provided. The device is under control of a controller for controlling an image-forming apparatus and includes a second S&H signal generator, light output part, and a light output controller. The second S&H signal generator generates a plurality of second S&H signals, each consisting of a sampling interval and a holding interval and generated using a first S&H signal provided from the controller. The light output part outputs a plurality of lights and the light output controller controls the light output part to generate the plurality of lights for the respective sampling intervals of the plurality of second S&H signals and sets a control signal value controlling intensities of lights to be maintained for the holding intervals of the plurality of second S&H signals on the basis of the intensities of the generated light. Accordingly, standardization of an interface between parts is simplified.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: March 3, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-min Lee
  • Patent number: 7479810
    Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: January 20, 2009
    Assignee: Intel Corporation
    Inventors: Budiyanto Junus, Luke A. Johnson
  • Patent number: 7477078
    Abstract: Variable phase bit sampling implementations are disclosed which minimize requirements for downstream digital processing resynchronization in systems that incorporate adjustable bit phase sampling that utilize variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit operative to provide an output signal in response to a data signal, where the sampling circuit includes a data input and a clock input. A variable delay circuit provides an adjustable trigger signal to the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount of time in response to at least one delay control signal.
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: January 13, 2009
    Assignee: Synthesys Research, Inc
    Inventors: Andrei Poskatcheev, Senthil Thandapani, Clint Fincher
  • Publication number: 20090002035
    Abstract: A comparator circuit according to an embodiment of the present invention includes a comparator configured to compare an input signal voltage with a reference voltage obtained by smoothing the input signal by use of a resistor and a capacitor, and output a result of the comparison, a discharge circuit configured to compare a first addition signal which is obtained by adding a positive first voltage to the input signal voltage, with the reference voltage, and discharge the capacitor when the first addition signal is lower than the reference voltage, and a charge circuit configured to compare a second addition signal which is obtained by adding a negative second voltage to the input signal voltage, with the reference voltage, and charge the capacitor when the second addition signal is higher than the reference voltage.
    Type: Application
    Filed: June 27, 2008
    Publication date: January 1, 2009
    Inventors: Tatsuya Yamamoto, Tsuneo Suzuki, Yuusuke Maeda, Souichi Honma
  • Publication number: 20080309375
    Abstract: A duty cycle and phase placement sampling circuit that can be used for high accuracy sampling and correcting the duty cycle and placement of differential clock signals is provided. The duty cycle and phase placement sampling circuit includes dual differential input stages and re-timed precharge signals that allow for high accuracy sampling of common mode logic clock phases.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 18, 2008
    Inventor: Curt Schnarr
  • Patent number: 7459943
    Abstract: A high accuracy sample and hold circuit including a first switch, a second switch, a first capacitor, a second capacitor and an amplifier is disclosed. The first capacitor receives and saves a sampling voltage from the first switch during a first period, while the second capacitor receives and saves another sampling voltage from the second switch during a second period. The amplifier has first and second positive input terminals, a negative input terminal, an output terminal and a first input stage and an output stage. Wherein, the first input stage includes a first input set and a second input set. During the first period, the amplifier disables the operation of the first input set and enables the operation of the second input set, while during the second period, the amplifier enables the operation of the first input set and disables the operation of the second input set.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: December 2, 2008
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chih-Jen Yen, Chih-Yuan Hsieh
  • Patent number: 7453291
    Abstract: Circuits that provide a gate boost to address non-linear threshold voltage variation in a CMOS T/H circuit. In embodiments of the invention, a boost capacitor and a feedback amplifier add a signal-dependent threshold voltage to the switch gate over-drive voltage of a switch that controls track and hold circuit sampling. In a modified embodiment, capacitive boost is omitted and the feedback amplifier provides the signal-dependent threshold voltage boost. In another embodiment, a boost capacitor and a diode connected transistor provide the signal-dependent threshold voltage boost. In a modified embodiment, capacitive boost is omitted and the diode connected transistor provides the signal-dependent threshold voltage.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: November 18, 2008
    Assignee: The Regents of the University of California
    Inventor: Bang-Sup Song
  • Patent number: 7436221
    Abstract: An analog storage cell circuit includes a switch that minimizes subthreshold conduction and diode leakage, as well as an accumulation-mode coupling mechanism to minimize overall switch leakage to minimize accumulation-mode leakage. In one embodiment, an analog storage circuit includes a sample and hold circuit including an amplifier having first and second inputs and a switch coupled to the first input of the amplifier. The switch includes a first switching device forming a core of the switch, a second switching device coupled to the first switching device to disconnect the first switching device from a first terminal during the hold phase, and a third switching device coupled to the first switching device to connect the first switching device to a second terminal during the hold phase to minimize accumulation mode conduction in the first switching device.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: October 14, 2008
    Assignee: Massachusetts Institute of Technology
    Inventors: Micah Galletta O'Halloran, Rahul Sarpeshkar
  • Patent number: RE41792
    Abstract: Integrated circuitry for selectively introducing capacitance and for controlling the transconductance transfer function of one or more amplifiers includes concatenated differential amplifiers with one or more pairs of switchable capacitive components differentially connected across outputs of the differential amplifiers to facilitate operation over a wide range of operating frequencies under control of external signals.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: October 5, 2010
    Assignee: Marvell International Ltd.
    Inventors: Sehat Sutardja, Pantas Sutardja