Abstract: An embodiment of a circuit switches between at least a first clock signal and a second clock signal in response to a corresponding switch command, and includes a selection module to select at a switch instant said second clock signal under the control of a signal selector. The circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal.

Abstract: Semiconductor circuit capable of selecting a corresponding adjusting parameter to adjust the received signal according to different voltages and frequencies. A voltage detector detects a voltage level of an external power voltage to generate a voltage detection signal, a frequency detector detects frequency of a main clock to generate a frequency detection signal, and a signal adjustment unit receives a first signal and selects one of a plurality of different adjusting parameters to adjust the first signal according to the voltage detection signal and the frequency detection signal.

Abstract: A system and method for seamlessly reprogramming clock frequencies includes a phase locked loop (PLL) that generates CPU and double data rate (DDR) clocks. A crystal is used to generate a reference clock. The CPU clock and the reference clock are inputs to a first multiplexer, and the DDR clock and reference clock are inputs to a second multiplexer. In normal operation the multiplexers provide the CPU and DDR clock signal as outputs. To reprogram the clock frequencies and reset the PLL, (1) the reference clock signal is selected to be the output of both multiplexers, so the device is running on the internal reference clock. The mux switching is synchronized with the CPU and DDR clock signals. (2) The PLL is reprogrammed, its internal voltage-controlled oscillator is reset, and the PLL is restarted at the new desired frequency. (3) When the new PLL frequency output is stable, the multiplexers are switched back to the PLL-generated CPU and DDR clocks, synchronously with the reference clock signal.

Abstract: A clock synchronization unit is provided for an electronic system, particularly for a microprocessor, that includes a first input for a first clock signal, a second input for a second clock signal, a third input for a select control signal, and an output for a system clock signal. A first control module controlled by the first clock signal, a second control module controlled by the second clock signal and connected to the first control module in terms of signaling technique is also provided. The first control module upon application of a predefined signal level of the select control signal at the third input synchronously with the first dock signal, is designed to set the system clock signal from the first clock signal to a predefined logic signal level as the system clock hold signal, and the second control module is designed, synchronously with the second clock signal, to reset the system clock hold signal and to cause an output of the second clock signal as the system clock signal.

Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: A clock switching circuit for switching between plural clock signals includes a selector for outputting a first control signal when a low speed clock is selected by a selection signal with a permission signal halted, and a second control signal when a high speed clock is selected by the selection signal with a second permission signal halted. The switching circuit includes a first stabilizer for holding the first control signal in timed with the low speed clock to output the second permission signal, and a second stabilizer for holding the second control signal in timed with the high speed clock to output the first permission signal. The switching circuit includes a first and a second gating cell circuit for latching and outputting the low speed clock and the high speed clock when the second permission signal and the first permission signal is supplied, respectively.

Abstract: The invention provides a signal coupling circuit and method for coupling an analog input signal to a processing circuit. The signal coupling circuit includes a number of first coupling units, a second coupling unit and a first multiplexer. The first coupling units are coupled to a first input terminal of the processing circuit, for respectively receiving a plurality of input signals. The first multiplexer is coupled between the first coupling units and the processing circuit for selecting one of the input signals and transmitting the selected input signal to the processing circuit. The second coupling unit is coupled to a second input terminal of the processing circuit, for receiving a common reference signal, wherein the processing circuit uses the common reference signal as reference for processing some or all of the input signals.

Abstract: There is described a method for increasing an availability and a redundancy of an analog current output as well as an analog current output with increased availability and redundancy. To improve the availability and also the redundancy behavior of an analog current output a first set of current sources is switched to active to generate an output current, one current source respectively of the first set is checked cyclically for serviceability and the other current sources respectively generate the output current in equal parts. Where unserviceability is determined, the corresponding current source is disconnected and removed from the first set. If a malfunction occurs, such as a failure of a current source for example, the output current advantageously does not drop out completely due to the allocation of generation to a number of current sources.

Abstract: An integrated circuit having cascade-connected multiplexers and a precharge unit. The cascade-connected multiplexers each have a plurality of data inputs, a data output, wherein each data input and each data output has two terminals for the application of a dual-rail signal, and a control input, wherein a signal present at the control input defines which of the data inputs is connected to the data output. The precharge unit, which is driven with a precharge unit control signal, is connected to the data output or at least one of the data inputs of one of the multiplexers to thereby bring the data outputs and/or data inputs of the multiplexers into a precharge state before execution of a computation operation.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: A voting scheme for analog signals is described. An analog block is replicated to provide three analog blocks that are designed to have substantially the same analog output based on receiving substantially the same input. Voting is used to compare the analog outputs from the three analog blocks. In one example, the analog output from one of the three analog blocks having a middle value between the values of the other two analog outputs is provided as an output of the voter circuit. In another example, if the original analog block provides the analog output having the middle value, the output of the original analog block is provided as an output of the voter circuit. Otherwise, an output of another analog block is provided as an output of the voter circuit. In another example, the analog voter circuit determines which of the three analog outputs have been impacted by a transient event based on a non-zero output of transconductor circuits.

Abstract: Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques disclosed herein permit a recovered clock signal to be digitally filtered and applied to the digital clock recovery circuit clock synthesis unit (CSU) as a synchronization reference clock signal, which advantageously eliminates a time base frequency difference to reduce that jitter component and also reduces an intrinsic jitter component associated with jitter already present in the incoming data signal. In one embodiment, a state machine uses a filtered version of a recovered clock signal as a reference when the frequency of the filtered version of the recovered clock signal is relatively close to the frequency of the CSU reference clock signal.

Abstract: A glitch-free clock switching circuit receives a first clock signal and a second clock signal and outputs a third clock signal corresponding to the first clock signal or a fourth clock signal corresponding to the second clock signal according to a clock switching signal. The glitch-free clock switching circuit switches to output clock signals by stopping output of a clock signal, and then waiting for a predetermined period of time before outputting another clock signal.

Abstract: A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.

Abstract: The present disclosure relates to a system, apparatus and method for a line driver circuit to generate a signal detect (SD) signal when an invalid data signal is detected at its input. An invalid signal may be present either when no signal is available or when the line driver circuit or another component in the system (e.g., a crosspoint switch, a multiplexer, etc.) fails. The SD signal is coupled to an external controller that can either power down the line driver circuit to save power when no signal is available, or change over to a different line driver circuit or other component of the system when a failure is identified. When the input signal is determined to be a valid data signal via the SD signal, the line driver circuit can be enabled for operation. The described systems, apparatus and methods can save the user from having to directly control the line driver power state, especially in systems with large router configurations that may include hundreds of line drivers.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: An improved clock switch in an integrated circuit chip that multiplexes two asynchronous clock signals to generate a multi-frequency clock signal in a manner that avoids glitches on the clock output line and meta-stable states within the switch. The clock switch does not include a cross-coupled feedback loop, thus rendering the clock switch test-friendly and avoiding potential race conditions in the switch. The clock switch is useable with asynchronous clock sources having a variety of different clock frequencies and phases.

Abstract: A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal. The disclosed semiconductor integrated circuit device also includes an output fixing circuit configured to generate a pulse that is maintained at a high level or a low level during a certain period, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.

Abstract: In a first aspect, a first method is provided that includes providing a plurality of select signals and a plurality of input signals for input by a multiplexer. Each select signal is adapted to cause the multiplexer to select a different one of the plurality of input signals for output by the multiplexer when the select signal is in a first logic state. The first method further includes preventing a first of the select signals that is in the first logic state from being provided to the multiplexer until the other select signals are in a second logic state. Number other aspects are provided.

Abstract: An integrated circuit can be switched between operating modes without the need for a dedicated mode selection pin. A circuit for operation at a specified maximum supply voltage comprises first and second supply terminals, a first signal input for application of a regular input signal, a second signal input, and an output. The circuit further comprises a multiplexer with first and second inputs connected to the first and second signal inputs, respectively, for selectively switching either of the first and second signal inputs to the output under control of a selection signal. A gate circuit provides the selection signal to the multiplexer. The input of the gate circuit is driven by control circuitry. Clamping circuitry is provided that limits the voltage at the first input of the multiplexer. With such a circuit design, a relatively high voltage applied to the first signal input will switch the circuit to another operating mode, such as a test mode.

Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.

Abstract: A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.

Abstract: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality of detection signals.

Abstract: A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

Abstract: A clock multiplexer circuit uses a delay element to detect a transition-free period in a first signal present on a D-input lead of an output latch. The output latch is then controlled to latch the stable value of the first signal, and to hold the value of the first signal on an output lead of the clock multiplexer circuit. The clock multiplexer circuit then controls a multiplexer of the clock multiplexer circuit to couple a second signal onto the D-input lead of the output latch. The clock multiplexer circuit then enables the output latch synchronously with respect to the second signal such that the output latch is made transparent at a time when the second signal on the D-input of the output latch is stable and not transitioning. The result is glitch free clock switching from the first signal to the second signal.

Abstract: A glitchless clock multiplexer controlled by an asynchronous select signal for use in GPS receivers is disclosed. A device in accordance with the present invention comprises a device for producing a clock signal, the clock signal being selected from a plurality of asynchronous frequency sources.

Abstract: An operating frequency generating method and circuit for a switching voltage converter are provided. The method includes the following steps. First, a reference clock signal and a digital period signal are received. The phase of the digital period signal is delayed according to at least one different delay time, so as to generate at least one delay period signal. The digital period signal or one of the delay period signals is selected as an operating frequency of the switching voltage converter at every predetermined time interval.

Abstract: A clock switching circuit for switching between plural clock signals includes a selector for outputting a first control signal when a low speed clock is selected by a selection signal with a permission signal halted, and a second control signal when a high speed clock is selected by the selection signal with a second permission signal halted. The switching circuit includes a first stabilizer for holding the first control signal in timed with the low speed clock to output the second permission signal, and a second stabilizer for holding the second control signal in timed with the high speed clock to output the first permission signal. The switching circuit includes a first and a second gating cell circuit for latching and outputting the low speed clock and the high speed clock when the second permission signal and the first permission signal is supplied, respectively.

Abstract: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

Abstract: The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.

Abstract: A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to be a second level and to output the clock as a composite clock for clock switching, for a specified period including one of a leading edge and a trailing edge of the clock as well as additional time before and after the edge, when the signal becomes active while the clock is at a first level; a switching demand signal generation circuit that receives the clock and the signal, and outputs a clock switching demand signal; a clock selection signal generation circuit that changes a level of a first clock selection signal when the signal becomes active; and a first selector that selects one of the clock and the clock, according to the level of the signal, and outputs the selected clock.

Abstract: A clock switching device capable of automatic switching to a clock distribution system for back-up without interrupting processing of the device, which includes an abnormality detection unit which detects lack of coincidence in a logical level between a current clock pulse and a one-cycle preceding clock pulse as abnormality in a waveform on the basis of a plurality of cock pulses, a phase adjustment unit for switching which adjusts a phase of other clock pulse to a phase of a clock pulse being output, and a switching unit which switches to and outputs other clock pulse whose phase is adjusted by the phase adjustment unit for switching based on detection of lack of coincidence in a logical level by said abnormality detection unit.

Abstract: A glitch-free, clock switching circuit in which an asynchronous, sequential logic circuit has as inputs a clock select signal and a pair of clock signals. A plurality of operating state variable signals are generated in the sequential logic circuit in response to transitions in the input signal. A combinational logic clock output circuit is responsive to the input clock signals and predetermined ones of the operating state variable signals for outputting a newly selected clock signal only when said predetermined operating state variable signals indicate the sensing of a falling edge of the currently outputted clock signal followed by a falling edge of the newly selected clock signal.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

Abstract: Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and second sampling circuits selects one of the samples as a retimed version of the frequency-divided clock. The particular sample selected is preferably the sample less likely to produce an erroneous retimed version of the frequency-divided clock.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Reduced glitch occurs in switching from a first clock input to a second clock input driving a clock multiplexer. The clock multiplexer receives a first clock input and provides a clock output and determines a low phase output level in the clock output in response to a low phase input level in the first clock output. For a limited period of time, a low phase output level is forced irrespective of the phase level of the first clock input signal. The clock multiplexer receives a second clock input and determines a low phase input level in the second clock input signal. Switching to providing the clock output in response to the second clock input occurs during the low phase input level in the second clock input signal. Then, the output of the clock multiplexer follows the phase level of the second clock signal.

Abstract: A clock switching circuit comprises PLL circuits into which external clocks CLKT, CLKB are respectively input, a multiplexer for selecting and outputting either an output PLB of one PLL circuit or an inverted signal of an output PLT of the other PLL circuit, and a clock control circuit for subjecting the multiplexer to switching control on the basis of a Lock determination signal that is asynchronous with CLKB and PLB. When the Lock determination signal is input into the clock control circuit, the clock control circuit switches the output of the multiplexer in synchronization with an offset clock PLQB that is offset from the phase of PLB by a predetermined value.

Abstract: A digital clock switching circuit and method is disclosed and is operable to deadlock-free switch a digital clock source for an integrated circuit. The circuit includes a first finite state machine associated with a first clock source and a second finite state machine associated with a second clock source. The finite state machines are connected to each other and monitor the current state of the other finite state machine. Each finite state machine receives an input select signal to control which clock source should be active and passed to a clock output. Each finite state machine includes a counter, wherein the counter associated with the active clock source is initialized to a first predetermined value when the input select signal indicates a switching off of the active clock source. The finite state machine associated with the active clock source enters a CHECK state and varies a count at each clock cycle.

Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.

Abstract: There is provided a semiconductor integrated circuit in which a source clock (S101) is inputted to a delay circuit (3), a counter circuit (6) is operated in response to a delay clock (S102) which is the output of the delay circuit (3), a clock used as a system clock by an internal circuit (4) is selected from the source clock (S101) and the delay clock (S102) based on the value of the counter circuit (6), and the duty cycle of the system clock is changed, so that it is possible to reduce electromagnetic interference resulting from harmonics generated by the switching of the internal circuit.

Abstract: Apparatus and systems, as well as methods and articles, may operate to select a microprocessor clock frequency responsive to a desired voltage and/or a desired temperature of operation.

Abstract: A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to switch between two different input signals and two different clock signals and the use of an S-R flip-flop unit to output either the first input signal or the second input signal during different specified periods. This feature allows the architecture of the proposed multiple-clock controlled logic signal generating circuit to be more simplified than prior art and thus easier to implement.

Abstract: A self-repairable semiconductor comprises a first device and a replacement device. A switching device selectively swaps the replacement device for the first device when the first device is non-operable. The switching device includes an analog switching circuit that selects one of a first pair of differential outputs of the first device having a first common mode voltage and a second pair of differential outputs of the replacement device having a second common mode voltage. The analog switching circuit includes first and second switches having one of a source and drain that communicate with the first pair of differential outputs. Third and fourth switches have one of a source and drain that communicate with the second pair of differential outputs. An amplifier has a first input that communicates with the other of the source and drain of the first and third switches and a second input that communicates with the other of the source and drain of the second and fourth switches.

Abstract: The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.

Abstract: A multiplexer circuit includes a plurality of switched differential amplifier circuits, one of which can be selected at a time. Each switched differential amplifier includes a pair of differential inputs and a pair of differential outputs, with each pair of differential inputs accepting a corresponding pair of input signals. Each of the switched differential amplifier circuits is configured to present a current mode version of its input signals at its differential outputs when the switched differential amplifier circuit is selected, and to present substantially zero level output signals at its differential outputs when the switched differential amplifier circuit is deselected. The multiplexer circuit also includes a selector that accepts a select signal and selects one of the plurality of switched differential amplifier circuits based on said select signal. A current mirror is used to combine a pair of multiplexer outputs into a single ended output, a version of which is used for feedback.

Abstract: An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based on control inputs to the decoder. The synchronized output signals from the decoder are used as trigger signals to the plurality of flip-flops. The flip-flops sample the clock signals based upon the trigger signals and provide outputs to a logic gate. The logic gate operates on the outputs from the flip-flops to generate an output signal indicative of whether glitch-free operation is verified or is not verified.

Abstract: Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and second sampling circuits selects one of the samples as a retimed version of the frequency-divided clock. The particular sample selected is preferably the sample less likely to produce an erroneous retimed version of the frequency-divided clock.

Abstract: Access is provided to internal analog voltage signals on internal analog nodes of an integrated circuit, without distortion of the internal analog voltage signals. An integrated circuit includes a voltage access circuit having buffered multiplexer circuits in proximity to respective groups of internal analog nodes for respective internal analog voltage signals. Each voltage access circuit outputs a selected one of the corresponding group of internal analog voltage signals as a buffered analog node signal. The voltage access circuit also includes a buffering output circuit configured for outputting a selected one of the buffered analog node signals from the respective buffered multiplexer circuits, as a buffered voltage signal, to an output pad configured for supplying the buffered voltage signal to an external probe. Successively larger buffer stages minimize loading on the internal analog nodes, while providing sufficient power for outputting the buffered voltage signal to the external probe.

Abstract: An integrated chip has a clock signal input (1.1) for application of a first clock signal (clk1) and a clock signal output (1.2–1.5). Moreover, it has a phase locked loop (2), which, on the input side, is connected to the clock signal input (1.1) and serves far generating a second clock signal (clk2). Furthermore, the chip has a multiplexer (MUX), via which the first clock signal (clk1) or the second clock signal (clk2) can optionally be switched to the clock signal output (1.2–1.5), and a unit for frequency monitoring (3), which, on the input side, is connected to the clock signal input (1.1) and is designed and can be operated in such a way that, in the event of a limiting frequency (fmin) being undershot, the multiplexer (MUX) is caused to switch the first clock signal (clk1) to the clock signal output (1.2–1.5).

Abstract: A clock switching circuit suitably adapted to stable switching operation of high-frequency multiphase clock signals. The clock switching circuit receives two clock signals and selectively outputs one of the two clock signals in accordance with a selection signal. The clock switching circuit includes a switching controller that transfers the selection signal at the beginning of a period in which both of the two clock signals are active, and an internal selector that selectively outputs one of the two clock signals in response to the selection signal transferred from the switching controller.