Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed relative to clock A to give a signal P, is then retimed relative to clock B to give a signal Q, and finally is retimed relative to clock A to give a signal R. Selector circuitry operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate, are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract: An integrated semiconductor module having at least one terminal for connection to a data bus and having at least one low-pass filter that is connected downstream of the terminal in order to limit the data rate during normal operation. A circuit arrangement is provided for bridging the low-pass filter in order to be able to test the module at a higher data rate.

Abstract: A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, as well as a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit. In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off. A reduced current consumption can be achieved by the present invention in this way.

Abstract: A clock generator (10a) outputs either a first clock signal or a second clock signal. The second clock signal is higher in frequency than the first clock signal. Under control of a control signal (CNTL1), when the first clock signal and the second clock signal are outputted from the clock generator (10a), a selector (81a) transmits the first and second clock signals to a clock transmission line (42) and to a clock transmission line (41), respectively. The clock transmission line (41) is greater in linewidth than the clock transmission line (42). Under control of the control signal (CNTL1), a selector (82a) connects either the clock transmission line (41) or the clock transmission line (42) to the outside.

Abstract: A clock switching circuit comprises:

Abstract: A method of producing a clock signal with reduced electromagnetic interference spectral components includes providing a first clock signal; producing a second clock signal by delaying the first clock signal; and generating a jittered clock signal by switching between the first clock signal and the second clock signal at times selected responsive to a random number generator.

Abstract: A clock generator for providing programmable control of an output clock, the clock generator includes a mechanism for creating a plurality of clocks offset in phase; two programmable selectors for selecting two clocks from the plurality of clocks; and logic for combining the two selected clocks to create an output clock with any combination of offset, if any, and width.

Abstract: A complement reset multiplexer latch is provided. The complement reset multiplexer latch selectively regenerates a first or a second data input signal on an output node. To react to rising edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second rising edge pulse reset control. To react to falling edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second falling edge pulse reset control. The complement reset multiplexer latch also selectively holds the output node at a stored value responsive to a clock signal. A multiplexer is used to select from the first or the second data input the value that is stored.

Abstract: An apparatus for providing a signal having a controlled transition characteristic at an output terminal includes: (A) A signal comparing unit having a plurality of input loci and at least one output locus, receiving a first signal at a first input locus and receiving a second signal at a second input locus. The signal comparing unit presents at least one gating signal having a value depending on relative values of the first signal and the second signal at the at least one output locus. (B) A switching unit coupled with the at least one output locus and receiving the first signal and the second signal. The switching unit switchingly controlling coupling of the first signal or of the second signal with the output terminal in response to the at least one gating signal.

Abstract: A system for allowing an asynchronous clock signal to be selected from a plurality of asynchronous clock signals without causing glitches. In the system, a requestor is connected to control signals. The control signals indicate to the requestor which asynchronous clock signal, of the two or more clock signals, to request. The requestor informs a selector of the request. The selector determines which asynchronous clock signal was selected. The selected asynchronous clock is then detected by the detector. The detector feeds the selected asynchronous clock signal to a signal output. The signal output releases the selected asynchronous clock signal.

Abstract: A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.

Abstract: This invention relates to switching-over to a higher speed clock from a lower speed clock. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.

Abstract: An apparatus and method is disclosed for providing a smooth transition between a first clock signal at a first frequency and a second clock signal at a lower second frequency. A pulse is generated that indicates whether the logic levels of the first and the second clock signals are similar or are different. The rising/falling edges of the pulse are synchronized with the rising/falling edges of the first clock signal. When a change in a logic level of a command signal for switching between the clock signals is detected, a first time period is identified in which the logic levels of the first and the second clock signals are different. The transition between the first clock signal and the second clock signal is allowed immediately after the first time period has ended.

Abstract: A power-up signal generation circuit includes a first power-up detecting unit, to which an external power supply voltage is applied, for activating a first power-up signal when an increase of the external power supply voltage is detected, a second power-up detecting unit, to which an internal power supply voltage is applied, for activating a second power-up signal when an increase of the internal power supply voltage is detected and a power-up signal generating unit for activating a final power-up signal in response to combination of the first and the second power-up signals.

Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.

Abstract: A clock system includes a provisioning layer corresponding to a plurality of input clocks, and a plurality of layers arranged according to a hierarchy. The first layer in the hierarchy is operable to arrange the input clocks into groups and for each group select a corresponding group output clock. The remaining layers in the hierarchy are operable to arrange the group output clocks from a next layer higher in the hierarchy into groups and for each group select a corresponding group output clock. The lowest layer in the hierarchy is operable to select one of the group output clocks from the next layer higher in the hierarchy as a selected clock.

Abstract: A clock multiplexer selects between two asynchronous clock signal inputs to produce a clock signal output such that the clock signal input corresponding to the clock signal output may be denoted as the current clock signal and the remaining clock signal input may be denoted as the selected clock signal. After detecting an edge of a specified type in the current clock signal, the clock multiplexer holds the clock signal output either high or low according to the specified type of clock edge being detected. After detecting an edge of the specified type in the selected clock signal, the clock signal output is released and the selected clock signal allowed to pass.

Abstract: A symmetric glitch free clock multiplexing circuit allows the input clock to a digital or analog processing unit to be switched from one frequency to the other at any moment during the operation, assuming the respective clocks themselves are stable. There exist no restrictions on the clocks or the switch control signal to be synchronous in any fashion. This circuit guarantees a glitch free output and also prevents short cycling of the output clock. Since all the related clocks and switch control signal are asynchronous, this circuit further eliminates meta-stability problems. Its symmetrical architecture allows the circuit to function with the output clock being switched from slow clock to fast clock and vise versa.

Abstract: A signal multiplexer system and a signal latch system for low voltage (Vdd≈1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module.

Abstract: The number of good IC (Integrated Circuit) chips per wafer or time to print a wafer is optimized by examining a number of prospective chip-to-wafer offsets, and, for each offset, a number of prospective arrangements of reticle exposures (shot maps). Integrating such a shot map optimization sub-system with a reticle layout (frame generation) sub-system permits creation of an optimal shot map for an IC chip of known size. These two sub-systems can also be used iteratively to explore a range of possible chip sizes, presenting the results in a simple graphical form. The instant invention integrates shot map optimization, frame generation and chip size optimization/visualization into a single system, providing the chip designer with insight into the impact of chip size on manufacturability.

Abstract: A clock generator circuit accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency created by dividing or multiplying the input clock frequency. In exemplary embodiments having four phased input signals and a duty cycle correction feature, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/2, where X is an integer. In other embodiments not having duty cycle correction, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/4. The delay through the clock generator circuit is minimal, and is independent of the divisor. Variations include programmable divisors and multipliers and optional phase shifting.

Abstract: A clock selection circuit for selecting one of a plurality of clocks as an output clock. When the selection circuit switches between two of the plurality of clocks for output, the currently output clock is removed from the output. The removal of the currently output clock is performed synchronously to the currently selected clock. The newly selected clock is then coupled to the output. Coupling of the newly selected clock is performed synchronously to the newly selected clock.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: The invention relates to a circuit (100) with which one of a plurality of input clock signals (CLK_SRC1, . . . , CLK_SCR_n) can be selected and passed on to an output signal (CLK_OUT). The input clock signals are present at a multiplexer (MUX) which applies one of these signals in dependence upon the selection signal (CFG_i) from its control input to its output. The output signal (MUX_OUT) of the multiplexer is applied via a switch (S) and a signal latch (LATCH) to the output of the circuit as output signal (CLK_OUT). Switching between two input signals is controlled by a state machine (FSM) which first intransparently switches the signal latch (LATCH) after a change of the external configuration signal (CFG), then switches the multiplexer (MUX) and transparently switches the signal latch again after the multiplexer output (MUX_OUT) has changed at least once and assumed the value stored in the signal latch. The state machine (FSM) is supplied with its own fast clock (FCLK).

Abstract: In a signal processing system with an IC having an intrinsic signal provided at a pin of the IC, a first operational function (de-emphasis) for the signal is provided at the pin, and further along in the signal flow path, a second operational function (variable attenuation) for the signal is provided within the IC. An extrinsic signal is switchably coupled to the pin so that the second operational function can be used to operate on the extrinsic signal. The second signal is coupled to the pin at a low source impedance so that when the second signal is switched to be operational, the first operational function is defeated, and the first signal is severely attenuated. When the circuit is switched to not couple the second signal to the pin, the coupling path for the second signal and the low source impedance are both removed, thus restoring the first operational function and the first signal at the pin of the IC.

Abstract: A device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device has a differential amplifier configuration having an input to receive a comparison signal, a plurality of inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also has at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal.

Abstract: The present invention relates to a device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device comprises a differential amplifier configuration having an input to receive a comparison signal, a plurality inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also comprises at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal. Finally, this device incorporates at least one plurality of latches each having at least one input terminal connected to a corresponding output of the differential amplifier configuration and at least one drive terminal coupled to the output terminal of the logic circuit with each of said latch circuits having at least one output terminal corresponding to an output of the selector.

Abstract: The present invention relates to a clock selection circuit which can eliminate short clock signals when switching clock signals produced by one clock generator to clock signals produced by another clock generator.

Abstract: A high speed phase detector utilizes an integrated XOR/MUX circuit having a higher bandwidth and lower power than conventional designs. The XOR/MUX circuit combines the functionality of an XOR device in series with a multiplexer in a manner that increases the bandwidth of the function. In a practical implementation, the XOR/MUX circuit includes an XOR arrangement having a plurality of transistors implemented at a first transistor level and a plurality of transistors implemented at a second transistor level. The XOR/MUX circuit also includes transistors implemented at a third transistor level; these transistors are utilized by the multiplexer feature of the circuit.

Abstract: A multiplexor generating a glitch free output. A slower clock signal and sleep clock signal are respectively synchronized with positive and negative edges of the faster clock signal. The sleep signal is further synchronized with a negative edge of the slower clock signal and provided to an AND gate gating the slower clock signal based on the value of a select signal formed by the synchronized sleep signal. The slower clock signal is delayed by a number of faster clock cycles equal to the time taken by the select signal to be received at the AND gate after the sleep signal is synchronized to the slower clock signal. In an alternative embodiment, a signal control block ensures that the 0 to 1 transition on one of the select signals follows the 1 to 0 transition on another select signal when the value of the sleep signal changes. In addition, each select signal is synchronized with a negative edge of the corresponding clock signal selected.

Abstract: The electronic calibration equipment for verifying the high frequency characteristics of electronic test equipment, including oscilloscopes arid time interval analyzers is provided.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

Abstract: A multi-input comparator in accordance with the invention determines a minimum or maximum signal value in a given set of signal values. An illustrative embodiment of the multi-input comparator includes N inputs and generates an output corresponding to the maximum or minimum value in a set of signal values applied to the N inputs. The comparator includes a first comparison circuit, such as a sense amplifier, having inputs for receiving a subset of the N signal values, such as a pair of the inputs. The comparator also includes a first multiplexer having a select signal input coupled to an output of the first comparison circuit, and inputs coupled to the subset of the N signal values. The comparator further includes N-2 additional comparison circuits and N-2 additional multiplexers, with the N-2 additional multiplexers coupled to corresponding ones of the N-2 additional comparison circuits. The comparison circuits and multiplexers are arranged to select a particular one of the N signal values, e.g.

Abstract: A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.

Abstract: A signal switching circuit has first to fourth diode pairs each comprising two series-connected diodes disposed respectively between a first input terminal and a first output terminal, between a second input terminal and the first output terminal, between the first input terminal and the second output terminal, and between the second input terminal and the second output terminal, and first to fourth capacitor circuits connected respectively between diode-to-diode connection points in the diode pairs and the ground. The first or second diode pair is rendered conductive in an alternative manner. Likewise, the third or fourth diode pair is rendered conductive in an alternative manner. A low pass filter for passing therethrough the corresponding first or second signal uses residual inductance in each of the diode pairs thus rendered conductive and the associated capacitor circuit.

Abstract: A precise and programmable duty cycle adjuster which can produce a user definable duty cycle clock signal comprises a digital to analog converter (DAC), low pass filter (LPF), operational transconductance amplifier (OTA), and a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit employs a number of delay stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. For a fixed number of delay stages, the range of duty cycle selection is inversely proportional to the frequency of an input clock signal. This frequency range limitation is alleviated by designing the VCDCG with a multiple number of delay taps in conjunction with multiple tap points which are multiplexed at the output.

Abstract: An apparatus or method for testing the setup time and hold time specifications of a chip. An apparatus according to the invention would include a first chip, a second chip, and multiple links coupling the first chip to the second chip. One of the links carries a clock signal between the chips. Other links carrying data have propagation delays different from the propagation delay of the link carrying the clock signal. The relation of the delays for the data links to the delay for the clock link determines a particular setup and/or hold time tested.

Abstract: A circuit and a method for generating a variable delay clock without glitches are provided. A DLL clock output circuit comprises a selection circuit. A plurality of select signals selectively switch the corresponding clock delay lines to be the output signal by the selection circuit. Each of the select signals traverses through a delay switching circuit to adaptively delay the time points at which the select signals switch the clock delay lines to the output signal, so as to produce a glitchless variable delay clock signal.

Abstract: This invention relates to switching-over to a higher speed clock from a lower speed clock. The switching-over of the clock is performed before, after, or simultaneously to a transition to a sleep mode is carried out. After the switching-over of the clock is performed, if oscillation of the high speed clock and an internal voltage are stabilized, it is returned to a normal mode from the sleep mode.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare.

Abstract: The invention relates to a clock synchronous type semiconductor device that accepts an input signal inputted from the exterior in synchronization with a clock signal. The semiconductor device according to the invention includes an input signal receiving unit that receives an input signal inputted from the exterior, where the receiving is done in synchronization with a clock signal; a clock timing selecting unit for outputting a clock selecting signal; and a clock generating unit that, in response to receiving a clock selecting signal and an external clock signal, generates a clock signal at a predetermined timing which corresponds to a signal level of the clock selecting signal, and outputs the clock signal to the input signal receiving unit, wherein it is possible to securely accept an input signal regardless of the frequency of the external clock signal.

Abstract: An initial arrangement is effected based on a net list and a cell library. Combination functions are extracted from a cost function. An optimum estimated temperature is calculated based on the difference between values of the cost function before and after two adjacent elements that have been selected randomly from elements to be arranged are interchanged in position, while near-optimum estimated temperatures are calculated based on the differences between respective values of the combination functions before and after the positional interchange. Of the near-optimum estimated temperatures, those lower than the optimum estimated temperature are recorded in a temperature schedule list together with the optimum estimated temperature. Thereafter, the Monte-Carlo method based on a random positional interchange between the elements to be arranged using the cost function is executed in order of the decreasing temperatures recorded in the temperature schedule list, whereby the initial arrangement is improved.

Abstract: A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass transistor. The control voltage is provided by a higher voltage power supply than the power supply that provides the data path reference voltage. In one embodiment, the higher voltage supply is a quiet supply that is not loaded with devices that switch during normal operation of the programmable switch such as CMOS devices. In another embodiment, the power supply that provides a voltage to an I/O circuit of the probable switch is the power supply that is utilized to provide the control voltage to the pass transistors. In a particular embodiment, the pass transistors comprise higher voltage tolerant devices than other devices in the programmable device. In a particular embodiment, the higher voltage supply is at least the data path reference voltage plus the threshold voltage of the pass transistors.

Abstract: A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. At time TA, the select signal transitions to a second state, thereby indicating that the secondary clock signal should be routed as the output clock signal. The first clock signal is prevented from being routed as the output clock signal at time TB, wherein time TB is the first time that the first clock signal has a predetermined logic state after time TA. The output clock signal is held at the predetermined logic state at time TB. The second clock signal is then routed as the output clock signal the first time that the second clock signal transitions to the predetermined logic state after time TB.

Abstract: It is an object of the present invention to provide a semiconductor circuit apparatus that allows an increase in circuit size associated with an increase in number of holders. A counter circuit (102) is used as means for selecting a certain data from data held in a holder. Output data of the counter circuit (102) is compared with data held in the holder by a comparator circuit (103) and data selected according to the result of the comparison is held. This allows a decoder circuit and selector circuit as comparator means to be replaced with the comparator circuit (103) and the holder (106), thereby reducing circuit size.

Abstract: An output interface circuit realizes a fast and stable interface operation without any chip-size increase even if the external supply voltage varies within a specific range (e.g., from 5 V to 3.3 V or from 5 V to 2 V). The output interface circuit comprises a first and a second output buffer circuit for receiving an output signal of an internal circuit, and an output-level adjusting circuit for receiving the output signal of the second output buffer circuit, for level-adjusting the output signal, and for outputting the level-adjusted output signal to an external output terminal. The first or second output buffer circuit outputs a signal based on the value of an external supply voltage.

Abstract: A method and apparatus for switching clocks comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate (i) a first signal in response to a select signal and a first clock signal, (ii) a second signal in response to said first signal and a second clock signal, (iii) a third signal in response to said select signal and said second clock signal, and (iv) a fourth signal in response to said third signal and said first clock signal. The second circuit may be configured to generate a first enable signal and a second enable signal in response to (i) said first signal, (ii) said second signal, (iii) said third signal, and (iv) said fourth signal. The third circuit may be configured to select (i) one or more first input signals, (ii) one or more second input signals, or (iii) a predetermined logic level as one or more output signals in response to said first enable signal and said second enable signal.

Abstract: A circuit to synchronously select one of the multiple clocks is presented. In one embodiment the selection circuit consists of four main blocks. These are the stable selects block, the decoder block, the synchronous selects block, and the output block. The stable selects block takes select signals as inputs and outputs a signal indicating whether the selects are stable or not, in addition to producing select signals that are synchronous to the current selected clock. The decoder block, decodes the select signals if they are stable, otherwise it re-circulates the previous values of the decoded clock select signals. The stable decoded select signals are then passed on to the synchronous selects block. This block outputs select signals in synchrony with their respective clocks. The synchronous select signals along with the stable decoded signals are used in the output block along with the clocks themselves to generate the final output clock.