Abstract: In a clock recovery circuit, a received APSK signal is sampled at a frequency N times higher than the transmitted clock in response to a first clock from a local clock source, and quantized into orthogonal digital APSK samples. An envelope of the orthogonal APSK digital samples is detected (3) and phase correlations are detected (5) between the envelope and locally generated orthogonal sinusoidal signals and averaged by a low-pass filter (6). The arctangent between the low-pass filtered orthogonal signals is detected (7) and applied to a subtracter (8). A threshold comparator (9) compares the subtracter output with N successive values. A digital V.C.O. (10) is supplied with an output signal from the comparator (9) to generate a sample clock f.sub.c at a frequency 1/N of the frequency of the first clock f.sub.s for sampling the digital samples from the A/D converter (1). A phase difference is detected by a phase comparator (12) between the second clock f.sub.c and the sample clock f.sub.

Abstract: A signed phase-to-frequency (`P-to-F`) converter for use in a very high frequency Phase Locked Loop is disclosed. The P-to-F converter receives an input signal indicating plus/minus phase errors and an enable signal. The input signal is converted into a count by a counting circuit. An upper part of the count signal is used to generate a 3-phase sawtooth digital pattern. A lower part of the count is converted by a lower-bit pulse density modulation (`PDM`) circuit to generate a signal indicating the binary weight of the lower part of the count. The output of the lower-bit PDM circuit is applied, along with the 3-phase digital pattern, to three higher-bit PDM circuits. The carry output of the higher-bit PDM circuits is the digital output of the P-to-F converter and is converted from a digital to an analog signal by RC filters. The positive and negative phase error is indicated by the leading/lagging phase among the 3-phase output waveforms.

Abstract: The present invention provides a system and method of automatic frequency control (AFC) in a frequency-shift-key (FSK) data transmission system that allows a receiver to be used that has a bandwidth that approaches the requisite minimum bandwidth for a given data transmission rate and produces a substantial signal noise ratio (SNR) in the detected signal by the receiver. The invention includes a transmitter that outputs a SPACE signal and a MARK signal in a preamble that precedes the transmission data. The apparatus also includes a receiver that uses the SPACE and MARK signals to adjust the frequency of the signal output by a voltage-controlled-oscillator (VCO) to tune the receiver and thereby improve the signal-to-noise ratio (SNR) in the signals subsequently detected by the receiver.

Abstract: A phase-locked loop demodulator comprises a mixer and a loop filter between an input and an output. A voltage-controlled oscillator is connected between its output and an input of the mixer. The demodulator further comprises a lock-on detector circuit whose output signal is adapted to increase the static loop gain after lock-on by modifying the characteristics of the filter.

Abstract: In a coherent M-ary PSK demodulator, an M-ary PSK detector demodulates a received M-ary PSK modulated convolutional code with a carrier recovered by a voltage-controlled oscillator to produce first and second channels of demodulated convolutional codes. A convolutional decoder decodes the signals of the first and second channels while correcting bit errors. An error rate detector is provided for detecting when the number of such errors occurring during a specified period of time is smaller than a predetermined value and generates a signal indicating that the convolutional decoder is synchronized with the demodulated signals. The power levels of signal and noise components of the demodulated channels are detected by a power detector.

Abstract: A signal modulated by original data is received and demodulated to output demodulated data. A number representing the correspondence of the original data with the outputted demodulated data or the lack of correspondence of the original data with the outputted demodulated data is counted. The count result representative of the suitability of the reception state of the receiver is outputted to a data processing circuit.

Abstract: A demodulator for biphase, suppressed-carrier PSK signals, in particular useful for the demodulation of digital information transmitted as an auxiliary information in radio transmission channels, in particular of the "radiodata" kind comprising a filter for the extraction of the portion of the base band spectrum carrying said PSK signals, an amplitude limiter connected to the output of said filter for standardizing the amplitude of said PSK signals, a double-loop circuit receiving the limiter signal comprising a first loop associated with a data transition tracking loop decoder; a second loop constituted by a digital phase-locked loop. The double loop circuit cooperates with a stable oscillator for providing a frequency at a predetermined multiple of the frequency of the suppressed carrier of said PSK signal from the limiter signal.

Abstract: An arrangement for coherently demodulating PSK (phase-shift keying) signals, includes a quasi-coherent demodulator which implements coarse coherent demodulation on an incoming PSK-modulated IF signal using a variable frequency which is applied from a controllable local oscillator. The output of the quasi-coherent demodulator is applied to a coherent demodulator which also receives the output of a VCO (Voltage Controlled Oscillator). A phase detector receives the output of the coherent demodulator and applies the output thereof to the VCO via a loop filter. The output of the loop filter is applied to a local oscillator controller having an output which is used to control the controllable local oscillator.

Abstract: A phase demodulator for directly demodulating carrier PSK signals, PSK-modulated with digital signals, without using any analog circuit. Where the invention is applied to a demodulator of the different detection type, the baud timing signal is converted into a synchronous band timing signal, synchronized with the first leading edge of the PSK signals converted into "1" or "0" in logical level. Meanwhile, the ring oscillator generates signals of a frequency substantially equal to the carrier frequency of the PSK signals, and generates outputs at N taps. the outputs obtained at the N taps have a 2.pi./N phase difference between every pair of mutually adjoining taps, and are latched with the synchronous baud timing signal in each baud period. The point at which the logical level of mutually adjoining latch outputs varies from "1" to "0" is the phase information of said digital signals. The corresponding phase information is encoded to constitute the demodulated output.

Abstract: A lock detector circuit (60) for demodulators of UQPSK signals I and Q has signal processing circuits for forming the signals:A=6I.sup.2 Q.sup.2 -I.sup.4 -Q.sup.4 ;B=4(I.sup.2 -Q.sup.2).A switch (19) is provided for coupling either signal A or signal B to the output (20) of the detector circuit, depending on the value of the signal ratio Q/I. In an alternative embodiment, a summing circuit adds signal A and signal B, and directs the sum to the detector output (20). The resulting output signal is constant under lock conditions, and oscillates when the demodulator is unlocked. This output signal is directed through a comparator (49) to the sweep circuit (43) controlling demodulator VCO (42), and causes the demodulator to remain in the locked condition. The lock detector circuit is effective for any value of Q/I, and utilizes only three analog multiplier circuits.

Abstract: A data referenced demodulator is provided for recovering differentially encoded multiphase modulated digital data such as QPSK modulated audio data. An analog carrier containing the differentially encoded QPSK data is converted to a digital waveform at an intermediate frequency that is a multiple of the QPSK bit frequency. The digital waveform is delayed in a shift register that samples the waveform at a clock rate which is a multiple of the intermediate frequency. Different stages of the shift register output the digital waveform one bit time earlier plus 45.degree. and one bit time earlier minus 45.degree.. These outputs of the shift register are multipled with the digital waveform using exclusive OR gates to provide differential QPSK detection. The shift register sampling clock is phase locked to a system master clock, which in turn is locked to the received data. In an illustrated embodiment, the sampling clock is 24 times the intermediate frequency, providing 15.degree. phase resolution.

Abstract: The present invention is directed to circuitry for achieving an improved carrier synchronization (i.e. estimation of carrier's phase) and data detection for digital data, suppressed carrier transmission systems. A new method--and corresponding apparatus--for pattern jitter cancellation and quadrant ambiguity removal, when incorporated within known or new carrier recovery scheme, results in an improved carrier synchronization and data detection. The resultant carrier recovery and data detection circuitry might be employed for phase estimation and the detection of balanced and unbalanced, coded or uncoded, quadrature amplitude modulation signals. Global positioning system receivers, cable, satellite and radio systems are some examples of where these circuitry might find an application.

Abstract: A QAM demodulator having an adaptive automatic equalizer includes a transversal filter of a band-pass filter type, a reference carrier generator for generating a complex reference carrier, an error detector for obtaining complex error data, and a gain tap coefficient adjusting unit for adjusting the complex gain tap coefficients using the complex error data and the complex reference carrier data. The gain tap coefficient adjusting unit includes first complex multipliers for multiplying the complex data of the reference carrier outputted from the reference carrier generator by the input data, second complex multiplier for multiplying a predetermined coefficient by the complex error data outputted from the error detector, third complex multipliers for multiplying the output data of the first complex multipliers respectively by the output data of the second complex multiplier, thereby obtaining the complex quantity for adjusting the complex gain tap coefficients for the automatic equalizer.

Abstract: A PSK signal which is subject to frequency fluctuation and noise is demodulated through a quasi-coherent detection process with a fixed local frequency oscillator (5) noise elimination process using a low pass filter (17,18) after frequency adjustment, and a frequency and phase regeneration process using a PLL circuit (20). The PLL circuit (20) is updated by the estimated center frequency of a received signal by using an FFT (fast Fourier transform) circuit (11), a power spectrum means (12,13,14), and a frequency estimation circuit (15) estimating the center frequency based upon the fact that the modulated signal component exists only on a high level portion of the frequency spectrum.

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.1, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E.sub.1, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from the relative positions (tf/T) and the phase values (F).

Abstract: A receiver responsive to a noise laden phase modulated signal on a carrier hard limits the signal to derive a constant amplitude phase modulated r.f. signal. The constant amplitude phase modulated r.f. signal is supplied to processing circuitry to derive a digital signal having a value representing the phase of the noise laden carrier. A phase locked loop, including a minimum variance Kalman predictor filter, responds to the noise laden carrier to derive a relatively noise free indication of carrier phase. The noise laden indication of phase and the relatively noise free indication of carrier phase are combined to indicate the phase of the phase modulated signal to which the receiver is responsive.

Abstract: A device for the simultaneous division of a bandpass signal s(t)=x(t) cos .omega.ot-y(t) sin .omega.ot, .omega.o being an arbitrary angular velocity, into its components x(t), y(t), according to two carriers in quadrature cos .omega.ot and -sin .omega.ot at the angular velocity .omega.o, including a filter (3) for filtering the signal s(t), analog transform circuitry (8;25,26) for producing the Hilbert transform s(t) of the input signal s(t) provided in at least one of the channels of the device, a first sampler (6;21) for sampling the input signal s(t) and a second sampler (9;22) for sampling the Hilbert transform s(t), the samplers being controlled at a sampling frequency fe supplied by a sampling oscillator, fe being not less than 2F, F being the difference between fo=.omega.o/2.pi. and the frequency of the spectrum of the filtered input signal s(t) which is most distant from fo, and two analog-digital converters (7,10;23,24), associated with each sampler (6,9;21,22).

Abstract: In a demodulator circuit for receiving a direct sequence spread spectrum signal having composite PN codes, there is provided a novel detecting and tracking circuit for faster acquisition of the component PN codes. The first component code of the received composite direct sequence spread spectrum code is noncoherently detected in a noncoherent detection branch and the subsequent component codes of the composite code are automatically detected in a coherent lock detection branch to provide faster acquisition than was heretofore possible. Further, while the noncoherent detection branch is acquiring the first component PN code, a novel coherent carrier tracking loop is acquiring and locking onto the direct sequence spread spectrum signal carrier.

Abstract: The invention involves an apparatus for recovering the carrier signal in OPSK or QAM data. First an energy directed phase detector controls a voltage controlled oscillator so that the output signal has a phase that is within a few degrees of the carrier phase. Following this coarse acquisition, the system clock timing is recovered and established. A decision directed phase detector, using the system clock information, then controls the VCO to adjust the output signal phase to within a very small tolerance of the actual carrier phase.

Abstract: A digital demodulator (10) operates by multiplying an input signal with first and second orthogonal demodulation reference signals (Loa, LOb) to generate respective product signals, which are then integrated to generate first and second integrated values (a, b) indicative of digital data encoded in the input signal. These integrated values (a, b) are digitized to generate first and second digital values (a, b). A first error signal a-a) indicative of the difference between the first integrated value (a) and the first digital value (a) is generated, and the first error signal (a-a) is combined with the second digital value (b) to generate a first feedback signal. This first feedback signal is utilized to generate a control signal (ab-ba) indicative of phase difference between the input signal and the demodulation reference signals (LOa, LOb).

Abstract: A circuit for recovering the carrier of a digitally modulated wave comprising a voltage-controlled oscillator (17) that is controlled by an error signal .epsilon.(.phi.) in order to adjust the phase of the oscillator, the modulated wave being introduced into two channels, the one in phase (10) and the other in quadrature (20) with the carrier, the two channels being joined together by a phase comparator arrangement (25) which produces the error signal and a sampling clock (H1). The phase comparator arrangement (25) alternately operates as a phase detector and as a frequency detector and therefore comprises an apparatus for selecting received signal points with the aid of selection zones formed by ring segments, situated around certain states of the signal constellation.

Abstract: A synchronizing circuit for offset quaternary phase shift keying, comprises: a four-phase demodulator 10; a processing module (11, 12); and a phase error calculating circuit (15) followed by a phase correcting circuit (16) which delivers a phase error correction signal. The invention is applicable to telecommunications by microwave beams.

Abstract: A phase lock recovery apparatus for a phase locked loop circuit having a voltage controlled oscillator. The apparatus includes a detection circuit coupled to the phase locked loop circuit for detecting a phase unlocked state occurred in the phase locked loop circuit and a sweep signal generator responsive to the detection circuit for sweeping the frequency of the voltage controlled oscillator to come within the lock range of the frequency of the input signal when the phase unlocked state is detected.

Abstract: A circuit for recovering clock information from an incoming data signal preferably in NRZ1 form, the circuit including a VCO (18) providing a clock signal (CK) to four integrate/hold circuits (I1to I4) which receive an incoming data signal, the integrate/hold circuits providing an error signal to the VCO (18) for adjusting the phase thereof to that of the incoming data signal, the integrate/hold circuits being sequenced by logic (10) to provide within each period of the clock signal three functions: (1) an integration of the incoming data signal in every bit period in which a voltage transition occurs, (2) a holding of the integrated value within a subsequent bit period or periods, and (3) a resetting of the integrated value following the next voltage transition in the incoming data signal, whereby the held integrated value, whose magnitude is dependent of the phase of the clock signal relative to the phase of the incoming data signal, provides said error signal.

Abstract: A first phase control loop not including a signal delay part and a second phase control loop including a signal delay part such as an automatic equalizer are formed independently of each other in a demodulator incorporated in a MODEM. The first and second phase control loops are arranged in such a relation that an input to the second phase control loop is not affected by an output of the first phase control loop, so that correction of a frequency offset by the first phase control loop and correction of a frequency jitter by the second phase control loop can be carried out independently of each other. This arrangement facilitates the design of the first and second phase control loops and improves the stability of the phase control system.

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.2, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F).