With Parallel Signal Combiners (e.g., Costas Loop) Patents (Class 329/308)
  • Patent number: 6466086
    Abstract: A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: October 15, 2002
    Assignee: NEC Corporation
    Inventor: Akihiko Syoji
  • Patent number: 6433630
    Abstract: In a demodulator, a local oscillator 7 feeds a local oscillation signal having a frequency of f/n to a phase shifter 8. In the phase shifter 8, all-pass filters 9 and 10 produce two oscillation signals separated in phase by 90/n degrees from each other, which are then fed individually to n-times frequency multiplier 11 and 12. The n-times frequency multipliers 11 and 12 multiply the frequency of those oscillation signals by a factor of n and thereby produce two carriers having a frequency of f and separated in phase by 90 degrees from each other, which are then fed to mixers 2 and 3.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: August 13, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroshi Isoda
  • Patent number: 6356145
    Abstract: A demodulator circuit including: a signal generating circuit for generating a sine-wave signal and a cosine-wave signal whose frequencies are same as that of the carrier wave of a modulated signal, a multiplying circuit for multiplying the modulated signal by the sine-wave signal and the cosine-wave signal generated by the signal generating circuit, and a filtering circuit for eliminating the frequency twice as high as that of the carrier wave from each of the results of the computation conducted by the multiplying circuit. Due to this, no restriction is imposed by the frequency of the system clock signal in configuring the system as a whole.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: March 12, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventor: Yoshihiro Inada
  • Patent number: 6297691
    Abstract: A receiver receives modulated message signals in non-coherent FSK and coherent 8PSK protocols. A selectively configurable processor demodulates the message signals, and includes a demodulator that derives in-phase and quadrature signals based on the message signals. A phase detector is responsive to the in-phase and quadrature signals and delayed in-phase and quadrature signals to derive a phase signal. A selector is responsive to the in-phase and quadrature signals to selectively connect a loop filter between the phase detector and the demodulator. When the selector connects the filter between the phase detector and demodulator, the demodulator is responsive to filtered phase signals to lock onto a frequency of the message signals so that the processor operates as a phase locked loop to demodulate coherent modulated signals.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: October 2, 2001
    Assignee: Rosemount Inc.
    Inventors: Stephen D. Anderson, Daniel V. Hulse, Kevin B. Moore, Paul D. Kammann, Gabriel A. Maalouf
  • Patent number: 6294952
    Abstract: A quadrature demodulator capable of calibrating an I (Q) signal conversion section without stopping the receiving operation performed by the quadrature demodulator. The quadrature demodulator comprises: an adder 32 for generating a pseudo noise superimposed signal obtained by adding a user signal IF and a pseudo noise PN; a signal conversion section 100 for generating a converted signal obtained by mixing the pseudo noise superimposed signal with a local frequency signal L1 of a predetermined local frequency; a first multiplier 72 for generating a correlated signal obtained by multiplying the converted signal with the pseudo noise, a first integrator 82 for integrating the correlated signal to provide an output; and a succeeding circuit 90 for processing the converted signal in a desired way. While performing calibration by causing the first multiplier 72 to extract the pseudo noise, the quadrature demodulator allows the succeeding circuit 90 to process the converted signal in a desired way.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: September 25, 2001
    Assignee: Advantest Corporation
    Inventor: Takashi Kato
  • Patent number: 6249559
    Abstract: In a digital frequency phase locked loop (FPLL) for a grand alliance (GA) HDTV receiver using a vestigial sideband (VSB) modulation transmission system, the digital FPLL for a VSB transmission system having a VCO and a plurality of NTSC carrier eliminating filters for eliminating interference of NTSC adjacent channels includes a filter for eliminating high-frequency components by converting a digital signal output from one of the plurality of NTSC carrier eliminating filters, a delay for delaying the high-frequency-component-eliminated signal by a predetermined width so that its frequency-versus-phase characteristics are changed linearly, symbol inverter for inverting the symbol of the digital signal output from another of the plurality of NTSC-carrier eliminating filters, a switch for selectively outputting the symbol-inverted signal and the digital signal output from another filter, a second filter for limiting the selectively output signal to a predetermined frequency band, a digital-to-analog (D/A) conver
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: June 19, 2001
    Assignee: L.G. Electronics Inc.
    Inventor: Jung-Sig Jun
  • Publication number: 20010003432
    Abstract: A quadrature demodulator applicable to digital communication and digital broadcast is provided, which simplifies the circuit configuration of a quadrature demodulator section and which reduces the labor or man-hours and the time required for adjusting the demodulation characteristic.
    Type: Application
    Filed: December 7, 2000
    Publication date: June 14, 2001
    Applicant: NEC CORPORATION
    Inventor: Akihiko Syoji
  • Patent number: 6208201
    Abstract: The present invention relates to the use of complex non-linear elements in improvements to the recovery of a carrier phase reference from a modulated input signal where the modulation is in accordance with the M-PSK modulation format and where M has a value greater than 4 and the signal-to-noise ratio in the channel is low. A voltage-controlled oscillator is employed to generate first and second oscillations in phase quadrature with respect to each other. The modulated input signal is mixed with the first of the oscillations to detect the (I) signal component and the modulated input signal is mixed with the second of the oscillations to detect the (Q) signal component. A control signal is derived from the (I) and (Q) signal components as an estimate of the phase difference between the input signal carrier and the voltage-controlled oscillator.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: March 27, 2001
    Assignee: Tandberg Television ASA
    Inventor: Garegin Markarian
  • Patent number: 6191649
    Abstract: A quadrature demodulator detects a phase angle error determined from the phase angle supplied from constellation symbols of outgoing in-phase and quadrature components of a modulated signal and and the phase angle of a NCO. The quadrature demodulator comprises a receiving circuit for receiving a quadrature modulated signal, and a local oscillator for generating a local carrier. A complex multiplier demodulates the quadrature modulated signal by complex-multiplying the quadrature modulated signal with the local carrier generated in the local oscillator. A symbol error detector detects a symbol error between the carrier of the modulated signal and the local carrier supplied from the signal demodulated at the complex-multiplier. A feedback loop controls the local carrier generated at the local oscillator by feeding back the symbol error detected at the symbol error detector to the local oscillator.
    Type: Grant
    Filed: July 2, 1999
    Date of Patent: February 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Sugita, Masaki Nishikawa
  • Patent number: 6147560
    Abstract: The present invention relates to methods and devices for such control and supervision of an oscillator signal from a controllable oscillator that is done mainly to control the frequency variation of the oscillator signal. According to the invention, the controllable oscillator is controlled by a controlling voltage, which in turn is modified by a correction signal, generated in a control loop. A time discrete representation of a secondary phase is generated in the control loop, the secondary phase corresponding to a frequency being the difference between the frequency of the oscillator signal and a constant frequency. A time discrete approximation signal is generated in dependence of the time discrete representation of the secondary phase. A time discrete error signal is generated in dependence of the time discrete approximation signal, the time discrete error signal indicating the difference between the actual frequency slope of the oscillator signal and a desired frequency slope.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: November 14, 2000
    Assignee: Telefonaktiebolget LM Ericsson
    Inventors: Lars I. Erhage, Osten E. Erikmats, Svenolov Rizell, H.ang.kan L. Karlsson
  • Patent number: 6125271
    Abstract: A front end circuit for an RF dual band GSM/DCS phone includes a first channel including an elliptical high-pass filter, a first SAW filter, and a low noise amplifier and a second channel including a second SAW filter and a second low noise amplifier. The output of each channel is alternately switchable to a single-side band mixer circuit. This front end circuit arrangement provides significantly reduced cost and part count over other approaches.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: September 26, 2000
    Assignee: Conexant Systems, Inc.
    Inventor: John R. Rowland, Jr.
  • Patent number: 6104237
    Abstract: A signal from a local oscillator is separated by a 90.degree. phase sifter into an in-phase component and an orthogonal component. Each of the components is multiplied by a received IF signal in a mixer to perform pseudo-synchronous detection. The pseudo-synchronously detected signals are subjected to A/D conversion in an A/D converter, and preamble portions are integrated in integrating circuits. The integrated signals are latched in latch circuits. The timing of the latch is controlled by a timing circuit. A power detector detects the power of the latched signal, and the maximum value is detected in a maximum value detector to determine timing at which the power becomes maximum in selectors. A phase (.theta.) is determined from the inverse tangent of the maximum value, and is used as an initial value of a voltage controlled oscillator (VCO) in a demodulator.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: August 15, 2000
    Assignee: NEC Corporation
    Inventor: Tetsuo Mabuchi
  • Patent number: 6100755
    Abstract: A phase decision circuit that can reduce the memory capacity of a ROM forming a look-up table. The quadrant decision section judges the quadrant to which an input signal belongs. The address conversion section converts the I-component digital signal and the Q-component digital signal of an input signal into address data based on the quadrant data. The phase angle data is read out of the ROM look-up table based on the converted address data so that the memory capacity of a ROM forming the ROM look-up table can be reduced to 1/8 of that of the conventional table, for example, in the QPSK modulation.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: August 8, 2000
    Assignee: Futaba Denshi Kogyo Kabushiki Kaisha
    Inventor: Satoru Ishii
  • Patent number: 6091306
    Abstract: Parasitic feedback is prevented in a transmitter, a modulator, or a demodulator from having an interfering influence on the circuit section that generates the mixed frequency. The circuit has a main oscillator and a subordinate oscillator connected downstream of the main oscillator. The main oscillator generates a signal having an x.sup.th harmonic that serves to excite the subordinate oscillator. Furthermore, a frequency divider is connected downstream of the subordinate oscillator. The frequency divider divides the frequency of an output signal of the subordinate oscillator by an integer divider value. The divider value differs from the value x.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: July 18, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventor: Josef Fenk
  • Patent number: 6069524
    Abstract: A FPLL has an I, a Q and a third multiplier, with the I multiplier supplying demodulated signals to a limiter and the Q multiplier supplying signals to a loop filter. A VCO and phase shift circuit supply quadrature signals to the I and Q multipliers. The analog input signal is applied to the I multiplier and to the third multiplier. The third multiplier, which is located in an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents, is also supplied with the digital output of the limiter. The third multiplier supplies its output to the Q multiplier.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: May 30, 2000
    Assignee: Zenith Electronics Corporation
    Inventors: Victor G. Mycynek, Gary J. Sgrignoli
  • Patent number: 6055280
    Abstract: Demodulation and bit synchronization apparatus that uses a plurality of field programmable gate arrays to provide parallel processing to implement demodulation and bit synchronization. An analog-to-digital converter converts and demultiplexes applied intermediate frequency signals having a substantially wide bandwidth to output demultiplexed data signals at a lower clock rate. A digital signal processor processes the demultiplexed data signals to produce detected signals. A plurality of algorithms are implemented in the demodulator and bit synchronizer that include Costas loop demodulators, for example implemented using a carrier loop/lock detector, a direct digital synthesizer and a plurality of multipliers. Eight-tap T/2 baseband equalizers are implemented using in-phase and quadrature-phase accumulators and equalizers, and an in-phase/mid-phase bit synchronizer is implemented using the in-phase accumulator and a mid-phase accumulator and equalizer.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: April 25, 2000
    Assignee: Raytheon Company
    Inventor: Thad Genrich
  • Patent number: 5963597
    Abstract: A data transmission apparatus applicable to transmission of data by the use of a cable of a television camera system or the like and capable of ensuring simplified exact demodulation of data transmitted through quadrature modulation. The apparatus comprises a demodulator for outputting detection signals of the quadrature-modulated signal based on reference signals whose phases are each different by a predetermined value from an I-axis reference signal and a Q-axis reference signal in the quadrature modulation; a signal level corrector for correcting the signal levels of the detection signals; and a signal converter for converting the output signals of the signal level corrector to detection signals based on the I-axis and Q-axis reference signals. An equalizer circuit is further included in the apparatus for adaptively equalizing the output signals of the signal converter or the output signals of the signal level corrector.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: October 5, 1999
    Assignee: Sony Corporation
    Inventor: Hiroshi Okawa
  • Patent number: 5956375
    Abstract: A system and method using a Costas loop to effect accelerated convergence with minimal system complexity. The system comprises an in-phase-limiter and a quadrature-phase limiter, operatively coupled to an EXCLUSIVE-OR gate, for exclusively-ORing an in-phase-sign signal and a quadrature-phase-sign signal to output a first error signal, responsive to the signals having same signs, or a second error signal, responsive to the signals having different signs. An AGC circuit, operatively coupled to an output of the EXCLUSIVE-OR gate, increases and decreases a voltage level of an AGC signal responsive to two consecutive first or second error signals and consecutive dissimilar error signals, respectively. A voltage-controlled oscillator, operatively coupled to an output of the AGC circuit and responsive to the increased or decreased voltage level, changes the frequency of a voltage-controlled-oscillator output signal.
    Type: Grant
    Filed: June 11, 1997
    Date of Patent: September 21, 1999
    Assignee: Golden Bridge Technology, Inc.
    Inventor: Emmanuel Kanterakis
  • Patent number: 5939951
    Abstract: An apparatus is disclosed for processing an input signal. The apparatus includes two feedback loops for generating output signal components from the input signal. Each loop contains an oscillator, which has a frequency or phase which is variable in response to a control signal, and a comparator for generating the control signal. The oscillator generates a loop output signal which forms one of the components of the output signal. The apparatus also includes a combiner for combining the loop output signals to produce the output signal. For each loop, the apparatus also produces a feedback loop operating signal, these signals being dependent on the output signal and in phase quadrature with one another. One input of the comparator in each loop receives the feedback loop operating signal, and the other input of the comparator receives a component of the input signal.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: August 17, 1999
    Assignee: BTG International Limited
    Inventors: Andrew Bateman, Kam Yuen Chan
  • Patent number: 5905405
    Abstract: In a quadrature circuit, when a large frequency variation is detected, the carrier reproduction is conducted by using the carrier reproduction loop having a signal distortion but a small delay, and then, if the reproduced carrier becomes stable at some degree, the carrier reproduction is conducted by using the carrier reproduction loop having a less signal distortion but a large delay. When the number of the errors detected by an error detecting and correcting circuit is larger than a predetermined value, a selector supplies a digital in-phase signal and a digital quadrature signal outputted from A/D converters located before a waveform equalizer, to a carrier phase error detecting circuit which generates a digital phase error signal feedback through a D/A converter to a local carrier oscillator.
    Type: Grant
    Filed: August 11, 1997
    Date of Patent: May 18, 1999
    Assignee: NEC Corporation
    Inventor: Yoshiro Ishizawa
  • Patent number: 5896061
    Abstract: The invention pertains to a homodyne receiver, in particular for angle-modulated carrier signals in which the converted signal (ZF) has a d.c. voltage portion, and a process for correcting the converted receiving signal. Essentially three classes of errors occur with homodyne receivers: d.c. offset, amplitude difference and phase errors between the in-phase (I) and quadrature (Q) branches. Standard adjustments of the local oscillator with phase-locked loop (PLL) do not work in the case of weak signals. To use cost-effective, rapid analog/digital converters, particularly the d.c. offset has to be separated out. In so far as this has been done previously and the I and Q signal were corrected also, these corrections could be accomplished only with expensive components in the RF class. To avoid this the invention provides an arithmetic unit that is designed for converting into a circle the ellipse set by the distorted I and Q signals.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: April 20, 1999
    Assignee: Sican Gesellschaft Fur Silizium-Anwendungen Und Cad/Cat
    Inventor: Hermann Behrent
  • Patent number: 5881107
    Abstract: Transmission system with a transmitter (T), a receiver (R), and a filter combination (FI1, FI2; FQ1, FQ2) for transmitting a digital signal (sr), encoded in symbols (Si), from the transmitter (T) to the receiver (R) at any frequency position by quadrature modulation, wherein one of the two quadrature signal components (ki, kq) in the transmitter is delayed before the quadrature modulation by a time interval td, particularly by td=Tsymb/4. (FIG.
    Type: Grant
    Filed: March 11, 1997
    Date of Patent: March 9, 1999
    Assignee: Deutsche ITT Industries, GmbH
    Inventors: Miodrag Termerinac, Franz-Otto Witte
  • Patent number: 5861773
    Abstract: A method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference area, when the demodulator is wrongly adjusted.
    Type: Grant
    Filed: December 2, 1997
    Date of Patent: January 19, 1999
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jacques Meyer
  • Patent number: 5822366
    Abstract: The invention relates to a transceiver for generating complex I/Q-signals on a transmission frequency (f.sub.TX) and for receiving them on a reception frequency (f.sub.RX). The device comprises a first frequency synthesizer (41) for forming a first mixer signal (f.sub.LI) for the mixer (42) of the first branch that mixes the I-component of the received signal into a lower-frequency I-signal, and a second frequency synthesizer (411, 49, 46) for forming a second mixer signal (f.sub.LQ) for the mixer (421) of the second branch that mixes the Q-component of the received signal into a lower-frequency Q-signal. The device further comprises control means (45) first for directing the phase of the first (f.sub.LI) and the second (f.sub.LQ) mixer signals into the same phase in the mixing effects thereof and, thereafter, into a 90 degree mutual phase shift in the mixing effects thereof when receiving signals for bringing the lower-frequency I- and Q-signals into a 90 degree mutual phase shift.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: October 13, 1998
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Juha Rapeli
  • Patent number: 5815541
    Abstract: A digital PLL apparatus includes a synchronization integrating circuit, an angle calculating circuit, and a digital PLL circuit. The synchronization integrating circuit determines a symbol timing by obtaining the maximum amplitude point of a correlation level during reception of a preamble. The angle calculating circuit outputs a phase .theta.c by performing an angle calculation every symbol timing determined by the synchronization integrating circuit. The digital PLL circuit receives the phase .theta.c from the angle calculating circuit and operates a phase locked loop, thereby obtaining an output phase.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: September 29, 1998
    Assignee: NEC Corporation
    Inventor: Mikio Fukushi
  • Patent number: 5812546
    Abstract: The demodulator has a plurality of matched filters in parallel. Each matched filter has a different binary PN code, a plurality of sample holders, a plurality of multipliers, an adder, and a controller. The sample holders has a common input, a switch, a first capacitor, a first inverse amplifier with an output and an input connected to the common input through the switch and the capacitor, and a first feedback capacitor for feeding the output of the first inverse amplifier back to the input. Each multiplier has a first and second sub-multiplexers, one of sub-multiplexer selecting corresponding sample holder output and another sub-multiplexer selecting a reference voltage.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: September 22, 1998
    Assignees: Yozan, Inc., Kokusai Electric Co., Ltd.
    Inventors: Changming Zhou, Guoliang Shou, Xuping Zhou, Makoto Yamamoto, Kenzo Urabe, Sunao Takatori
  • Patent number: 5761251
    Abstract: A circuit arrangement capable of achieving both DC offset correction and automatic gain control for QAM demodulation. The QAM signal is digitized and then the positive signal samples are averaged and combined with the negative signal samples. The sum of these two averages is an indication of the DC offset while the difference of these two averages is an indication of the gain factor for automatic gain control. Common circuitry is then alternately used to process the DC offset and the gain factor for automatic gain control.
    Type: Grant
    Filed: November 8, 1995
    Date of Patent: June 2, 1998
    Assignee: Philips Electronics North America Corporation
    Inventor: Andrew Reid Wender
  • Patent number: 5748046
    Abstract: An arrangement for selectively controlling the response time of a type II phase locked loop (PLL), especially one which includes a phase detector and an amplifier of a feedback type of integrator within an IC, comprises a controllable filter stage coupled in cascade with the amplifier. The controllable filter stage includes a filter section and a switching arrangement for selectively bypassing the filter section in response to a mode -determining control signal. In the described embodiment, the PLL controls the frequency of a local oscillator of a tuner and the second filter section has an amplitude versus frequency response for increasing the response time of the PLL during a fine tuning mode so that a demodulator can continue to operate properly during the fine tuning mode.
    Type: Grant
    Filed: June 25, 1997
    Date of Patent: May 5, 1998
    Assignee: Thomson Consumer Electronics, Inc.
    Inventor: David Mark Badger
  • Patent number: 5745004
    Abstract: A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: April 28, 1998
    Assignee: Zenith Electronics Corporation
    Inventors: Victor Mycynek, Gary Sgrignoli
  • Patent number: 5729173
    Abstract: A quadrature amplitude modulation demodulator for receiving a quadrature amplitude modulated signal having a suppressed pilot signal. In the demodulator, a receiver unit converts received quadrature amplitude modulated signal into a frequency converted signal and a signal at a phase 90 degrees shifted from this frequency converted signal. A synchronous detector unit performs synchronous detection on the signals outputted by the receiver unit by detecting a frequency difference between a carrier of the frequency converted signal and a reference signal. Then, a phase detector unit performs phase detection on the synchronous detected signals by detecting a phase difference included in the synchronous detected signals. A detector unit detects transmitted data from the phase detected signal.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: March 17, 1998
    Assignee: Taisei Electric Incorporation
    Inventor: Yoichi Sato
  • Patent number: 5703526
    Abstract: A method for detecting a locked condition of a demodulator of at least one signal that may have discrete levels defining a constellation of nominal points in a plane. The method includes the steps of defining reference areas about the nominal points, a reference area being separated from another by a band or an angular sector crossing the origin of the constellation plane, and indicating a locked condition if the ratio of points occurring in the reference areas is above the probability for points to occur in the reference areas when the demodulator is wrongly adjusted.
    Type: Grant
    Filed: July 1, 1996
    Date of Patent: December 30, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jacques Meyer
  • Patent number: 5668498
    Abstract: A biphase stable FPLL includes a polarity determination circuit that ascertains the lockup phase of the FPLL based upon the polarity of the pilot in the digital signal. A frequency lock circuit also determines from the recovered pilot when frequency lock has occurred and the polarity determination circuit is responsive thereto for inverting the phase of the incoming, or alternatively, of the outgoing signal, as determined in order to supply an output signal of predetermined polarity.
    Type: Grant
    Filed: May 13, 1996
    Date of Patent: September 16, 1997
    Assignee: Zenith Electronics Corporation
    Inventor: Gary J. Sgrignoli
  • Patent number: 5656971
    Abstract: In a demodulation device for demodulating a phase-modulated wave, a baseband signal producing circuit produces a baseband signal having particular information which is dependent on the phase-modulated wave. Responsive to the baseband signal, a phase information producing circuit produces a phase difference signal. A reception logic circuit detects the baseband signal to produce an alarm signal when the particular information is not detected from the baseband signal. In response to the alarm signal, a reset signal producing circuit produces a reset signal. With reference to presence and absence of the reset signal, a selector selects, as a control signal, one of the phase difference signal and a cancelling signal which is supplied to the selector. In accordance with the control signal, a wave producing circuit produces a reproduced and a phase-shifted carrier wave which are used to make the baseband signal producing circuit produce the baseband signal.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: August 12, 1997
    Assignee: NEC Corporation
    Inventor: Yuichi Gotoh
  • Patent number: 5652768
    Abstract: The demodulation of binary amplitude-modulated carrier signals gives rise to special problems, for example in the case of contactless data carriers, because the RF signal is then also used for generating the operating voltage which is limited to a fixed value when the energy is sufficiently high. Moreover, strong interference signals are often superposed on amplitude-modulated signals. For reliable demodulation in such circumstances, therefore, a control signal is subtracted from the input signal and the values of one polarity of the difference are integrated. In order to generate the control signal, the values of one polarity of a further difference between the input signal and a further control signal which is proportional to the former control signal are continuously integrated so as to form an integral signal which is periodically reduced by a fixed fraction. The control signals are derived from said integral signal in a non-linear fashion, preferably by way of the input characteristic of a transistor.
    Type: Grant
    Filed: September 1, 1995
    Date of Patent: July 29, 1997
    Assignee: U.S. Philips Corporation
    Inventors: Siegfried Ritter, Wolfgang Tobergte
  • Patent number: 5652769
    Abstract: A costas loop includes a comparator, and a BPSK-modulated signal which is converted into a binary signal by the comparator is latched by a D-FF according to an oscillation signal from a VCO. An output of the D-FF becomes a demodulated signal. On the other hand, a phase-difference between the BPSK-modulated signal and the oscillation signal is detected by a phase-comparator, and the phase-difference is applied to the VCO via a loop filter. An oscillation frequency of the VCO is thus controlled according to a phase-comparison result.
    Type: Grant
    Filed: October 31, 1995
    Date of Patent: July 29, 1997
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Tatsuo Hiramatsu
  • Patent number: 5640425
    Abstract: A system and method using a Costas loop to effect accelerated convergence with minimal system complexity. The system comprises an in-phase-limiter and a quadrature-phase limiter, operatively coupled to an EXCLUSIVE-OR gate, for exclusively-ORing an in-phase-sign signal and a quadrature-phase-sign signal to output a first error signal, responsive to the signals having same signs, or a second error signal, responsive to the signals having different signs. An AGC circuit, operatively coupled to an output of the EXCLUSIVE-OR gate, increases and decreases a voltage level of an AGC signal responsive to two consecutive first or second error signals and consecutive dissimilar error signals, respectively. A voltage-controlled oscillator, operatively coupled to an output of the AGC circuit and responsive to the increased or decreased voltage level, changes the frequency of a voltage-controlled-oscillator output signal.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: June 17, 1997
    Assignee: Golden Bridge Technology, Inc.
    Inventor: Emmanuel Kanterakis
  • Patent number: 5640125
    Abstract: For demodulating a phase-modulated signal having 2M states of a carrier (M being an integer), the signal is converted into two baseband signals in quadrature. For that, they are multiplied by a signal delivered by a local oscillator at a transposed carrier frequency. Then the baseband signals are digitized by sampling at the clock frequency of the modulating signal. The clock of the signal is recovered by adjusting the phase of a local clock, stabilized at a bit frequency. For that, a minimum value of the intersymbol interference is searched. The signal clock is recovered before the carrier is recovered. Devices for implementing the method are also disclosed.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: June 17, 1997
    Assignee: Matra Communication
    Inventor: Michel Alard
  • Patent number: 5627861
    Abstract: A carrier phase estimation apparatus include a base band converter and a phase estimator. A received IF signal is converted to an in-phase component In and an quadrature component Qn of a digital base band signal in the base band converter. In the phase estimator, a non-linear circuit executes a non-linear operation of the components In and Qn to output non-linearly converted in-phase component In' and quadrature component Qn' of the digital base band signal and the components In' and Qn' are input to a pair of filters. In each filter, the components In' or Qn' are stored into shift registers at a predetermined timing and the signals stored in the shift registers are multiplied by respective weighting factors C.sub.k in respective multipliers. The multiplied values are summed by an adder and the obtained sum is divided by a stage number N of the shift register in a divider to obtain filtering signals Xn and Yn.
    Type: Grant
    Filed: October 17, 1995
    Date of Patent: May 6, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Nobuhisa Kataoka
  • Patent number: 5614861
    Abstract: A phase modulated signal demodulation system which is not affected by noise and distortion of an input signal. The system includes a carrier reproduction PLL circuit for generating a reproduction reference clock having a frequency which is N times of a carrier frequency which is synchronized with an N-phase phase modulated input signal, and a clock generation circuit for dividing the reproduction reference clock by 1/N and for generating N clocks, each of which has a different phase offset by 360.degree./N. The system further includes a phase detector which detects a phase of the N-phase phase modulated signal by using the N clocks together with the input N-phase phase modulated signal; and an operating circuit which detects a data edge of the input signal and the reproduction reference clock.
    Type: Grant
    Filed: September 12, 1995
    Date of Patent: March 25, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroyuki Harada
  • Patent number: 5612975
    Abstract: A digital receiver includes a tuner and a demodulator that obtains a modulated signal carried in a received analog signal. A digital-to-analog converter operates at a preselected fixed sampling rate on the modulated signal to produce a first sequence of digitized samples. The first sequence of digitized samples is processed by a digital rotator to frequency-and phase-correct the first sequence of digitized samples. A controllable digital filter processes the first sequence to produce a filter output including a second sequence of digitized samples at a symbol rate. The second sequence is processed to ascertain a symbol rate of the modulated signal. The controllable filter coefficients are automatically varied to accommodate changes in the symbol rate of the modulated signal, so that the sampling rate of the digital-to-analog converter need not change.
    Type: Grant
    Filed: June 16, 1994
    Date of Patent: March 18, 1997
    Assignee: TV/COM Technologies, Inc.
    Inventors: Donald W. Becker, Thomas R. Bilotta
  • Patent number: 5610948
    Abstract: A demodulation apparatus of digital detection processing type of the invention offers versatility as consumer equipment in mobile communications, ATV, satellite broadcasting, CATV, and the like. A modulated wave output is obtained by multiplying an input digitally modulated wave signal by a local oscillating signal from a local oscillator. The obtained modulated wave output has a center frequency which is substantially equal to the symbol frequency. The modulated wave output is A/D converted at a rate which is four times as high as the symbol frequency, so as to be output as interleaved I and Q digital data. The I and Q data is split, and the split I and Q data are multiplied by coefficients of "+1" and "-1", respectively. The multiplied two output signals are selectively output. Thus, the data multiplied by the coefficients of "+1" and "-1" are alternately output for the I and Q signals, so as to perform the digital detection.
    Type: Grant
    Filed: May 23, 1995
    Date of Patent: March 11, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kunio Ninomiya, Seiji Sakashita
  • Patent number: 5596606
    Abstract: A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: January 21, 1997
    Assignee: Scientific-Atlanta, Inc.
    Inventor: Leo Montreuil
  • Patent number: 5528195
    Abstract: A quadrature demodulator for demodulating an input signal which includes respective data signals modulating in-phase and quadrature carriers. The demodulator includes a voltage controlled oscillator responsive to a control signal for generating an oscillatory signal. A demodulator, coupled to receive the oscillatory signal from the voltage controlled oscillator and the input signal, provides the in-phase and quadrature components of the input signal. Phase comparison circuitry, responsive to the in-phase and quadrature components of the input signal generates a phase error signal. The phase error signal represents the difference, in phase and magnitude, between a vector defined by the in-phase and quadrature components of the input signal and reference vectors. Filter circuitry, responsive to the phase error signal, generates a control signal for the voltage controlled oscillator.
    Type: Grant
    Filed: May 9, 1995
    Date of Patent: June 18, 1996
    Assignee: Panasonic Technologies, Inc.
    Inventors: Cheng-Youn Lu, Robert S. Burroughs
  • Patent number: 5500878
    Abstract: An automatic frequency control apparatus includes a local oscillator, a quadrature detector, a frequency offset value estimation circuit, a demodulation circuit, a synchronization determination circuit, a memory, and an AFC circuit. The synchronization determination circuit determines reception synchronization on the basis of demodulated signals from the demodulation circuit to output a synchronization determination signal to the AFC circuit when reception synchronization is established and outputs the value to the AFC circuit. The apparatus also includes a power-on state detection circuit for outputting a detection signal to the AFC circuit. The AFC circuit determines the oscillation frequency of the local oscillator on the basis of the outputs from the above components. An automatic frequency control method is also disclosed.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: March 19, 1996
    Assignee: NEC Corporation
    Inventor: Motoya Iwasaki
  • Patent number: 5490176
    Abstract: In a method of detecting false-locking the trains of clock signals corresponding to the two phase offset initially modulated trains of signals, the phase offset between said trains of clock signals is monitored, and false-locking is detected when the phase offset changes signal. Also, a method of demodulation implements this method of detecting false-locking. Also, a device for implementing the method of detecting false-locking contains a flip-flop in series with a monostable.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: February 6, 1996
    Assignee: Societe Anonyme Dite: Alcatel Telspace
    Inventor: Jacques Peltier
  • Patent number: 5477199
    Abstract: A synchronous detector for demodulating and decoding a digital data signal modulated either according to a vestigial sideband or a quadrature amplitude modulation scheme is based upon the principle of recognizing that a vestigial sideband signal may be regarded and treated as an offset-keyed QAM signal. The detector comprises a tuner for tuning to a center frequency symmetrically displaced within the transmitted digital data signal frequency spectrum and a decoder circuit selectively operating to reconstruct the transmitted digital data stream according to the duration of a transmitted data symbol. A related method of demodulating and decoding a modulated digital data stream comprises analogous steps of tuning to a center carrier frequency and selectively switching between in phase and quadrature arms of the demodulator such that the switch resides in one position or the other for a duration equal to half the duration of a transmitted data symbol.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: December 19, 1995
    Assignee: Scientific-Atlanta, Inc.
    Inventor: Leo Montreuil
  • Patent number: 5440267
    Abstract: In a demodulator, a delay detection means receives a .pi./4-shift QPSK signal and performs delay detection of a signal at an interval of symbols. An averaging circuit respectively averages two channel quadrature signal components of a signal. A preamble detection means detects a preamble having a specific pattern in which a phase shift of .pi./4 of the phase of a received symbol from the immediately preceding symbol and a phase shift of -3.pi./4 of a phase of a next symbol from the immediately preceding symbol are alternately repeated on a phase plane of the two channel quadrature signal components. A phase angle calculating means calculates the phase angle of an output signal from the averaging circuit. A frequency offset estimating circuit calculates a carrier frequency offset. A voltage-controlled oscillator has an output oscillation frequency variably controlled by an output signal from the frequency offset estimating circuit.
    Type: Grant
    Filed: September 14, 1994
    Date of Patent: August 8, 1995
    Assignee: NEC Corporation
    Inventors: Hiroki Tsuda, Motoya Iwasaki
  • Patent number: 5440268
    Abstract: AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is v
    Type: Grant
    Filed: September 16, 1994
    Date of Patent: August 8, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Taga, Tatsuya Ishikawa, Susumu Komatsu
  • Patent number: 5400363
    Abstract: A system for processing inphase and quadrature data channels, such as a Costas loop QPSK demodulator, employs an additional feedback loop for adjustment of phase offset between carrier reference signals, this loop being in addition to the Costas error loop for control of frequency and phase of an oscillator which provides the regenerated carrier signal. The additional loop employs cross-channel products of demodulated inphase and quadrature data signals as does the Costas loop. The regenerated carrier is applied via an adjustable phase-offset unit to provide quadrature carrier reference signals to phase detectors of inphase and quadrature data channels. The phase offset unit includes a 90 degree hybrid circuit energized by the carrier signal at a main input port plus an adjustable fraction of the carrier power applied to an auxiliary input port.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: March 21, 1995
    Assignee: Loral Aerospace Corp.
    Inventors: Geoffrey S. Waugh, Gary L. Wagner, Michael E. Jacobson
  • Patent number: 5398002
    Abstract: A method and apparatus for digitally demodulating a phase or frequency modulated signal using a quadrature mixing circuit to mix the phase or frequency modulated signal with a frequency equal to the carrier frequency of the received modulated signal to produce in-phase component signal (I) and a quadrature component signal (Q) of the received phase or frequency modulated signal which differ in phase by 90 degrees. The I and Q signals are provided via respective low pass filters to a phase to digital converter for generating a digital output signal. The digital output signal is provided to an interface circuit which generates a plurality of phase-change information signals which are provided to a signal processing circuit. The signal processing circuit uses interpolation circuitry to produce a demodulated signal. A further output of the signal processing circuit, i.e. a D.C. signal, is fed back to provide automatic frequency control to an oscillator in the quadrature mixing circuit.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: March 14, 1995
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Sa-Hyun Bang