Abstract: A demodulation apparatus of digital detection processing type of the invention offers versatility as consumer equipment in mobile communications, ATV, satellite broadcasting, CATV, and the like. A modulated wave output is obtained by multiplying an input digitally modulated wave signal by a local oscillating signal from a local oscillator. The obtained modulated wave output has a center frequency which is substantially equal to the symbol frequency. The modulated wave output is A/D converted at a rate which is four times as high as the symbol frequency, so as to be output as interleaved I and Q digital data. The I and Q data is split, and the split I and Q data are multiplied by coefficients of "+1" and "-1", respectively. The multiplied two output signals are selectively output. Thus, the data multiplied by the coefficients of "+1" and "-1" are alternately output for the I and Q signals, so as to perform the digital detection.

Abstract: A synchronous detector has first and second mixer circuits and a voltage controlled oscillator. The voltage controlled oscillator provides a local oscillator signal directly to the second mixer circuit and indirectly to the first mixer circuit through a phase transformer. The output of the first and second mixer circuits are combined in combiner circuitry to produce a jitter cancelled output signal. The jitter cancelled output signal is filtered in a loop filter and applied to the voltage controlled oscillator to control the frequency and phase of the local oscillator signal. The combiner circuitry includes a summer and a jitter cancellation filter. The jitter cancellation filter is preferably a high pass filter matched to spectrum of the signal detected. The output of the first mixer circuit is passed through the high pass filter into one input of the summer while the output of the second mixer circuit is passed to the second input of the summer. The output of the summer is passed to the loop filter.

Abstract: A quadrature demodulator for demodulating an input signal which includes respective data signals modulating in-phase and quadrature carriers. The demodulator includes a voltage controlled oscillator responsive to a control signal for generating an oscillatory signal. A demodulator, coupled to receive the oscillatory signal from the voltage controlled oscillator and the input signal, provides the in-phase and quadrature components of the input signal. Phase comparison circuitry, responsive to the in-phase and quadrature components of the input signal generates a phase error signal. The phase error signal represents the difference, in phase and magnitude, between a vector defined by the in-phase and quadrature components of the input signal and reference vectors. Filter circuitry, responsive to the phase error signal, generates a control signal for the voltage controlled oscillator.

Abstract: An automatic frequency control apparatus includes a local oscillator, a quadrature detector, a frequency offset value estimation circuit, a demodulation circuit, a synchronization determination circuit, a memory, and an AFC circuit. The synchronization determination circuit determines reception synchronization on the basis of demodulated signals from the demodulation circuit to output a synchronization determination signal to the AFC circuit when reception synchronization is established and outputs the value to the AFC circuit. The apparatus also includes a power-on state detection circuit for outputting a detection signal to the AFC circuit. The AFC circuit determines the oscillation frequency of the local oscillator on the basis of the outputs from the above components. An automatic frequency control method is also disclosed.

Abstract: In a method of detecting false-locking the trains of clock signals corresponding to the two phase offset initially modulated trains of signals, the phase offset between said trains of clock signals is monitored, and false-locking is detected when the phase offset changes signal. Also, a method of demodulation implements this method of detecting false-locking. Also, a device for implementing the method of detecting false-locking contains a flip-flop in series with a monostable.

Abstract: A synchronous detector for demodulating and decoding a digital data signal modulated either according to a vestigial sideband or a quadrature amplitude modulation scheme is based upon the principle of recognizing that a vestigial sideband signal may be regarded and treated as an offset-keyed QAM signal. The detector comprises a tuner for tuning to a center frequency symmetrically displaced within the transmitted digital data signal frequency spectrum and a decoder circuit selectively operating to reconstruct the transmitted digital data stream according to the duration of a transmitted data symbol. A related method of demodulating and decoding a modulated digital data stream comprises analogous steps of tuning to a center carrier frequency and selectively switching between in phase and quadrature arms of the demodulator such that the switch resides in one position or the other for a duration equal to half the duration of a transmitted data symbol.

Abstract: AFC circuit for QPSK demodulator including, a circuit for obtaining quadrature related detection signals by multiplying a modulated input signal with quadrature related local oscillation frequency signals from a quadrature phase local oscillator, digital converter for converting the detection signals into corresponding digital signals by sampling them with quadrature related clocks which have a frequency two times higher than a symbol rate of the input signal, frequency error detecter for detecting a frequency error between the quadrature related digital signals using a symbol timing sample value and a symbol intermediate timing sample value in the converted digital signals, first validity determinator for determining whether the frequency error signal is valid or not through a detection of the pattern of the modulated input signal from sample values before and after the symbol timing so as to result a first validity signal, second validity determinator for deetermining whether the frequency error signal is v

Abstract: In a demodulator, a delay detection means receives a .pi./4-shift QPSK signal and performs delay detection of a signal at an interval of symbols. An averaging circuit respectively averages two channel quadrature signal components of a signal. A preamble detection means detects a preamble having a specific pattern in which a phase shift of .pi./4 of the phase of a received symbol from the immediately preceding symbol and a phase shift of -3.pi./4 of a phase of a next symbol from the immediately preceding symbol are alternately repeated on a phase plane of the two channel quadrature signal components. A phase angle calculating means calculates the phase angle of an output signal from the averaging circuit. A frequency offset estimating circuit calculates a carrier frequency offset. A voltage-controlled oscillator has an output oscillation frequency variably controlled by an output signal from the frequency offset estimating circuit.

Abstract: A system for processing inphase and quadrature data channels, such as a Costas loop QPSK demodulator, employs an additional feedback loop for adjustment of phase offset between carrier reference signals, this loop being in addition to the Costas error loop for control of frequency and phase of an oscillator which provides the regenerated carrier signal. The additional loop employs cross-channel products of demodulated inphase and quadrature data signals as does the Costas loop. The regenerated carrier is applied via an adjustable phase-offset unit to provide quadrature carrier reference signals to phase detectors of inphase and quadrature data channels. The phase offset unit includes a 90 degree hybrid circuit energized by the carrier signal at a main input port plus an adjustable fraction of the carrier power applied to an auxiliary input port.

Abstract: A method and apparatus for digitally demodulating a phase or frequency modulated signal using a quadrature mixing circuit to mix the phase or frequency modulated signal with a frequency equal to the carrier frequency of the received modulated signal to produce in-phase component signal (I) and a quadrature component signal (Q) of the received phase or frequency modulated signal which differ in phase by 90 degrees. The I and Q signals are provided via respective low pass filters to a phase to digital converter for generating a digital output signal. The digital output signal is provided to an interface circuit which generates a plurality of phase-change information signals which are provided to a signal processing circuit. The signal processing circuit uses interpolation circuitry to produce a demodulated signal. A further output of the signal processing circuit, i.e. a D.C. signal, is fed back to provide automatic frequency control to an oscillator in the quadrature mixing circuit.

Abstract: An AFC method is used in a demodulator, which employs a 2.sup.n -phase phase shift keying modulation system, where n is an integer greater than or equal to two, to correct an error between a received carrier frequency and a local frequency. The AFC method includes the steps of (a) subjecting an intermediate frequency signal of a signal received by the demodulator to a quadrature wave detection to obtain I-axis and Q-axis signals, (b) converting amplitude information of the I-axis and Q-axis signals into phase information which includes frequency information, and (c) correcting the local frequency based on the frequency information included in the phase information.

Abstract: A method and apparatus for producing a frequency-controlled loop in a phase-diversity receiver for demodulating received ON-OFF-keyed (OOK) and phase shift keying (PSK) signals, by feeding a reference frequency signal and the received signals to a quadrature mixer (QM) which produces two output signals in phase quadrature at nominally zero intermediate frequency. Quadrature continuous wave signals void of the modulation are produced from the phase quadrature output signals. A voltage proportional to the frequency of the quadrature continuous wave signals is generated and is utilized for controlling the frequency of the generated reference frequency signal.

Abstract: A BPSK demodulator having a compound phase locked loop, such as a Costas loop, is disclosed. An in-phase component, signal SI from a Costas loop demodulating section 10 is converted by a symmetrical binary-valued signal forming converting circuit 21 into binary-valued signals, while a quadrature signal component SQ from the demodulating section 10 is also converted by a non-symmetrical binary-valued signal forming converting circuit 22 into binary-valued signals. The outputs of the circuits 21, 22 are supplied to a flip-flop 23 as its data input and its clock input, respectively. An output of flip-flop 23 is integrated by an integrating circuit 25. A CPU 28 decides whether or not an integrated value from integrating circuit 25 exceeds a predetermined threshold value TH to decide whether or not the Costas loop demodulating section 10 is in the locked state. In this manner, the locked state can be detected by a simplified constitution, while a pseudo-locked state may also be detected.

Abstract: A circuit for regenerating a carrier, through coherent detection and demodulation of a quadrature modulated wave, is controlled by an improved AFC control to prevent possible false pull-in. The carrier regeneration circuit includes detector 1, a first multi-level code discriminator 2, a phase deviation detection circuit 3 and a voltage control oscillator 5.

Abstract: The present invention concerns a method and a system for demodulating mutually interfering signals according to a suitable synchronism bond between said signals. With such a system a complete decoupling of the demodulators of said signals is obtained. The system is characterized in that on each polarization there is at least a pair of demodulators, a first pair operate a baseband conversion of both signal H and V using the carrier recovery circuit driven by data of one of the two signals (e.g. V) and a second pair operate still a baseband conversion of both signals H and V but using said carrier recovery circuit now driven by data of the other signal (e.g. H).

Abstract: A data communication receiver (100) includes a first antenna feed (106) coupled to a first receiver element (110) for demodulating (502) a radio signal containing data bits and for deriving a first phase-locked loop error signal. The data communication receiver (100) also includes a second antenna feed (108) coupled to a second receiver element (112) for demodulating (502) the radio signal and for deriving a second phase-locked loop error signal. A received signal strength indicator (134, 144) measures signal strength of the radio signal from the first antenna feed (106) during reception of a data bit, and concurrently measures signal strength from the second antenna feed (108). A processor (146) then defines (506, 508, 512) the data bit as received from the antenna feed (106, 108) having the greater signal strength to be the optimum data bit.

Abstract: A phase-error detecting circuit for detecting a phase error of an output signal of the VCO in a QDPSK demodulating circuit in accordance with the Costas loop method is disclosed. The phase-error detecting circuit comprises a first circuit which generates a first product (P.times.Q) of a first demodulated signal (P) and a second demodulated signal (Q) of a QPSK signal. A second circuit generates the difference of the squares (P.sup.2 -Q.sup.2) of the first and second demodulated signals. A third circuit receives both the first product (P.multidot.Q) generated by the first circuit and the difference (P.sup.2 -Q.sup.2) generated by the second circuit and generates the product of the first product (P.multidot.Q) and the difference (P.sup.2 -Q.sup.2). The first circuit includes a first quadratic multiplier for generating the first product. The second circuit includes second and third quadratic multipliers, a phase-reversing mechanism for reversing the phase of the signal (Q), and an adding mechanism.

Abstract: A non-coherent demodulator 1 multiplies a modulated intermediate frequency (IF) signal with a signal from a local oscillator 2 to produce a first pseudo baseband signal having frequency error. The first pseudo baseband signal is supplied to a wide band PLL type demodulator 15. A low-pass filter 26 removes noise component from a first control signal from a loop filter 19 in the wide band PLL type demodulator 15 to produce a second control signal. Multipliers 24 and 25 multiply the first pseudo baseband signal with an output of a voltage-controlled oscillator 27 controlled by the second control signal to produce a second pseudo baseband signal having smaller frequency error. The second pseudo baseband signal is supplied to a narrow band demodulator 14 and converted into a baseband signal.

Abstract: For processing a multiplied signal into a modified signal in a demodulator circuit, an adder (34) sums up a first, a second, and a third processed signal into a sum signal for use as the modified signal. A first processing circuit (31) processes the multiplied signal into the first processed signal. A second processing circuit (32) processes the multiplied signal into the second processed signal in accordance with a conjugate complex clock and a complex local signal. A third signal processing circuit (33) processes the multiplied signal into the third processed signal in accordance with a complex clock and a conjugate complex local signal. The complex clock signal represents a first complex number. The complex local signal represents a second complex number. The conjugate complex clock signal represents a complex conjugate of the first complex number. The conjugate complex local signal represents a complex conjugate of the second complex number.

Abstract: In order to coherently demodulate an incoming multi-phase PSK analog signal irrespective of large frequency deviation, an automatic frequency feedback loop is provided. An analog baseband signal is generated by multiplying the IF analog signal by a local signal and then is converted into the corresponding digital baseband signal. A multiplier multiplies the digital baseband signal by another local signal. The output of the multiplier is further multiplied and then applied to a plurality of single-tuned filters which are arranged in parallel and have tuning frequencies each different from an adjacent frequency by a predetermined frequency interval. Each of the plurality of single-tuned filters generates a signal for use in carrier recovery, a frequency error signal and a correlation coefficient. Subsequently, one of the plurality of single-tuned filters is selected in a manner wherein the maximum value is detected among the correlation coefficients.

Abstract: A receiving circuit is designed for an MSK (Minimum Shift Keying) receiver and a QPSK (Quadrature Phase Shift Keying) receiver. The circuit provides a synchronous state determining device and a control voltage sweeping device for sweeping the output of a voltage oscillator. In the asynchronous state, a switch is turned off for interrupting a reproducing phase error signal so that the output of the voltage oscillator may be swept for causing the synchronous state. Then, the sweeping operation is stopped and the switch is turned on for controlling the voltage of the voltage controlled oscillator so that the low-frequency error component is removed from the phase error signal of the demodulating circuit. This results in implementing the simply-arranged demodulating circuit which keeps the proper demodulating performance against the shifted carrier frequency without any degrade and demodulates the input signal stably if the signal has a low C/N ratio.

Abstract: A method and apparatus are described for demodulating a modulated signal having a carrier component and a data component, in which the modulated signal is split into at least two parts one of which is delayed with respect to the other, and the two parts are multiply-coupled and linearly-combined to produce a combined output corresponding to a function of the data component independent of the carrier component frequency. In the described method and apparatus the undelayed part is coupled with the delayed part in a multiport coupler, wherein the parts are relatively phase-shifted to produce a plurality of phase-shifted signals; and the phase-shifted signals are linearly combined such that the data component, in the function of the combined output, is not affected by variations in frequency or phase of the carrier component. This enables a robust direct-detection DPSK receiver.

Abstract: A circuit array for frequency translation by means of quadrature heterodyne signals has very low quadrature errors even at very high frequencies and is monolithically integratable with little external circuitry. The circuit array includes a first mixer which receives a first portion of an input signal, a second mixer which receives a second portion of the input signal, and a heterodyne signal generator which receives a local oscillator signal and supplies quadrature heterodyne signals to the mixers. The heterodyne signal generator includes a control loop to ensure a 90.degree. phase shift between the quadrature heterodyne signals. The circuit array can be used in a modulator for a transmitter or in a demodulator for a receiver.

Abstract: A microwave demodulator for a digital radio link using QAM type modulation, comprising on one path, a first circuit for compensating quadrature error and, on the other path, a second circuit for compensating the delay and temperature variations of the first circuit. The invention is particularly applicable to digital radio beams.

Abstract: An angular modulated signal is quadrature demodulated (37) into first and second signal vectors by a local carrier signal (36) having a frequency difference from a received carrier signal which is angular modulated by a modulating signal comprising symbols representative of binary one and zero at a symbol interval. In the modulating signal, a particular symbol sequence comprises the symbols in a predetermined manner and results in the first signal vector. A data symbol sequence comprises the symbols to represent data and results in the second signal vector. The first signal vector has inphase and quadrature phase amplitudes which are converted (41) to phase values substantially at the symbol interval. An individual error is provided by comparing (44) a phase variation between two phase values (42-43) with a reference variation (45) determined by the predetermined manner. Such individual errors are averaged (46) into a phase error (47) which is used in correcting (39) the second signal vector.

Abstract: A receiver for tracking a carrier suppressed phase-shifted input signal comprises a phase-locked loop circuit for receiving the input signal and having a variable frequency oscillator responsive to a control signal for oscillating at a frequency corresponding to an intermediate frequency and a frequency difference detector for producing an output signal indicative of the frequency difference between the frequency of the input signal and the intermediate frequency, a feedback loop network having a narrow-band path and a wide-band path and being responsive to the detector output signal for producing the control signal and applying the control signal to the oscillator through one of the paths whereby to change the intermediate frequency of the oscillator in response to the control signal, a quality detector responsive to the detector output signal for producing a signal corresponding to the bit error rate of the input signal; and selection means responsive to the bit error rate signal for causing the control sig

Abstract: A digital demodulator or receiver (22) having an interface (24) for receiving an input signal modulated with digital data, a multiplier (26) for multiplying the input signal with a local oscillator signal (LOa-LOd) to generate a product signal, and an integrator (38) for periodically integrating the product signal to generate a sequence of integrated signals, each having an amplitude indicative of a respective portion of the digital data, operates in a SEARCH mode to supply acquisition reference signals (1xi, 1xq, 2xi, 2xq) to the multipliers (36). The resulting integrated values (Ia-Id) are proportional to the sine and cosine of the pahse (.phi.) of the input signal. The polarities (Sa-Sd) of these integrated values (Ia-Id) are processed to estimate this phase (.phi.) and to generate a reset signal (RESYNC) for the receiver (22) at the appropriate time.

Abstract: Method for receiving carrier oscillations modulated with a useful signal. For a universal transmitting/receiving device, a method for the automatic adaptation of its modem to the type of modulation of the incoming signal is provided in which the incoming DPSK signal is first demodulated. The demodulator output signal is then converted into a polar co-ordinate representation and, after formation of the difference phase angle (.DELTA..phi.), its value frequency (H) is represented modulo 90.degree. in a histogram which can be evaluated for derivation of the control information.

Abstract: Apparatus is provided for locking onto a severe doppler shifted data modulated carrier signal. A phase lock loop of the type having a data detection branch, a carrier tracking branch and a voltage controlled oscillator branch is modified to provide a summing circuit at the input of the voltage control oscillator in the voltage controlled oscillator branch. A sweep control circuit is connected to the input of the summing circuit for sweeping the voltage controlled oscillator through a range of frequencies which encompass the doppler shifted carrier frequency. An automatic frequency control circuit is connected to the input of the summing circuit for automatically disconnecting the sweep control circuit from the summing circuit when the frequency of the voltage controlled oscillator reaches a predetermined value defining a window which encompasses only the center frequency of the doppler shifted carrier frequency.

Abstract: A method of demodulating a quadrature modulated signal includes first receiving the signal. The rf signal is then quadrature demodulated to produce in-phase and quadrature signals. One of these signals is filtered to produce a correction signal which is used for phase and amplitude correction. Both of the demodulated signals are again quadrature demodulated to produce the output signals. The second demodulation can be accomplished utilizing a correlation decoder. The applied correlation pulse includes a subcarrier component.

Abstract: The present invention describes a phase shift key receiver or demodulator having an A.C. couple base band automatic gain control. A pair of detectors for the automatic gain control are A.C. coupled to the output of a pair of linear analog multipliers for the purpose of eliminating DC offset signals and for minimizing thermal noise at the input of the automatic gain control circuit. The outputs of the pair of detectors connected in the data detecting branch and the carrier tracking branch of the PLL are connected to a input of the summing circuit whose output is connected to the automatic gain control loop filter. The output of the filter supplies the scaling signal employed as the scaling input to the linear analog multipliers.

Abstract: A digital modem is provided for demodulation of differential phase-shift keyed (DPSK) signals in a land mobile satellite receiver. The DPSK demodulator comprises a coarse frequency and lock detect module for identifying and estimating the frequency of the input signal, a numerically controlled oscillator (NCO) for generating in-phase and quadrature signals from the input signal, one pair each of delayed and non-delayed integrate and dump (I&D) modules, a symbol timing module for achieving symbol synchronization by determining the dump time of the I&D modules, a dot product detector for receiving the output of the non-delayed I&D modules and providing a detected data output, and an AFC loop comprising a cross product detector and an AFC loop filter that provides feedback to the NCO and lock detect module. The DPSK demodulator achieves symbol synchronization independent of carrier phase or frequency and at low signal-to-noise ratios.

Abstract: A PSK demodulator uses a sweep controller to broaden a range in which synchronism may be captured. The invention uses a decision circuit jointly based on a received PSK signal and a recovered carrier wave for making a soft decision as to the correction required for synchronism. An error voltage is developed responsive to a phase error for causing the sweep controller to sweep when there is no synchronism and to remain fixed when there is synchronism. The resulting circuit eliminates false synchronism indications.