Abstract: A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts.

Abstract: A signal modulation device and a signal amplifier cooperative therewith. The signal modulation device includes a local oscillation signal source, a baseband signal source, a first NMOS transistor, and a second NMOS transistor, wherein the first and second NMOS transistors are coupled with the baseband signal source and form a circuit architecture of a Gilbert-cell based differential pair to be directly switched by a differential baseband signal, and a high-frequency signal from the local oscillation signal source is controlled by the baseband signal so as to generate an amplitude-modulation high-frequency signal at an output end. The single-stage signal power amplifier amplifies the amplitude-modulation signal from the preceding circuit so as to increase the magnitude of signals transmitted and simplify the preceding digital/analog signal conversion circuit in a conventional amplitude-modulation circuit.

Abstract: Disclosed is a device structure using an inverse-mode cascoded Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) beneficial in applications requiring radiation hardened circuitry. The device comprises a forward-mode common-emitter HBT cascoded with a common-base inverse-mode HBT, sharing a common sub-collector. An exemplary device was measured to have over 20 dB of current gain, and over 30 dB of power gain at 10 GHz, thus demonstrating the use of these circuits for high-frequency circuit applications. In addition, the radiation response and voltage limits were characterized and showed to have negligible performance effects in typical operating conditions. Due to the unique topology, the disclosed device has the benefit of being a more compact cascode design and the additional benefit of providing significantly improved radiation tolerance.

Abstract: An amplifier arrangement having a transistor arrangement comprising a first transistor (1) in common-emitter configuration and a second transistor (2) in common-base configuration. A switching device (7) couples, in a first mode of operation, the first transistor (1) to an input (3) of the amplifier arrangement and while the second transistor (2) forms a cascade stage. In a second mode of operation the second transistor (2) is coupled to the input (3). While high gain is achieved during the first mode, the second mode allows for high linearity without requiring inductive degeneration.

Abstract: A semiconductor device has an external wiring for GND formed over an underside surface of a wiring substrate. A plurality of via holes connecting to the external wiring for GND are formed to penetrate the wiring substrate. A first semiconductor chip of high power consumption, including HBTs, is mounted over a principal surface of the wiring substrate. The emitter bump electrode of the first semiconductor chip is connected in common with emitter electrodes of a plurality of HBTs formed in the first semiconductor chip. The emitter bump electrode is extended in a direction in which the HBTs line up. The first semiconductor chip is mounted over the wiring substrate so that a plurality of the via holes are connected with the emitter bump electrode. A second semiconductor chip lower in heat dissipation value than the first semiconductor chip is mounted over the first semiconductor chip.

Abstract: A memory cell for storing a charge that gives rise to a cell voltage representing a bit value, the memory cell being capable of having the cell voltage boosted to a boost value at a time following reading of the stored charge. The memory cell includes a first capacitor connected between a first node and ground. A second capacitor is connected between a second node and ground, and a first switch is connected between the first node and the second node. A second switch and a third capacitor are connected in series between the first node and the second node, with a terminal of the second switch being connected to the first node, the common connection node of the second switch and the third capacitor comprising a third node. A third switch is connected between the third node and ground. In operation, in a first storage phase the first and third switches are closed and the second switch is open.

Abstract: A resonance circuit comprising, for example, an inductor and a plurality of capacitors is provided as a load of a transistor. The capacitors are changed over by a switch. As the capacitors are changed over by the switch, a resonance frequency is changed according to the invention the frequency hopping of an input signal. To cancel ringing that occurs at the time of the switching action, a transistor which cancels gate feed through is added to the switch. An inductor is provided at the gate in order to suppress a gain reduction and an increase in noise factor in a high-frequency range. This provides a compact, wide-band amplifier which has low noise, a wide gain and low power consumption.

Abstract: In a power amplifier, a serial bus interface is provided for sending and receiving information to other devices, such as a baseband controller. The power amplifier includes several control pins that can be used as a serial interface, or alternately, with a direct pin control interface. The serial bus interface can be used with digital power control techniques that provide various advantages over conventional power amplifiers.

Abstract: A charged particle detector and method are disclosed providing for simultaneous detection and measurement of charged particles at one or more levels of particle flux in a measurement cycle. The detector provides multiple and independently selectable levels of integration and/or gain in a fully addressable readout manner.

Abstract: Active circuits with active loads linearized via distortion cancellation are described. In one design, an apparatus includes a first stage and a load stage. For an amplifier, the first stage amplifies an input signal and provides an output signal having a larger signal level. For a mixer, the first stage mixes an input signal with an LO signal and provides an output signal. The load stage provides an active load for the first stage and is linearized by canceling distortion generated by the active load. In one design, the load stage includes a first transistor that provides the active load and generates distortion due to its nonlinearity. The load stage further includes at least one transistor that generates a replica of the distortion from the first transistor. The distortion replica is used to cancel the distortion from the first transistor. The first stage may also be linearized with distortion cancellation.

Abstract: There is provided with an amplifier comprising: first and second power amplifiers; a first path configured to output first and second input signals to the first and second power amplifiers; a second path configured to divide a first input signal, output one of divided signals to the first power amplifier and output the other divided signal to the second power amplifier; a first path changeover unit configured to change over the first and second paths; a third path configured to output first and second power amplified signals from the first and second power amplifiers; a fourth path configured to combines a first power amplified signal through an impedance conversion unit from the first power amplifier and a second power amplified signal from the second power amplifier at a combining point and output a combined signal; and a second path changeover unit configured to changeover the third and fourth paths.

Abstract: An audio signal switch has a plurality of inputs and an output. Each input is arranged to be selectively connected to the output via a respective transmission chain, each transmission chain includes: a first bipolar transistor, of a first type, connected to the input; a second bipolar transistor, of a second type, complementary to said first configuration, connected to the output; and an intermediate bipolar transistor, of the second type, connected between said first and second transistors. The first and second transistors are arranged in an emitter-follower circuit configuration, and the intermediate transistor is arranged to act as a diode to protect the first transistor from a large reverse voltage applied to its base-emitter junction.

Abstract: An amplifier circuit includes an amplifier and a phase shifter coupled in parallel to the amplifier and switchable such that the phase shifter has a first impedance for an alternating signal in an on state and has a second impedance for the alternating signal in an off state. The second impedance is higher than the first impedance.

Abstract: An embodiment of the present invention provides an apparatus, comprising an integrated circuit, wherein a first portion of the integrated circuit is placed on a top tier substrate and a second portion of the integrated circuit is placed on a bottom tier substrate stacked adjacent the top tier substrate and wherein the first portion and the second portion of the integrated circuit are interconnected; and printed spiral arms stacked vertically on both the top and bottom surface of the top tier substrate thereby creating high Q inductors.

Abstract: An amplifying circuit and an associated linearity improving method are provided to correct the AM to PM distortion of an amplifier, thereby improving the amplifier linearity. The amplifying circuit includes an amplifier and a correcting unit. The amplifier has a non-linear input capacitor. The correcting unit generates a correction signal according to an input signal of the amplifier, and performs an AM to PM correction according to the correction signal, thereby making the amplifier have an approximately linear equivalent input capacitor.

Abstract: An amplifier comprises an input circuit that receives an input to the amplifier. A start-up circuit communicates with the input circuit, generates a start-up signal, and turns off the start-up signal when an output of the amplifier reaches a threshold voltage. The start-up circuit includes a first transistor having first and second terminals and a base terminal and a second transistor having first and second terminals and a base terminal. The base terminals of the first and second transistors receive a bias input, the first terminals of the first and second transistors communicate with each other and with a first current source, and the second terminals of the first and second transistors communicate with the input circuit.

Abstract: An arrangement of signal line pairs and amplifiers is disclosed. One embodiment provides each signal line pair of a group of signal line pairs that are directly adjacent and run parallel to one another is respectively assigned an amplifier from a group of amplifiers arranged successively in a signal line direction. Each signal line pair includes a first and a second signal line, between which the amplifier assigned to the respective signal line pair is arranged. The position of an amplifier is assigned to a specific signal line pair in the amplifier group along the signal line direction is chosen in such a way that a first coupling section which forms the first signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, and a second coupling section, which forms the second signal line assigned to the respective amplifier together with its adjacent lines along the amplifier group, substantially have the same coupling properties.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and tennination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be updated while signals (e.g, clock or data) are transmitted. Some embodiments identify elements in a high-impedance state by examining incoming signals.

Abstract: a circuit for an RFID device in one embodiment includes an operational amplifier having a first input, a second input, and an output where the first input receives an incoming signal, arid the second input is coupled to the output via a feedback loop. An operational amplifier for an RFID device according to another embodiment compares an output of the operational amplifier to an incoming baseband signal, A circuit according to another embodiment includes an operational amplifier having a first input, a second input, and an output, wherein the first input receives an incoming signal, and wherein the second input is coupled to the output via a feedback loop. A comparator having one input is coupled to the output of the operational amplifier, another input receiving the incoming signal, and an output for outputting an outgoing signal. Methods for adjusting a filtering characteristic of an operational amplifier are also disclosed.

Abstract: Disclosed herein is a high-power constant current Darlington circuit, including an input terminal in which the base terminal (B) (a first terminal) of the constant current Darlington circuit is connected to the base of a transistor (Q1), the emitter of the transistor (Q1) being connected to one end of a resistor (R1) and the base of a transistor (Q2), the other end of the resistor (R1) being connected to an emitter of the transistor (Q3), the collector terminal (C) (a second terminal) of the constant current Darlington circuit connected to the collector of the transistor (Q1) and the collector of the transistor (Q2), the emitter of the transistor (Q2) being connected to one end of a constant voltage source (CV1), the emitter terminal (E) (a third terminal) of the constant current Darlington circuit directly connected to a load (LD1), the other end of the constant voltage source (CV1) being connected to one end of a resistor (R2) and the base of the transistor (Q3), and the terminal (E1) (a fourth terminal) of

Abstract: An apparatus for automatically analyzing genetic and protein materials using photodiodes. The apparatus comprises a computer for controlling the entire operation of the apparatus and analyzing a voltage level from a characteristic detector to analyze states of the genetic and protein materials, and an address decoder connected to the computer. The photodiodes are connected to the address decoder and generate currents in response to external light being incident thereon. A plurality of amplifiers are connected respectively to the photodiodes to amplify output currents therefrom, and a plurality of voltage output circuits are connected respectively to the amplifiers to convert output currents therefrom into voltages. An output selector selects any one of output voltages from the voltage output circuits under the control of the computer. The characteristic detector measures a level of an output voltage from the output selector and applies the measured voltage level to the computer.

Abstract: Provided is a burst mode optical receiver considering a characteristic of an extinction ratio of a received optical signal is provided. By using a peak detector considering a characteristic of an extinction ratio, top and bottom peak voltages of actual burst packets can be precisely detected while not being affected by a DC offset corresponding to an extinction ratio even though burst packets having a DC offset corresponding to the extinction ratio are received. Accordingly, waveform distortion of a signal output from the burst mode optical receiver can be minimized.

Abstract: A device for bi-directional amplification of data signals over power lines is disclosed. In one embodiment, the device includes a bandpass filter, a frequency converter and an amplifier. The bandpass filter filters out undesired frequencies and the frequency converter converts the frequency band of the data signals to a different frequency band. The output of the filter is provided to the amplifier for amplifying the frequency converted data signals for transmission over power line.

Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.

Abstract: A collector boost circuit is disclosed for providing a first voltage in a first mode of operation to a power amplifier, and a second voltage in a second mode of operation to the power amplifier. The collector boost circuit uses a switch and an indicator signal for triggering the switch between the first and the second mode of operation. The second voltage is a boosted voltage greater than the first voltage and is provided during peak excursions through a boost capacitor.

Abstract: The present invention relates to an amplifier arrangement having a plurality of amplifier stages that form a series circuit. Each amplifier stage comprises a current mirror, the translation ratio of which defines the gain of the amplifier stage. Moreover, a current coupling-out element is provided in each amplifier stage, a partial current being output at said element, and the partial currents are added together in a summation element. An RSSI signal associated with the summed currents is provided at the output of the summation element. The RSSI amplifier arrangement provides constant and thermostable signal amplification, low sensitivity to overvoltages, and exhibits a low current requirement and good radio frequency properties.

Abstract: Methods and apparatus are provided for RF switches (504, 612) integrated in a monolithic RF transceiver IC (500) and switched gain amplifier (600). Multi-gate n-channel enhancement mode FETs (50, 112, 114, Q1-3, Q4-6) are used with single gate FETs (150), resistors (Rb, Rg, Re, R1-R17) and capacitors (C1-C3) formed by the same manufacturing process. The multiple gates (68) of the FETs (50, 112, 114, Q1-3, Q4-6) are parallel coupled, spaced-apart and serially arranged between source (72) and drain (76). When used in pairs (112, 114) to form a switch (504) for a transceiver (500) each FET has its source (74) coupled to an antenna RF I/O port (116, 501) and drains coupled respectively to second and third RF I/O ports (118, 120; 507, 521) leading to the receiver side (530) or transmitter side (532) of the transceiver (500). The gates (136, 138) are coupled to control ports (122, 124; 503, 505; 606, 608).

Abstract: A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.

Abstract: An electrical circuit includes an amplifier. The amplifier includes an input circuit in communication with an input of the amplifier. The amplifier includes a start-up circuit in communication with the input circuit. The start-up circuit is configured to generate a start-up signal to enable subsequent operation of the amplifier. Generation of the start-up signal by the start-up circuit can be ceased when the operation of the amplifier reaches a steady-state. The amplifier also includes an output circuit in communication with an output of the amplifier and in communication with the input circuit and the start-up circuit.

Abstract: A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage.

Abstract: A band gap circuit using NPN transistors (10, 12) having collectors connected to a power source voltage is employed, and transistor active regions of the NPN transistors (10, 12) and semiconductor elements constituting other signal processing circuits are integrated in the same floating block (19) with high voltage resistance. As a result, a reference voltage circuit used in the signal processing circuit can be integrated in a compact manner.

Abstract: There is disclosed, for use in an integrated circuit, an apparatus for driving a signal line in the integrated circuit. The apparatus comprises: 1) a line driver for receiving an incoming data signal and transmitting an outgoing data signal on the signal line; 2) a power source for supplying a plurality of power voltage levels to a power supply rail of the line driver; and 3) a power level controller for determining a data rate of the outgoing data signal and in response to the determination, selectively applying one of the plurality of power voltage levels to the power supply rail of the line driver to thereby modify an amplitude of the outgoing data signal.

Abstract: A column driver for a graphics display has reduced power consumption by sharing power between upper and lower column amplifiers. The upper column amplifier operates over an upper supply range, while the lower column amplifier operates over a lower supply range. The upper and lower amplifiers have the substantially the same quiescent operating current such that the total operating current for the column drivers in the graphics display is reduced by a factor of two. Each column amplifier can be driven over half of the power-supply range such that lower voltage amplifiers may be employed for the column driver amplifiers.

Abstract: A circuit for a power amplifier is disclosed which amplifies and outputs an audio signal by amplifying an input audio signal using first and second differential circuits, and driving a push-pull output transistor with the outputs from the first and second differential circuits. The circuit includes a signal generating part generating a disconnection timing signal for disconnecting a bias current reducing activation currents of the first and second differential circuits based on a switch control signal, and positive feedback loops of the first and second differential circuits. A switch part is disposed in each of the positive feedback loops of the first and second differential circuits, disconnecting the positive feedback loops in response to the disconnection timing signal. A bias part stops the operation of the first and second differential circuits by reducing the activation currents of the first and second differential circuits by reduction of the bias currents.

Abstract: An apparatus comprising a Darlington transistor pair and a common-base transistor. The Darlington transistor pair may be configured to generate an output signal in response to an input signal. The common-base transistor may (i) be coupled between an output transistor of the Darlington transistor pair and the output signal and (ii) have a base configured to receive a frequency dependent reference voltage.

Abstract: A preamplifier system is provided for use with a magneto-resistive (MR) sensor. Included is an alternating current (AC) coupling module connected to the MR sensor for blocking a direct current (DC) voltage associated with an input signal, and filtering low frequency noise associated with the input signal. Also provided is a gain stage module coupled to the AC coupling module. The gain stage module includes a plurality of cascode field effect transistors (FETs) configured for amplifying the input signal, while reducing intrinsic noise and increasing operational bandwidth. Coupled to the gain stage module is a control circuit for feeding back an output of the gain stage module for bias regulation and disturbance rejection.

Abstract: An apparatus comprising a Darlington transistor pair, a first common-base transistor and a second common-base transistor. The Darlington transistor pair may be configured to generate an output signal in response to an input signal. The first common-base transistor may be coupled between the Darlington transistor pair and the output signal. The second common-base transistor may also be coupled between the Darlington transistor pair and the output signal. The first and second common-base transistors may each have a base configured to receive a reference voltage.

Abstract: An equalizer circuit for equalizing first and second differential input signals comprises a differential pair, a reactive load, and first and second input followers. The differential pair defines first and second input nodes and first and second output nodes, and the reactive load is coupled to the differential pair. The first input follower circuit is connected to the first input node of the differential pair and is operable to receive the first differential input signal and to receive a first feedback signal from the differential pair and in response to generate a first input signal at the first input node of the differential pair. The second input follower circuit is connected to the second input node of the differential pair and is operable to receive the second differential input signal and to receive a second feedback signal from the differential pair and in response to generate a second input signal at the second input node of the differential pair.

Abstract: A microwave isolator including a driving circuit and a receiving circuit, wherein the driving circuit receives an input signal from a first isolated circuit and generates a corresponding radio frequency (RF) signal and the receiving circuit detects and decodes the corresponding RF signal and provides a corresponding output signal to a second isolated circuit. The driving circuit contains an oscillator for generating the corresponding RF signal based on the input signal from the first isolated circuit, a transmitting antenna for transmitting the corresponding RF signal, and a microwave switch interposed between the oscillation means and the transmitting antenna for switching the RF signal to the antenna. The receiving circuit contains a receiving antenna to receive the corresponding RF signal and means for detecting and decoding the received corresponding RF signal and providing the corresponding output signal to the second isolated circuit.

Abstract: A differential amplifier and a method for amplifying an input signal are disclosed. The differential amplifier comprises an amplification stage configured to amplify an input signal to produce an amplified output, a current source configured to provide a bias current for the amplification stage, and an impedance network connected to the amplification stage and the current source. The impedance network is configured to provide a high common mode impedance within the range of operating frequencies.

Abstract: The invention relates to an LDMOS transistor including a gate, source and drain, and an earth plane located under the gate, source and drain. According to the invention, the earth plane is given such an extent in the lateral direction of the transistor that an additional component of chip type can be mounted on it, whereby the LDMOS transistor and the additional component of chip type have a shared earth plane. The earth plane suitably comprises a silicon layer which is doped so that it has become conductive and can thereby constitute the earth plane for the transistor and the additional component of chip type.

Abstract: The present invention relates to a power transistor module for radio frequency applications, particularly for use in an amplifier stage in a radio base station or a ground transmitter for TV or radio, wherein said power transistor module comprises a support, a power transistor chip arranged thereon, outer electrical connections projecting from the module, and inner electrical connections connected between said transistor chip and said outer connections, where at least one of said outer electrical connections is comprised of a first conductor pattern arranged on a flexible foil. The invention further comprises a power amplifier comprising said power transistor module, a method for fabrication of a power amplifier, wherein said module is electrically connected to a circuit board mounted at a heat sink and is mounted at said heat sink, and finally a power amplifier manufactured according to the method.

Abstract: An optical signal power monitor and regulator comprises: a lasing semiconductor optical amplifier for receiving the optical signal and whose laser output is used to monitor a power level of the optical signal; a monitor circuit which receives the laser output and outputs a monitoring signal; a tunable element for receiving a version of the optical signal and whose level of amplification is adjustable and for outputting an amplified optical signal; and a regulator circuit for receiving the monitoring signal and adjusting the amplification of the tunable optical amplifier depending upon the monitoring signal. The tunable element may comprise a tunable gain-clamped semiconductor optical amplifier. Such an embodiment is capable of automatically regulating the tunable element such that a power level of the amplified optical signal is kept stable.

Abstract: A circuit configuration is configured such that selectively a first amplifier or a second amplifier amplifies signals. The second amplifier is operated depending on the conditions established at the input terminal of the first amplifier. A switching element has a controlled path connected to an input terminal of the second amplifier. The switching state of the switching element can be controlled by the input terminal of the first amplifier. As a result, it is possible to effect the changeover between the amplifiers with minimal outlay and without disturbing the amplifiers.

Abstract: In general, the invention is directed to an efficient amplifier for use in radio-frequency identification (RFID) applications. In particular, the invention provides a highly efficient amplifier that requires little power, yet has significant modulation bandwidth to achieve high data communication rates. The amplifier makes use of many components of a class E amplifier including a first transistor, an inductor coupling the first transistor to a power supply, and a shunt capacitor connected in parallel to the first transistor. A second transistor is connected in parallel to the first transistor. A controller selectively controls the first and second transistors to achieve amplitude modulation at a high modulation bandwidth.

Abstract: A data receiver that is capable of precisely detecting data at high speed even at a high frequency after receiving differential reference signals and data in synchronization with a clock signal, and a method for receiving data, are provided. The receiver includes an amplifier which compares differential reference signals with input data and outputs first differential reference signals based on the results of the comparison; and a folded differential voltage sensor which amplifies the difference between the first differential signals in synchronization with a clock signal and detects the input data.

Abstract: A PWM power amplifier having at least one PCM/PWM converter fed by PCM digital input signals and producing PWM digital output signals, and at least one power amplification final stage of the PWM digital output signals. At least one PCM/PWM converterincludes a counter fed with at least one clock signal produced by a clock generator device and having a digital comparator suitable for comparing the PCM digital input signals of at least one PCM/PWM converter with a digital comparison signal produced by the counter and producing in output the PWM digital signals. The clock generator device includes a pulse generator device and an oscillator; the pulse generator device receives a signal at a frequency that is equal to the frequency of the PCM digital input signals of the at least one PCM/PWM converter and produces in output reset pulses. The reset pulses are sent in input to the oscillator, which produces in output the at least one clock signal.

Abstract: A preamplifier having extremely high input impedance amplifies the electrical signal output from an electret condenser microphone (ECM) without suffering from the effects of a DC leakage current at the input. The preamplifier circuit includes a pair of cross-coupled PN junction diodes setting the input impedance, a PMOS device, and a load resistor configured similarly to a conventional preamplifier. A capacitor is placed between the input and the cross-coupled diodes such that a DC path no longer exists to bias the cross-coupled diodes. Therefore, leakage currents are prevented from upsetting the DC operating point of the preamplifier and biasing the cross-coupled diodes. Consequently, small signal gain distortion, excessive demodulation products and increased noise can be avoided.

Abstract: Systems and methods are described for long subscriber loops using modified load coils.

Abstract: An optical signal power monitor and regulator comprises: a lasing semiconductor optical amplifier for receiving the optical signal and whose laser output is used to monitor a power level of the optical signal; a monitor circuit which receives the laser output and outputs a monitoring signal; a tunable element for receiving a version of the optical signal and whose level of amplification is adjustable and for outputting an amplified optical signal; and a regulator circuit for receiving the monitoring signal and adjusting the amplification of the tunable optical amplifier depending upon the monitoring signal. The tunable element may comprise a tunable gain-clamped semiconductor optical amplifier. Such an embodiment is capable of automatically regulating the tunable element such that a power level of the amplified optical signal is kept stable.