Having Signal Feedback Means Patents (Class 330/260)
  • Patent number: 8552799
    Abstract: A power amplifying circuit includes first and second operational amplifiers. The power amplifying circuit includes first to fourth feedback resistor. The power amplifying circuit includes a fully differential operational amplifier that is connected to the output terminal of the first operational amplifier at a non-inverting input terminal thereof, to the output terminal of the second operational amplifier at an inverting input terminal thereof, to a first signal output terminal at a non-inverting output terminal thereof, and to a second signal output terminal at an inverting output terminal thereof and maintains a constant differential gain. The power amplifying circuit includes a switching circuit. The power amplifying circuit includes first and second input resistors. The power amplifying circuit includes a midpoint potential controlling circuit that monitors a power supply voltage and controls the switching circuit.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: October 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Tsurumi
  • Patent number: 8552801
    Abstract: Systems and methods for providing a fully differential amplifier performing common-mode voltage control having reduced area and power requirements are disclosed. The amplifier disclosed comprises an additional input stage at the amplifier input which senses the common mode voltage of the amplifier's inputs and applies internal feedback control to adjust the output common-mode voltage until the input common-mode voltage matches a target voltage and thereby indirectly set the output common-mode voltage. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: October 8, 2013
    Assignee: Dialog Semiconductor GmbH.
    Inventor: Andrew Myles
  • Publication number: 20130258148
    Abstract: An amplification circuit includes an amplifier, a first capacitor including a first terminal connected to an input terminal of the amplifier, a second capacitor including a first terminal connected to the input terminal of the amplifier and a second terminal connected to an output terminal of the amplifier, and a correction unit configured to correct a difference in bias dependency between capacitance values of the first and second capacitors.
    Type: Application
    Filed: March 22, 2013
    Publication date: October 3, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hideo Kobayashi, Masanori Ogura
  • Publication number: 20130257537
    Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Jean-Marc Mourant, Feng-Jung Huang, Ran Li, Chuying Mao
  • Publication number: 20130235487
    Abstract: Amplifier architectures are provided for current sensing applications. An amplifier includes a load device, an operational amplifier, a current source, and a bipolar transistor. The operational amplifier has a first input terminal connected to a first input node that receives an input current, and a second input terminal connected to a second input node that receives a reference voltage. The current source is connected to an output of the operational amplifier. The operational amplifier, the current source, and the bipolar transistor form a feedback loop that generates and maintains a bias voltage on the first input node based on the reference voltage applied to the second input node. The bipolar transistor amplifies the input current received on the first input node, and generates an amplified input current. The load device converts the amplified input current to an output voltage, wherein the output voltage is used to sense the input current.
    Type: Application
    Filed: November 12, 2012
    Publication date: September 12, 2013
    Applicant: LSI Corporation
    Inventors: Brad A. Natzke, Cameron C. Rabe, Hong Jiang, Andrew P. Krebs, Jason P. Brenden
  • Publication number: 20130217345
    Abstract: Apparatus and methods for envelope tracking systems are disclosed herein. In certain implementations, an envelope tracking system for generating a power amplifier supply voltage for a power amplifier is provided. The envelope tracking system includes a DC-to-DC converter that generates a regulated voltage from a battery voltage and controls a voltage of the regulated voltage using a low frequency feedback signal. The envelope tracking system further includes an error amplifier that generates an output current using an envelope signal and a high frequency feedback signal. The low frequency feedback signal is based on a low frequency component of the power amplifier supply voltage and the high frequency feedback signal is based on a high frequency component of the power amplifier supply voltage. The error amplifier generates the power amplifier supply voltage by adjusting the magnitude of the regulated voltage using the output current.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 22, 2013
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: SKYWORKS SOLUTIONS, INC.
  • Publication number: 20130214864
    Abstract: A signal amplifying circuit of a communication device is disclosed including: an amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the input terminal is coupled with a fixed voltage level; a feedback circuit coupled with the second input terminal and the output terminal of the amplifier; a digital-to-analog converter (DAC); a signal processing circuit; a switch for selectively coupling the second input terminal of the amplifier with the DAC or the signal processing circuit; and a control unit coupled with the switch for controlling the operations of the switch.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 22, 2013
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Realtek Semiconductor Corp.
  • Publication number: 20130214863
    Abstract: The present disclosure relates to a front-end system for a radio device, the front-end system comprising a low-noise amplifier (LNA), arranged for receiving a radio frequency input signal (RFIN) and arranged for outputting an amplified radio frequency signal (RFOUT), wherein the low-noise amplifier comprises a first differential amplifier, and a mixer (MIX), arranged for down-converting the amplified radio signal (RFOUT) provided by the low-noise amplifier (LNA) to a baseband signal (BB), by multiplying the amplified radio signal (RFOUT) with a local oscillator (LO) frequency tone, said low-noise amplifier (LNA) and said mixer (MIX) being inductively coupled.
    Type: Application
    Filed: February 15, 2013
    Publication date: August 22, 2013
    Applicant: IMEC
    Inventor: IMEC
  • Patent number: 8514021
    Abstract: Embodiments of the invention are concerned with configurable RFICs. In an exemplary embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between: an internal input impedance matching topology in which the respective low noise amplifier circuit includes one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, said one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; and a topology different from said internal input impedance matching topology.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 20, 2013
    Assignee: Renesas Mobile Corporation
    Inventors: Jari Johannes Heikkinen, Jonne Juhani Riekki, Jouni Kristian Kaukovuori
  • Publication number: 20130207723
    Abstract: Embodiments provide a gm-ratioed amplifier. The gm-ratioed amplifier comprises a first input voltage terminal and a second input voltage terminal, a first output voltage terminal and a second output voltage terminal, and an amplifying unit. The amplifying unit may be coupled between the input voltage terminals and the output voltage terminals and may be adapted to supply an output voltage to the output terminals in dependence on an input voltage supplied to the input terminals. The amplifying unit may comprise a gm-load, which comprises a first load branch comprising a first field effect transistor, and a second load branch comprising a second field effect transistor. A first source/drain terminal and a gate terminal of the first field effect transistor may be coupled to the first output voltage terminal, and a first source/drain terminal and a gate terminal of the second field effect transistor may be coupled to the second output voltage terminal.
    Type: Application
    Filed: March 24, 2010
    Publication date: August 15, 2013
    Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Zhiming Chen, Foo Chung Choong, Yuanjin Zheng
  • Publication number: 20130208393
    Abstract: A power amplifier circuit that has an inductor and capacitor connected to one end of the output winding of an RF transformer. The other end of the output winding is connected to a current sensor that in turn is connected to ground. The transformer has two primary windings. Both primary windings have one end connected to a voltage supply. The other end of each primary winding is attached to a switch. All three windings are wound around a core. Current flowing from the DC voltage supply to the switches causes a magnetic flux in the core. A voltage is generated on the secondary winding current sensor by the current that flows through the igniter. This voltage is fed back to the switches, controlling on and off timing. Voltage is provided to the igniter or pulled from the igniter when the current traveling into or from the igniter is at zero.
    Type: Application
    Filed: March 15, 2013
    Publication date: August 15, 2013
    Applicant: Federal-Mogul Ignition Company
    Inventor: Federal-Mogul Ignition Company
  • Publication number: 20130207722
    Abstract: Analog peaking amplifiers with enhanced peaking capability are provided. For example, a peaking amplifier circuit includes an input node, output node, a feedback node, a first input amplifier having an input connected to the input node and an output connected to the feedback node, a second input amplifier having an input connected to the input node, a coupling capacitor connected between an output of the second input amplifier and the feedback node, a forward-path gain amplifier having an input connected to the feedback node and an output connected to the output node, and a feedback circuit having an input coupled to the output node and an output connected to the feedback node. A peaking response of the peaking amplifier circuit is realized by capacitively coupling the output of the second input amplifier to the feedback node to suppress negative feedback and increase the peaking gain at higher frequencies.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: International Business Machines Corporation
    Inventors: John F. Bulzacchelli, Ping-Hsuan Hsieh
  • Patent number: 8509290
    Abstract: A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 13, 2013
    Assignee: Icera Canada ULC
    Inventors: Abdellatif Bellaouar, Tajinder Manku
  • Patent number: 8503967
    Abstract: An amplifier is arranged to receive an input signal and provide an output signal in response, and includes a main amplifier core and an auxiliary circuit. The main amplifier core includes an input node, an output node and a sum node with the input node coupled to the input signal, and is arranged to provide an interior signal to the sum node and output the output signal at the output node in response to signals provided to the sum node. The auxiliary circuit is coupled between the input node and the sum node, and is arranged to match an impedance of the input node and provide a cancelling signal to the sum node in response to the input signal. An associated receiver is also disclosed.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Inc.
    Inventor: Chih-Fan Liao
  • Publication number: 20130194040
    Abstract: A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 1, 2013
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: REALTEK SEMICONDUCTOR CORP.
  • Publication number: 20130187716
    Abstract: In various embodiments, a pilot signal generation circuit is provided having an operational amplifier buffer connected via a first resistor to receive a source reference voltage. A differential amplifier is connected at a first input to receive the source reference voltage and at a second input to an output of the operational amplifier buffer. A first shunt transistor is connected to shunt the source reference voltage at the operational amplifier buffer in response to pulse width modulated signal. A second shunt transistor is connected to the differential operational amplifier so as to shunt the source reference voltage in response to an output of the first shunt transistor. The output of the differential amplifier provides a pulse width modulated bipolar signal at precision voltage levels in response to the pulse width modulated signal.
    Type: Application
    Filed: October 14, 2012
    Publication date: July 25, 2013
    Inventor: Albert Flack
  • Publication number: 20130187620
    Abstract: Embodiments and methods herein operate as two-stage voltage controlled current sources (i.e., dynamic current sources) operating in class AB mode. Phase-delayed current injection circuits are associated with first-stage bias, second-stage bias, or both. The current injection circuits operate to quickly re-charge inter-stage parasitic capacitance associated with the active side of the class AB dynamic current source shortly after that side becomes inactive. Doing so quickly dissipates an otherwise slowly-decaying residual drive signal to prevent the output stage from continuing to conduct after the associated side of the current source becomes inactive. Excessive current consumption and possible destructive operation of the output stage are mitigated as a result.
    Type: Application
    Filed: January 24, 2012
    Publication date: July 25, 2013
    Inventor: Charles Parkhurst
  • Publication number: 20130181778
    Abstract: A high fidelity current dumping audio amplifier in which for achieving the best performance are combined the feedforward error correction and the negative feedback. The principle of feedforward error correction in a balanced bridge in A.C. is used, including the whole audio frequency amplifier, combined with a classical negative feedback that includes the items of the amplification chain likely to introduce distortions. The amplifier can be built in a symmetrical or in a asymmetrical structure. The symmetrical structure of the amplifier contains an operational amplifier used as a voltage-current converter and signal de-phasing, two low power symmetrical amplifiers in “A” class with a current mirror structure with local feedback and a power stage in “B” class, with no quiescent current. The asymmetrical structure of the amplifier contains an operational amplifier, a low power amplifier in “A” class, and a power stage in “B” class.
    Type: Application
    Filed: November 24, 2012
    Publication date: July 18, 2013
    Inventor: Barbu Popescu
  • Patent number: 8489035
    Abstract: A radio communication transceiver includes a transformer, a switch, a power amplifier (AP), and a low noise amplifier (LNA). The transformer has a primary winding and a center-tap secondary winding, the primary winding has a first endpoint and a second endpoint, and the center-tap secondary winding has a first endpoint, a second endpoint, and a third endpoint. The switch has a gate, a drain, and a source, in which the gate receives a control signal (CS), the drain is connected to the second endpoint of the primary winding of the transformer through a coupling capacitor, and the source is grounded. The PA has at least one output terminal connected to the first endpoint and the second endpoint of the center-tap secondary winding of the transformer. The LNA has an input terminal connected to the second endpoint of the primary winding of the transformer.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: July 16, 2013
    Assignee: ISSC Technologies Corp.
    Inventors: Ming Chou Chiang, Hsin Chieh Huang
  • Publication number: 20130176082
    Abstract: A reference voltage generation circuit has: a first PN junction element; a second PN junction element having a higher forward direction voltage than the first PN junction element; a first differential amplifier inputting an anode of the first PN junction element and a first connection node between a first and a second resistor disposed in series between a first output of the first differential amplifier and a first potential, and generating a first output voltage at the first output; and a second differential amplifier inputting an anode of the second PN junction element and a second connection node between a fourth and a third resistor disposed in series between a second output of the second differential amplifier and the first output of the first differential amplifier, and generating a reference voltage at the second output. A resistance ratio between the third and the fourth resistors is variable.
    Type: Application
    Filed: November 30, 2012
    Publication date: July 11, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: FUJITSU SEMICONDUCTOR LIMITED
  • Patent number: 8482265
    Abstract: A current balance circuit includes a first branch and a second branch in parallel between a power supply unit and at least one load, which respectively include a switch. The current balance circuit detects and compares currents flowing through the first branch and the second branch. The current balance circuit also generates triangle waves and reversed triangle waves, compares voltage of a control pole of a first switch with the triangle waves, and compares voltage of the control pole of a second switch with the reversed triangle waves. Then the current balance circuit controls if the triangle waves and the reversed triangle waves are input to the first switch and the second switch according to the currents flowing through the first branch and the second branch to adjust impedance of the first switch and the second switch to balance the currents flowing through the first branch and the second branch.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: July 9, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Yi-Guo Chiu
  • Publication number: 20130169460
    Abstract: A delta-sigma modulator includes: an integrator having an operational amplifier; a quantizer quantizing an output of the integrator; a first D-A converter converting an output of the quantizer to a current signal to provide negative feedback to the operational amplifier; a feedforward path feeding forward an input of the integrator to the quantizer; and a second D-A converter converting the output of the quantizer to a current signal to provide negative feedback to the quantizer. The integrator includes a resistive element having a first end connected to the input of the integrator and a second end connected to an inverting input of the operational amplifier, n capacitive circuits connected in series between the inverting input and an output of the operational amplifier, and (n?1) resistive elements each having a first end connected to an interconnecting node of the capacitive circuits and a second end connected to a common node.
    Type: Application
    Filed: February 27, 2013
    Publication date: July 4, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: PANASONIC CORPORATION
  • Publication number: 20130170309
    Abstract: A sense-amplifier circuit of a memory, which includes a sense-amplifier unit, a first switch unit and a second switch unit. The sense-amplifier unit is constituted by a plurality of transistor switches and having a first, a second, a third and a fourth connection terminal. The first switch unit is configured to be parallel coupled between the first and second connection terminals of the sense-amplifier unit. The second switch unit is configured to be parallel coupled between the third and fourth connection terminals of the sense-amplifier unit. The first and second switch units each are constituted by a plurality of transistor switches coupled in parallel and are configured to control each of the parallel-coupled transistor switches on or off in the first and second switch units so as to calibrate a sensing range of the sense-amplifier unit. A calibrating method for a sense-amplifier circuit of a memory is also provided.
    Type: Application
    Filed: January 3, 2012
    Publication date: July 4, 2013
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventor: Shi-Wen CHEN
  • Patent number: 8476974
    Abstract: A differential amplifier comprises a first amplifier (A1) with a signal input (Inp) and a signal output (Out1) that is fed back to a first feedback input (In1) of the first amplifier (A1) and is also connected to a first output (outp) of the differential amplifier. Furthermore, a buffer circuit (Buff) is connected to the first output (outp). A nonlinear resistor circuit (Rnl1, Rnl2) is coupled via a first output node (Vmid1) with the first output (outp) and via a second output node (Vmid2) with the buffer circuit (Buff).
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: July 2, 2013
    Assignee: AMS AG
    Inventors: Thomas Carl Froehlich, Wolfgang Duenser
  • Patent number: 8476977
    Abstract: In an operational amplifier, a control unit switches an operation mode between first and second operation modes. A first output drive stage circuit section is configured to amplify a first input signal differentially-amplified by a first or a second input differential stage circuit section to output as a first drive voltage, similar to a second output drive stage circuit section. First and second power supplies: supply voltages in a first voltage range to the first differential stage circuit section and the first output drive stage circuit section in the first operation mode, supply voltages in the first voltage range to the second differential stage circuit section and the first output drive stage circuit section in the second operation mode, similar to third and fourth power supplies. The drive voltage on each of the first and second output nodes is fed back.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Nishimura
  • Publication number: 20130162353
    Abstract: A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 27, 2013
    Applicant: SK HYNIX INC.
    Inventor: SK hynix Inc.
  • Patent number: 8471639
    Abstract: A system for a feedback transimpedance amplifier with sub-40 khz low-frequency cutoff is disclosed and may include amplifying electrical signals received via coupling capacitors utilizing a transimpedance amplifier (TIA) having feedback paths comprising source followers and feedback resistors. The feedback paths may be coupled prior to the coupling capacitors at inputs of the TIA. Voltages may be level shifted prior to the coupling capacitors to ensure stable bias conditions for the TIA. The TIA may be integrated in a CMOS chip and the source followers may comprise CMOS transistors. The TIA may receive current-mode logic or voltage signals. The electrical signals may be received from a photodetector, which may comprise a silicon germanium photodiode and may be differentially coupled to the TIA. The chip may comprise a CMOS photonics chip where optical signals for the photodetector in the CMOS photonics chip may be received via one or more optical fibers.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 25, 2013
    Assignee: Luxtera Inc.
    Inventor: Brian Welch
  • Patent number: 8471631
    Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: June 25, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Tanaka, Fuminori Morisawa, Makoto Tabei
  • Patent number: 8471633
    Abstract: A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: June 25, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuchi, Sensuke Kimura
  • Publication number: 20130154742
    Abstract: An amplifier system has an amplifier for amplifying a plurality of input signals from a plurality of different channels, and a plurality of demodulators each operatively coupled with the amplifier for receiving amplified input signals from the amplifier. Each demodulator is configured to demodulate a single amplified input channel signal from a single channel of the plurality of different channels. The system thus also has a plurality of filters, coupled with each of the demodulators, for mitigating the noise.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 20, 2013
    Applicant: Analog Devices, Inc.
    Inventor: Analog Devices, Inc.
  • Publication number: 20130154741
    Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential amplifier of a cascade structure and a switched-capacitor type Common-Mode FeedBack (CMFB) circuit. The differential amplifier amplifies a difference between two input signals to output an anode output voltage and a negative output voltage. The switched-capacitor type CMFB circuit averages the anode output voltage and the negative output voltage of the differential amplifier, compares the average voltage with a reference voltage to generate a feedback signal based on a result of the comparison, and provides the feedback signal to the differential amplifier. Therefore, power consumption is reduced and a battery use time of a wireless terminal can be extended. Also, since an operational amplifier gain of each analog filter terminal is not negatively affected, a Direct Current (DC) offset is reduced, thereby improving signal quality.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 20, 2013
    Applicant: SAMSUNG ELECTRONICS CO. LTD.
    Inventor: Samsung Electronics Co., Ltd.
  • Publication number: 20130154740
    Abstract: Techniques for designing a highly linear programmable gain amplifier (PGA). In an aspect, the PGA includes a plurality of feedback switches selectively coupling an output of an operational amplifier (op amp) to an input of the op amp via a corresponding series-coupled feedback resistance. The PGA may further include a plurality of input switches selectively coupling an input of the op amp to a PGA input voltage via a corresponding series-coupled input resistance. The switches are designed such that the ratio of on-resistances between any two switches is substantially equal to the ratio of the corresponding series-coupled resistances. In an exemplary embodiment, transistors implementing the switches may be accordingly sized to implement the desired on-resistance ratios.
    Type: Application
    Filed: March 15, 2012
    Publication date: June 20, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventor: Weijun Serena Xie
  • Publication number: 20130154728
    Abstract: Some embodiments of the invention relate a transimpedance amplifier circuit having a negative feedback network that provides additional filtering of an out-of-band transmitted signal is provided herein. In one embodiment, the transimpedance amplifier circuit has a first pole, transimpedance amplifier having a multi-stage operational amplifier with an input terminal and an output terminal. An RC feedback network extends from the output terminal to the input terminal. A negative feedback network, extending from an internal node of the multi-stage operational amplifier to an input terminal of the single pole, transimpedance amplifier provides a negative feedback signal with an amplitude having an opposite polarity as the out-of-band transmitted signal. The negative feedback signal suppresses the out-of-band-transmitted signals within the demodulator circuit, thereby improving linearity of the transimpedance amplifier circuit.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Infineon Technologies AG
    Inventors: Umut Basaran, Ashkan Naeini
  • Patent number: 8466744
    Abstract: A signal filter circuit, an amplifier circuit, combinations thereof and methods for configuring and using the same are provided. Embodiments of the amplifier circuit may provide precise reproduction and amplification of input signals. The amplifier may be built entirely with discrete components or an integrated circuit may be configured to provide some or all of the modules included in the amplifier.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 18, 2013
    Assignee: Bryston-OmegaLeap Partners
    Inventor: Ioan Alexandru Salomie
  • Publication number: 20130147553
    Abstract: In aspects of the invention, at normal operation, an operational amplifier circuit has feedback applied from the output thereof to the input thereof so that currents equal to each other flow in differential pair transistors, respectively. While, in order that currents equal to each other may flow in the differential pair transistors, respectively, for compensating the difference in threshold voltages in the differential pair transistors, a voltage lower by a certain voltage difference than the voltage applied to the gate terminal of the transistor must be applied to the gate terminal of the transistor. From this, the switching of switches, when a virtual short circuit occurs, can make the output voltage of the operational amplifier circuit become a signal in which positive and negative rectangular ripples, with the values thereof being proportional to the value of the certain voltage difference, are superimposed on a true value.
    Type: Application
    Filed: November 13, 2012
    Publication date: June 13, 2013
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: FUJI ELECTRIC CO., LTD.
  • Publication number: 20130147560
    Abstract: A low noise amplifier with back-to-back connected diodes and a back-to-back connected diode with high impedance thereof are provided. The low noise amplifier includes a first operational amplifier (OP) and at least two first back-to-back connected diodes. The back-to-back connected diode with high impedance is formed from at least one MOS FET operated within a cut-off region. The first back-to-back connected diodes are connected electrically between the first input end and the first output end, and between the second input end and the second output end, of the first OP respectively. By the implementation of the present invention, the low noise amplifier is not only low noise, but also with low energy consumption, high stability, low circuitry complexity, and easily controlled manufacturing process.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 13, 2013
    Applicant: National Chip Implementation Center National Applied Research Laboratories
    Inventors: Wei-Hsien CHEN, Kuei-Cheng Lin, Bing-Song Chen, Chien-Chih Lin
  • Patent number: 8461926
    Abstract: A differential amplifier circuit includes a first/second field effect transistor including a gate coupled to a first/second differential input signal terminal, a source coupled to a reference potential node, and a drain coupled to a first/second differential output signal terminal, a first variable capacitor coupled between the gate of the first field effect transistor and the drain of the second field effect transistor, a second variable capacitor coupled between the gate of the second field effect transistor and the drain of the first field effect transistor, and a first envelope detector configured to detect an envelope of a signal at the first differential output signal terminal or the second differential output signal terminal, the first variable capacitor and/or the second variable capacitor has a capacitance that varies in accordance with an envelope detected by the first envelope detector.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 11, 2013
    Assignee: Fujitsu Limited
    Inventors: Akiko Mineyama, Yoichi Kawano, Toshihide Suzuki
  • Publication number: 20130127536
    Abstract: A fully differential operational amplifier includes a differential input stage, at least one output stage and a common-mode feedback circuit connected with the input stage. The differential input stage includes a differential pair of transistors and a bias circuit for the differential pair of transistors. A start-up circuit operates to detect an operating condition of the differential pair of transistors of the input stage and in response thereto turn on the bias circuit.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 23, 2013
    Applicants: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics S.r.l.
  • Publication number: 20130120066
    Abstract: A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier.
    Type: Application
    Filed: November 11, 2011
    Publication date: May 16, 2013
    Applicant: CREST SEMICONDUCTORS, INC
    Inventors: Tracy Johancsik, Rex K. Hales, Ryan James Kier, Yusuf Haque
  • Patent number: 8442628
    Abstract: A differential voltage sensing method for achieving input impedance matching comprises the steps of: providing a first bio-potential signal to a first variable resistor for generating a first signal; providing a second bio-potential signal to a second variable resistor for generating a second signal; differentially amplifying first and second signals for generating a third signal; selecting an operation band of the third signal for generating first and second logic signals; and dynamically adjusting one of the impedances of the first and second variable resistors according to the first and second logic signals, wherein each of the first and second bio-potential signals has a common signal voltage level and a differential signal voltage level.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: May 14, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Wen Ying Chang, Cheng Hung Chang, Ying Ju Chen
  • Patent number: 8441313
    Abstract: A current-mode analog baseband apparatus is provided. The apparatus includes a current-mode low-order filter, a current-mode programmable gain amplifier (PGA) unit and a high-order filter. The input impedance is smaller than the output impedance in the current-mode low-order filter. An input terminal of the current-mode PGA unit is connected to an output terminal of the current-mode low-order filter. An input terminal of the high-order filter is connected to an output terminal of the current-mode PGA unit.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 14, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Horng-Yuan Shih, Kai-Cheung Juang, Wei-Hsien Chen
  • Publication number: 20130106516
    Abstract: A fast settling reference voltage buffer and method are disclosed. In one of embodiments, An apparatus comprising: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal coupled to a circuit node shunt to ground by a shunt capacitor via a current sensor; a tunable resistor, controlled by a control signal, coupling the circuit node to the feedback node; a load circuit coupled to the feedback node via a switch controlled by a logical signal; and a control circuit for receiving an output of the current sensor and outputting the control signal, wherein the control signal is adapted in accordance with the output of the current sensor.
    Type: Application
    Filed: April 26, 2012
    Publication date: May 2, 2013
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang Lin
  • Publication number: 20130106514
    Abstract: A high-voltage driver amplifier for piezo haptics comprises an input amplifier having a gain greater than one, a first amplifier of an amplifier pair coupled to an output of the input amplifier, a second amplifier of the amplifier pair coupled to the output of the input amplifier, a first impedance coupled between an output of the first amplifier of the amplifier pair and an input of the input amplifier, and a second impedance coupled between the output of the first amplifier of the amplifier pair coupled to an output of the second amplifier of the amplifier pair. A substantially capacitive load is coupled to the output of the second amplifier. The substantially capacitive load is a piezo-capacitance, wherein the piezo-capacitance is employed in haptics. The second impedance, a shunt impedance, allows for a feedback of output variations between the first amplifier and the second amplifier over the first impedance.
    Type: Application
    Filed: December 16, 2011
    Publication date: May 2, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brett Earl Forejt, Mayank Garg, David John Baldwin
  • Patent number: 8432223
    Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: April 30, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Tetsuo Oomori
  • Patent number: 8427236
    Abstract: An operational amplifier includes an input differential stage having one external input receiving an external input voltage and two outputs; and two output stages. A switch section is provided between inputs of the two output stages and the two outputs of the input differential stage, and is configured to alternately connect the two outputs of the input differential stage and inputs of a positive-only output stage of the two output stages; and the two outputs of the input differential stage and inputs of a negative-only output stage of the two output stages.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: April 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Nishimura
  • Patent number: 8427355
    Abstract: An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: April 23, 2013
    Assignee: University of Macau
    Inventors: Sai-Weng Sin, Li Ding, Yan Zhu, He-Gong Wei, Chi-Hang Chan, U-Fat Chio, Seng-Pan U, Rui Paulo da Silva Martins, Franco Maloberti
  • Patent number: 8410847
    Abstract: A voltage level shifter for a direct coupling of an external voltage source to a common mode of a circuit may include an amplifier, a voltage-controlled current source, a first and second resistors. A first input of the amplifier may be connected to the common mode. A second input of the amplifier may, via the first and second resistors, receive a voltage indicative of the external voltage source. The output of the amplifier may indicate a voltage difference between the first and second inputs. The voltage-controlled current source may be controlled by the voltage difference to supply a current to a common node of the first and second resistors so that the voltage difference between the first and second inputs may be minimized.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: April 2, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Robert Libert, Khiem Quang Nguyen
  • Publication number: 20130076438
    Abstract: In one embodiment, the present invention includes a mixer having various stages, including a transconductance stage with a differential transistor pair, a bias circuit, and a feedback circuit. The transistor pair can include a first transistor having a first terminal to receive a first input radio frequency (RF) voltage and to output a first RF current via a second terminal of the first transistor, and a second transistor having a first terminal to receive a second input RF voltage and to output a second RF current via a second terminal of the second transistor. In turn, the bias circuit is coupled to the second terminals of the transistors to provide a bias current to these transistors. The feedback circuit is in turn coupled to the second terminals of the transistors to generate a feedback signal corresponding to a common mode voltage at the second terminals of the transistors.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Inventor: Tamas Marozsak
  • Publication number: 20130076439
    Abstract: A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner.
    Type: Application
    Filed: September 25, 2011
    Publication date: March 28, 2013
    Applicant: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang Lin
  • Publication number: 20130057348
    Abstract: A circuit includes a transimpedance amplifier portion having a first input node and a second input node, and a feedback circuit portion comprising a first transistor having a drain terminal connected to the first input node, a source terminal, and a gate terminal, a second transistor having a drain terminal connected to the second input node, a source terminal, and a gate terminal, and a third transistor having a drain terminal connected to the source terminal of the first transistor and the source terminal of the second terminal.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan E. Proesel, Alexander V. Rylyakov, Clint L. Schow, Jose A. Tierno