And Particular Biasing Arrangement Patents (Class 330/267)
  • Patent number: 4410814
    Abstract: A buffer circuit in an integrated circuit for applying to a connecting terminal thereof an output signal the polarity of which depends on a voltage to which an external load resistor is connected, the other end of this load resistor being connected to the terminal. The circuit comprises two output transistors arranged in series with two current measuring impedances for measuring the direction of the current flowing through the load resistor and for cutting off one of the output transistors.
    Type: Grant
    Filed: July 29, 1981
    Date of Patent: October 18, 1983
    Assignee: U.S. Philips Corporation
    Inventor: Peter A. Duijkers
  • Patent number: 4406990
    Abstract: A direct-coupled DC amplification circuit effects amplification over all the amplification stages using a ground potential as the reference voltage, and yet supplies a load with voltages in both positive and negative directions. In one preferred embodiment, a second or subsequent amplification stage including a phase compensating element has an amplification element in the form of cascode-connected complementary transistors connected to positive and negative power input terminals via first and second constant current circuits, respectively, and the set current of the first constant current circuit is set to be twice greater than that of the second constant current circuit.
    Type: Grant
    Filed: August 26, 1981
    Date of Patent: September 27, 1983
    Assignee: Stax Industries, Ltd.
    Inventor: Masao Noro
  • Patent number: 4394625
    Abstract: A semiconductor integrated circuit device including a power amplifier circuit which includes a first PNP transistor, first NPN transistor, second PNP transistor and second NPN transistor which are formed in a common semiconductor substrate. The first PNP transistor is formed as a vertical type one which constitutes, together with the second NPN transistor, a first inverted Darlington circuit. The first NPN transistor, together with the second PNP transistor, constitutes a second inverted Darlington circuit. A d.c. power source is supplied to the emitter of the vertical type PNP transistor, with the emitter of the first NPN transistor being grounded.
    Type: Grant
    Filed: December 21, 1981
    Date of Patent: July 19, 1983
    Assignee: Toko, Inc.
    Inventor: Koichi Sakai
  • Patent number: 4390852
    Abstract: A buffer amplifier suitable for use as an input amplifier for an oscilloscope comprises a hybrid FET-bipolar transistor source follower input stage and a complementary emitter follower output stage. Both the input and output stages include bootstraps to eliminate thermal transient response aberrations, to increase input impedance, and to maintain standing current in the output stage. Other attributes include a very short response time for high bandwidth operation, and high linearity.
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: June 28, 1983
    Assignee: Tektronix, Inc.
    Inventor: John L. Addis
  • Patent number: 4384261
    Abstract: In a complementary single-ended push-pull amplifier in which emitters of first and second complementary bipolar output transistors are connected through first and second emitter resistors to a load such as a loudspeaker, third and fourth complementary bipolar transistors are connected in series between the bases of the first and second bipolar transistors having their emitters connected to a bias voltage source for operating the first and second output transistors in the Class A mode. The bases of third and fourth transistors are respectively connected to the emitters of the first and second transistors, whereby a negative feedback is provided from the emitters of the first and second transistors to the bases thereof. With this arrangement, the sum of the collector currents of the first and second transistors is kept substantially constant and hence distortion of an output current (difference between the collector currents of the output transistors) fed to the load at large signal levels can be improved.
    Type: Grant
    Filed: July 1, 1981
    Date of Patent: May 17, 1983
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Kenji Yokoyama
  • Patent number: 4378530
    Abstract: An amplifier system comprising at least two tracking switching regulators or a dual-output regulator, which regulators vary the voltage across the output stage at the signal or its envelope rate.
    Type: Grant
    Filed: June 25, 1980
    Date of Patent: March 29, 1983
    Assignee: Unisearch Limited
    Inventor: Peter Garde
  • Patent number: 4370623
    Abstract: An amplifier arrangement is provided which comprises first and second biasing power supply circuits, a push-pull amplifier comprising a pair of transistors, a DC amplifier having a non-inverting input terminal connected to a junction point at which one half of a predetermined potential fed from the first biasing power supply circuit is applied and an inverting input terminal connecting a feedback loop through which the output the amplifier is fedback, a second biasing power supply circuit having a junction point at which the output of the DC amplifier is applied, and means responsive to an output of the DC amplifier for applying either of the first and second predetermined potentials fed from the first and second biasing circuits in accordance with the amount of feedback from the output of the push-pull amplifier to produce an output signal showing a biasing current, whereby the output signal is applied to each base of the push-pull transistors so as to balance the half potential of the first biasing power su
    Type: Grant
    Filed: April 13, 1981
    Date of Patent: January 25, 1983
    Assignee: Kabushiki Kaisha Nagasawa
    Inventor: Hideki Nagasawa
  • Patent number: 4366442
    Abstract: An amplifier is disclosed having a differential amplifier circuit, a current mirror circuit, a bias circuit and first and second single ended push-pull (SEPP) circuits connected in parallel to each other between a power source and earth. The first SEPP circuit includes a pair of diode-connected complementary transistors whose emitters are connected together and connected to the amplifier circuit. The second SEPP circuit includes a pair of diode-connected complementary transistors whose emitters are electrically insulated from those of the first SEPP circuit and connected to an output terminal of the amplifier. When a muting switch is opened, the supply of currents to the bias circuit is shut off, causing the first and second SEPP circuits to become unactuated and thereby attenuating an output signal from the output terminal of the amplifier.
    Type: Grant
    Filed: September 10, 1980
    Date of Patent: December 28, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hisashi Yamada
  • Patent number: 4366447
    Abstract: A push-pull amplifier circuit which is fully compensated for shortages in bias at times of high power output and in which the transistors are always maintained in their active regions. The circuit includes at least one pair of output transistors coupled in a push-pull circuit arrangement. A variable bias generating circuit controls the bias voltages applied to the bases of the output transistors according to the currents flowing in the output transistors to cause the output transistors to operate in their active regions. A circuit applies the voltage variation components at supply terminals from which current is applied to the output transistors to the variable bias generating circuit to compensate for shortages in bias during times of high power output.
    Type: Grant
    Filed: January 22, 1981
    Date of Patent: December 28, 1982
    Assignee: Pioneer Electronic Corporation
    Inventor: Yoshinobu Sugiyama
  • Patent number: 4357579
    Abstract: A power amplifier is supplied a DC power source voltage to its power-amplifying circuit from a switching regulator type DC power source. A driver circuit is supplied its DC power source voltage from a non-switching regulator type DC power source like a battery or a series regulator type DC power source, and the DC power source voltage for the driver circuit is limited to a level below the DC power source voltage for the power amplifying circuit to reduce or eliminate spurious emissions based on ripple voltage components on the signal supplied by the DC power source voltage.
    Type: Grant
    Filed: October 8, 1980
    Date of Patent: November 2, 1982
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Shuichi Kato, Hiromi Kusakabe, Hiroyasu Yamaguchi, Yoshihiro Yoshida
  • Patent number: 4356452
    Abstract: A class A complementary push-pull amplifier comprising first amplification means and second amplification means complementary in type to the first amplification means; first and second current detection means for detecting each output current of the first and second amplification means, each current detection means being coupled in serial relation with each other between output points of the first and second amplification means and a load of the push-pull amplifier being connected to a junction point of the first and second current detection means; comparator means for comparing a potential difference developed across the first current detection means and/or the second current detection means with a constant voltage to produce a control signal; and bias setting means for feeding bias current to the first and second amplification means in proportion to the control signal thereby to maintain the sum of output currents of the first and second amplification means constant.
    Type: Grant
    Filed: August 26, 1980
    Date of Patent: October 26, 1982
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Masayuki Iwamatsu
  • Patent number: 4352073
    Abstract: An amplifier includes an inverter with two transistors of complementary types. The first transistor is biased through a third transistor of the same type of conductivity by a first reference voltage, the third transistor being biased by a third voltage of reference. The second transistor is biased through a fourth transistor of the same type of conductivity by a second voltage of reference, the fourth transistor being biased by a fourth voltage of reference. The first and second voltages of reference are determined so that without any alternating input signal the current in the first and second transistors of the inverter is minimum. The third and fourth voltages of reference are determined so that the equivalent resistances of the third and fourth transistors are very high.
    Type: Grant
    Filed: June 13, 1980
    Date of Patent: September 28, 1982
    Assignee: Ebauches Electroniques SA
    Inventor: Oskar Leuthold
  • Patent number: 4349786
    Abstract: A complementary differential amplifier circuit in which a complementary differential amplifier having a first differential pair of first and second bipolar transistors of a first conductivity type and a second differential pair of third and fourth bipolar transistors of a second conductivity type is driven by source-follower circuits comprising a pair of input field effect transistors having their drains coupled together and a pair of source resistors having their first ends connected to the sources of the field effect transistors, respectively, and their second ends coupled together. A first constant voltage source or circuit such as a Zener diode is connected between the drains of the field effect transistors and the emitters of the third and fourth bipolar transistors, while a second constant voltage source or circuit is connected between the emitters of the first and second bipolar transistors and the second ends of the source resistors.
    Type: Grant
    Filed: November 3, 1980
    Date of Patent: September 14, 1982
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Kenji Yokoyama
  • Patent number: 4331930
    Abstract: A bias circuit for single-ended push-pull amplifiers permits class A or class AB operation while substantially reducing the idling current of the output transistors at low input signal levels. The bias circuit includes a DC current limiting circuit comprised of transistors that are connected between the common output of the amplifier and the bases of the output transistors. The transistors of the DC current limiting circuit limit the idling currents of the output transistors when there is no input signal applied to the amplifier. The bias circuit further includes RC/diode circuits which operate to increase or decrease the bias voltages of the transistors of the DC current limiting circuit corresponding to a decrease or an increase of the output voltage of the amplifier. In this way, the idling currents of the output transistors are changed so as to effectively follow the input signal power.
    Type: Grant
    Filed: January 8, 1980
    Date of Patent: May 25, 1982
    Assignee: Trio Kabushiki Kaisha
    Inventors: Isumi Shibata, Kazumasa Sakai, Nobuyuki Sanpei
  • Patent number: 4330757
    Abstract: The present invention prevents the destruction of an output transistor when the output terminal of a single-ended push-pull type power amplification circuit connects to a ground line or other section to form a short circuit. That is, the base-emitter of a current-detection transistor of the same conduction type as that of the transistor to be protected is connected between the base and emitter of the output transistor to be protected. The collector current of this current-detection transistor is applied to a current-voltage conversion means through a current mirror circuit, and the voltage of the current-voltage conversion means is compared with that of the output terminal by a comparator transistor. With the output of the comparator transistor, the supply of a base current to the transistor to be protected is stopped.
    Type: Grant
    Filed: August 9, 1979
    Date of Patent: May 18, 1982
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hirokazu Fukaya, Hisashi Togari
  • Patent number: 4329657
    Abstract: An amplifier with power supply switching is arranged so that the levels of the power supply voltages to be supplied to the amplifying elements of the output stage are switched over in accordance with the level and the rise time of a signal corresponding to an input signal of the amplifier, thereby, to enhance the power efficiency and to prevent an increase of distortion, as well as to reduce switching noises which tend to occur during the switching of the power supply voltages.
    Type: Grant
    Filed: October 14, 1980
    Date of Patent: May 11, 1982
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Shingo Kamiya
  • Patent number: 4319199
    Abstract: An amplifier which minimizes the power loss in its output stages is described. This is achieved by operating the several output stages from separate power supplies operating at staggered voltage levels. The output stages, which have parallel signal paths, are unity-gain emitter follower circuits connected so that the follower operating from the lowest usable power supply voltage always delivers the load current. Control circuitry shifts the load current from one output stage to another based upon the instantaneous relationship between supply voltages and the output voltage. The shift between output stages introduces very little signal distortion into the output.
    Type: Grant
    Filed: December 20, 1979
    Date of Patent: March 9, 1982
    Assignee: Tektronix, Inc.
    Inventor: Richard A. Sunderland
  • Patent number: 4318052
    Abstract: A wideband high voltage video amplifier shares the amplification of positive and negative signal peaks between positively and negatively charging output bipolar transistors, respectively, thereby circumventing distortion of the output signal by the base-to-collector junction capacitance of each transistor.
    Type: Grant
    Filed: November 30, 1979
    Date of Patent: March 2, 1982
    Assignee: Hughes Aircraft Company
    Inventor: Joseph H. Colles
  • Patent number: 4315221
    Abstract: A muting switching circuit for decoupling the output signal from an FM tuner including a transistor PNP-NPN pair push-pull connected between the terminals of a power source with a current mirror circuit supplying bias to the transistor pair in response to an input muting control signal. A middle point potential equal to one-half the voltage of the power source supplying current to the circuit is connected to a common connection point of the transistor pair so that when the transistors are rendered nonconductive by control of the input control signal, the common connection point thereof, which is also the output terminal of the circuit, is brought to the middle point potential immediately so that no pop noise is produced in the output signal. Preferably, a capacitor is coupled between the source of the middle point potential and ground to slow down transitions in the output signal when the power source is switched off or on to thereby prevent pop noise in the output signal at that time.
    Type: Grant
    Filed: September 25, 1979
    Date of Patent: February 9, 1982
    Assignee: Pioneer Electronic Corporation
    Inventors: Tatsuo Numata, Kohji Ishida
  • Patent number: 4313082
    Abstract: A circuit for providing a current having a positive temperature coefficient including a first circuit for producing a first current having substantially a constant temperature coefficient (or a negative temperature coefficient) of a first predetermined value. The first current source is coupled to a current sink circuit which sinks a known value of current from said first circuit, the current sunk by the current sink circuit having a negative temperature coefficient of a second predetermined value. The negative temperature coefficient current of the current sink circuit being greater than the negative temperature coefficient of the current source so that a difference current is provided having a positive temperature coefficient.
    Type: Grant
    Filed: June 30, 1980
    Date of Patent: January 26, 1982
    Assignee: Motorola, Inc.
    Inventor: Robert A. Neidorff
  • Patent number: 4296382
    Abstract: The output stage of a quasi-linear amplifier employs a p-channel and an n-channel FET with their sources at relatively positive and relatively negative operating voltage rails to drive a load from their drain-to-drain connection, so that despite their being enhancement types full rail-to-rail output voltage capability can be obtained without need for bootstrapping. Input signal voltage and direct-coupled feedback voltage are applied to the gate-to-gate connection of p-channel and n-channel source-followers with their respective sources direct-coupled to the gate of the p-channel FET in the output stage and to the gate of the n-channel FET in the output stage, respectively, and with their respective drains connected to the relatively positive operating voltage rail and to the relatively negative operating voltage rail, respectively, in a representative driver stage.
    Type: Grant
    Filed: December 28, 1979
    Date of Patent: October 20, 1981
    Assignee: RCA Corporation
    Inventor: Merle V. Hoover
  • Patent number: 4293875
    Abstract: The video amplifier circuit comprises a complementary symmetrical arrangement of a first and second solid state transistor element with the video input source coupled through a level shifting circuit to the first element and through a DC level shifting circuit to the second element and with means provided for operating each element in a clamped mode approaching saturation. Additional circuit modifications include means for modulating the video input signal with a high frequency signal to cause continuous gray scale variation.
    Type: Grant
    Filed: January 3, 1980
    Date of Patent: October 6, 1981
    Assignee: Telegram Communications Corp.
    Inventor: Bernard R. Katz
  • Patent number: 4286227
    Abstract: The cut-off frequency of a transistor drops remarkably when the collector-emitter voltage of the transistor is driven into the quasi-saturation region of about 1 V. To prevent this problem, the collector-emitter voltage of the transistor is detected and compared with a predetermined reference voltage by comparison-limiting means. The comparison-limiting means limits the base current of the transistor and thus restricts the drop in the collector-emitter voltage. Limiting the voltage drop in this manner prevents the transistor from being driven into the quasi-saturation region. The reference voltage is set to the p-n junction voltage in the forward direction. Hence, the drop in the collector-emitter voltage is limited to a value near this reference voltage.
    Type: Grant
    Filed: June 26, 1979
    Date of Patent: August 25, 1981
    Assignee: Hitachi, Ltd.
    Inventor: Tetsuo Sato
  • Patent number: 4274018
    Abstract: A clamp circuit is disclosed which includes a transistor connected between the multiple collectors of a bias current device for complementary output transistors and the output terminal of a driver circuit. The clamp transistor is rendered conductive by signals at the output terminal of the driver circuit which would otherwise heavily saturate the bias current device. The clamp transistor conducts current to provide additional needed bias to the complementary output device and to keep such current from disturbing the magnitudes of currents provided by a current generator circuit which is also connected to the bias current device.
    Type: Grant
    Filed: January 2, 1979
    Date of Patent: June 16, 1981
    Assignee: Motorola, Inc.
    Inventors: David L. Cave, Robert B. Davies
  • Patent number: 4268796
    Abstract: An a-c linear amplifier with two push-pull-connected output transistors includes an ancillary transistor which, during saturation of one of the output transistors and the simultaneous cutoff of a controlled transistor driving these output transistors through a set of pilot transistors, conducts to maintain the base potential of this controlled transistor at its conduction threshold for preventing a distortion of the end of the flattened peak of the corresponding half-cycle of the output voltage. The ancillary transistor has one of its input leads maintained at a fixed biasing potential and the other of its input leads connected to a point of output-dependent variable voltage that allows its conduction during the flattened peak only.
    Type: Grant
    Filed: March 26, 1979
    Date of Patent: May 19, 1981
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventor: Sergio Palara
  • Patent number: 4262262
    Abstract: An electrical amplifier comprising several partial amplifiers, which are so connected and voltage fed that each of them amplifies a voltage interval of an input voltage, wherein every partial amplifier is power fed by two supply voltage equipments, which may have the same polarity and are connected to different active components in the amplification unit of each partial amplifier. This gives great flexibility, considerable simplification in mode of operation and possibility to improve the degree of efficiency and reduces the distortion through simple means, especially at the occurence of reactive loads.
    Type: Grant
    Filed: January 31, 1979
    Date of Patent: April 14, 1981
    Inventor: Lennart H. E. Hoglund
  • Patent number: 4240040
    Abstract: An internally compensated monolithic integrated operational amplifier circuit has a differential input stage, balanced complementary common base stage, a complementary compound emitter-follower stage, and a push-pull output stage. The push-pull output stage includes complementary common emitter transistors, the base electrode of each transistor connected to a transistor connected in common base configuration. Bandwidth and slew rate are enhanced by a feed-forward capacitor connected between the amplifier inverting input and the input to the push-pull output stage and also by a range extender network connected between the output of the input differential stage and the input of the push-pull output stage. Internal bias voltages are referenced to the potential applied to the amplifier noninverting input by means of a voltage follower circuit which is interactively connected with a diode chain and current sources.
    Type: Grant
    Filed: February 11, 1974
    Date of Patent: December 16, 1980
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Veikko R. Saari
  • Patent number: 4232273
    Abstract: A limit is placed upon the maximum collector current available from a common-emitter transistor in the driver stage of an amplifier provided with overall feedback from its output stage following the driver stage to its input stage preceding the driver stage. This limit is imposed by saturation of a transistor in the input stage, which is of complementary conductivity type to the common-emitter transistor and which applies its collector current as base current to the common-emitter transistor, limiting the voltage applied to its base circuit. The common-emitter transistor in the driver stage is provided with emitter degeneration resistance, so limiting the voltage applied to its base circuit results in limiting the drive capability of the driver stage. This prevents the overall feedback increasing the output current of the driver stage so much it interferes with restriction of the base-current drive whenever a tendency towards overly large current flow through the output transistor is sensed.
    Type: Grant
    Filed: January 29, 1979
    Date of Patent: November 4, 1980
    Assignee: RCA Corporation
    Inventor: Arthur J. Leidich
  • Patent number: 4228404
    Abstract: An integrated circuit gain block is obtained by cascading a common collector stage with a complementary common emitter stage. The current density of the common emitter transistor is made sufficiently greater than that of the common collector transistor so that the common emitter V.sub.BE lowest worst case value is higher than the common collector V.sub.BE highest worst case value. This makes the circuit manufacturable in integrated circuit form and permits the circuit to operate from a single power supply potential that can be as low as the series combination of one V.sub.BE added to one transistor collector to emitter saturation voltage. The circuit has a high current gain and is amenable to incorporation into current boosted class B amplifier output stages.
    Type: Grant
    Filed: February 5, 1979
    Date of Patent: October 14, 1980
    Assignee: National Semiconductor Corporation
    Inventor: Robert J. Widlar
  • Patent number: 4218638
    Abstract: A vertical deflection amplifier includes a driver amplifier stage having a source of sawtooth deflection signals at the vertical rate and direct current feedback from the vertical deflection winding as inputs. The driver amplifier stage drives a pair of voltage translation stages each of which drives a transistor in a complementary-symmetry output stage. The voltage translation stages are independent of each other and are biased to operate as constant current sources with no signal present for controlling the quiescent current of the output stage. The improved vertical amplifier can thus be utilized to pass a horizontal rate signal combined with the vertical rate signal to effect image rotation when the deflection amplifier is used with an image pickup tube.
    Type: Grant
    Filed: October 30, 1978
    Date of Patent: August 19, 1980
    Assignee: RCA Corporation
    Inventor: David W. Breithaupt
  • Patent number: 4217555
    Abstract: In an amplifier comprising a signal-amplifying circuit for amplifying an input signal to the amplifier and a power-supply circuit for supplying power to the signal amplifying circuit for operation, there is provided an additional amplifying circuit driven by the output signal of the signal-amplifying circuit and powered from said power circuit. Changes in the power-supply currents for the respective amplifying circuits cancel each other. Thus, the total current supplied from the power supply circuit is maintained constant.
    Type: Grant
    Filed: December 8, 1978
    Date of Patent: August 12, 1980
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Masayuki Iwamatsu
  • Patent number: 4205273
    Abstract: A pulse signal amplifier includes a pair of complementary drive transistors and a pair of complementary output transistors, each being connected in an emitter-follower circuit to supply an amplified pulse signal to an inductive load. A leakage current from said inductive load is prevented from flowing to the base-emitter circuit of the output transistor by a current limiting circuit.
    Type: Grant
    Filed: January 26, 1979
    Date of Patent: May 27, 1980
    Assignee: Sony Corporation
    Inventor: Tadao Yoshida
  • Patent number: 4199732
    Abstract: An amplifying circuit comprising an input terminal to which an alternating current signal is applied; a first transistor; a second transistor where one of the first and second transistors is a NPN transistor and the other is a PNP transistor; an output terminal to which is connected the respective collectors of the first and second transistors means for operating the second transistor as a constant current source; and connecting means for connecting the alternating current signal at the input terminal to the respective bases of the first and second transistors where the connecting means includes a capacitor connected between the input terminal and the base of the second transistor to thereby connect to the second transistor substantially only those frequencies of the alternating current signal which are at least as high as the cut-off frequency of the first transistor although frequencies below the cut-off frequency may also be coupled to the second transistor in a further embodiment of this invention.
    Type: Grant
    Filed: May 31, 1978
    Date of Patent: April 22, 1980
    Assignee: Trio Kabushiki Kaisha
    Inventor: Tatsuhiko Okuma
  • Patent number: 4195267
    Abstract: In a low-level audio preamplifier circuit having complementary connected PNP and NPN bipolar transistors cascode coupled to other complementary PNP and NPN bipolar transistors in receiving the audio input from a low-level transducer in which induced distortion from externally generated radio frequence energy is cancelled.
    Type: Grant
    Filed: November 6, 1978
    Date of Patent: March 25, 1980
    Assignee: Crown International, Inc.
    Inventor: Gerald R. Stanley
  • Patent number: 4178559
    Abstract: The use of a nonlinear device such as a diode inserted in series with the load impedance of a transistor amplifier stage will reduce even and odd order distortion and thus improve the overall linearity characteristics of the amplifier.
    Type: Grant
    Filed: September 11, 1978
    Date of Patent: December 11, 1979
    Assignee: Rockwell International Corporation
    Inventor: Richard A. Nichols
  • Patent number: 4167708
    Abstract: A transistor amplifier comprises an input stage circuit and an output stage circuit direct-coupled to the input stage circuit: the input stage including complimentary paired transistors having bases commonly connected to an input terminal and emitters AC-wise grounded and further connected to constant current sources, respectively; the output stage being a single-ended push-pull amplifier circuit including complimentary paired transistors having bases connected to collectors of the input stage transistors, respectively, and emitters commonly connected to an output terminal. This transistor amplifier has advantages that it is simple in arrangement and that both its DC and AC operations are highly stabilized against variations in the ambient temperature and in the voltages of operating power supplies.
    Type: Grant
    Filed: March 7, 1978
    Date of Patent: September 11, 1979
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Motoomi Goto
  • Patent number: 4165494
    Abstract: A bi-state linear amplifier is provided which, in response to a first state of a control signal, functions as a linear amplifier, and in response to a second state of a control signal, is cut off to define a high output impedance. The amplifier includes a control circuit responsive to relatively low-current control signals for selectively opening and closing the internal amplification circuit of the amplifier.
    Type: Grant
    Filed: April 28, 1978
    Date of Patent: August 21, 1979
    Assignee: Circuit Technology Incorporated
    Inventor: Barry E. Becker
  • Patent number: 4160216
    Abstract: A high fidelity audio amplifier having a pair of cooperating active amplifying devices includes two diodes, each of which is connected in a distinct signal pathway directly associated with an active amplifying device so that the amplifier achieves true Class A operation over the full range of normal input signals. The amplifier can achieve true Class A operation using bipolar transistors, field effect transistors, or vacuum tubes as the active amplifying devices.
    Type: Grant
    Filed: January 16, 1978
    Date of Patent: July 3, 1979
    Inventor: Barry W. Thornton
  • Patent number: 4158820
    Abstract: In a low level audio preamplifier circuit having complementary connected PNP and NPN bipolar transistors for receiving the audio input from a low level transducer such as a tape head, in which induced distortion from externally generated radio frequency energy is cancelled with minimal loss of audio fidelity.
    Type: Grant
    Filed: February 1, 1978
    Date of Patent: June 19, 1979
    Assignee: Crown International, Inc.
    Inventor: Gerald R. Stanley
  • Patent number: 4152665
    Abstract: The present invention comprises a circuit for addition to a non-linear amplifier wherein the non-linearity is of the first degree. The circuit essentially adds a signal (or signal variable impedance path) to that already existing to remove non-linearity in operating characteristics over a given range of voltage.
    Type: Grant
    Filed: February 27, 1978
    Date of Patent: May 1, 1979
    Assignee: Rockwell International Corporation
    Inventor: Vernon R. Cunningham
  • Patent number: 4135162
    Abstract: A power amplifier circuit having a differential amplifier at an input stage and a following complementary symmetry circuit which is driven by a pair of opposite phase output signals of the differential amplifier as a push-pull circuit. One of the pair output signals is directly applied to a transistor of the complementary symmetry circuit and the other is applied to the other transistor of the complementary symmetry circuit through a phase-inverting transistor which forms a current mirror circuit together with a diode or a transistor being connected in the collector circuit of the transistor of the differential amplifier corresponding to the other output signal. So that the pair of opposite phase output signals are applied to two transistors of the complemeary symmetry circuit after being converted into in-phase signals.
    Type: Grant
    Filed: October 11, 1977
    Date of Patent: January 16, 1979
    Assignee: Sansui Electric Co., Ltd.
    Inventor: Susumu Takahashi
  • Patent number: 4128813
    Abstract: An amplifier comprised of a field effect transistor whose gate electrode is adapted to receive an input signal. An impedance converter couples the input signal to the gate electrode of the field effect transistor, the impedance converter being formed of n impedance converting stages, each stage having a relatively low output impedance. A voltage limiting circuit is connected between the source of input signal and the gate electrode of the field effect transistor so as to limit the forward biasing of the field effect transistor. This voltage limiting circuit includes m voltage-limiting elements, wherein n and m are integers (1, 2, 3, . . . ) and n is equal to or greater than m. In a preferred embodiment, the amplifier is formed of two field effect transistors connected in push-pull relation, each field effect transistor being provided with an impedance converter and a voltage-limiting circuit as described above.
    Type: Grant
    Filed: November 18, 1977
    Date of Patent: December 5, 1978
    Assignee: Sony Corporation
    Inventors: Tadao Suzuki, Tadao Yoshida
  • Patent number: 4117418
    Abstract: An electric amplifier useful for instance in simulators for strong electric signals, comprising several partial amplifiers so connected and voltage fed that they will amplify an interval each of the input voltage. Every partial amplifier comprises at least one amplification component and two gates, of which gates one is blocking those potentials applied to the component that are less than a given first value but is open for potentials exceeding said value while the other gate is open for potentials less than a given second value greater than said first value but is blocking the component for potentials exceeding said second value.
    Type: Grant
    Filed: January 14, 1977
    Date of Patent: September 26, 1978
    Inventor: Lennart Harry Erik Hoglund
  • Patent number: 4115742
    Abstract: An emitter follower type power amplifier capable of changing over supply voltage and hence the load line, comprising: an amplifying transistor of saturating type; at least a first and a second supply voltage source; a switching transistor having, a collector connected to the first supply voltage source, and an emitter connected to the second supply voltage source via a diode and also to the collector of said power amplifying transistor; a load resistor connected between the emitter of the power amplifying transistor and the ground; and a biasing voltage source connected between the base of the switching transistor and the emitter of the power amplifying transistor. This power amplifier circuit arrangement allows switching-over between load lines for small signal region and large signal region thereby enabling large signal amplification and reducing the collector loss of the power amplifying transistor. This circuit arrangement is also used in a push-pull power amplifying circuit to obtain the same advantage.
    Type: Grant
    Filed: March 18, 1977
    Date of Patent: September 19, 1978
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Kenji Yokoyama
  • Patent number: 4114109
    Abstract: An amplifier circuit suitable for use as a video amplifier in a color television circuit for driving the variable impedance load provided by a color television picture tube, in which the load impedance of the amplifier element of the circuit is also made variable. This is achieved, in one embodiment by using as the output stage of the amplifier two transistors with a complementary symmetrical configuration so that one is always substantially cut-off while the other conducts. In another embodiment a transistor in common collector configuration acts as the amplifier element and its emitter from which the output of the amplifier is taken is connected by a diode to the collector of a transistor which feeds the base of the common collector transistor.
    Type: Grant
    Filed: May 3, 1977
    Date of Patent: September 12, 1978
    Assignee: Indesit Industria Elettrodomestici Italiana S.p.A.
    Inventor: Armando Campioni
  • Patent number: 4100501
    Abstract: An audio frequency power amplifier wherein an input signal is applied to respective input electrodes of a pair of transistors of the same conductivity type to produce an output signal at an output electrode of one of the pair of transistors. A common electrode of the one transistor is connected with an output electrode of the other transistor and a power from a first D.C. power supply is supplied to the junction thereof through a diode while a power is supplied to a common electrode of the other transistor from a second D.C. power supply having a higher voltage than that of the first D.C. power supply. The other transistor and the diode are alternately rendered conductive and non-conductive in response to the signal level of the input signal, a capacitor is connected to the input electrode of the other transistor, which capacitor is charged during the turn-off of the other transistor whereby the charge is supplied to the other transistor upon turning on of the other transistor to shorten the rise time.
    Type: Grant
    Filed: February 11, 1977
    Date of Patent: July 11, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Harushige Nakagaki, Tohru Sampei, Nobutaka Amada, Tatsuo Baba
  • Patent number: 4099139
    Abstract: A power amplifier circuit comprising a voltage amplifier stage and a current amplifier stage, the mode of bias of which can be changed over between class A and class B (AB). The supply voltage for the current amplifier stage is changed over by a mode selection switch. The change in the supply voltage is detected to select the bias voltage for the current amplifier stage.The possibility of applying a class A bias to the current amplifier stage supplied with a class B line voltage is thus completely removed.
    Type: Grant
    Filed: February 8, 1977
    Date of Patent: July 4, 1978
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventor: Kenro Oguri
  • Patent number: 4096443
    Abstract: A low distortion audio amplifier utilizes a pair of field effect transistors connected in a balanced source follower configuration. A tapped inductor connected between the sources of the field effect transistors provides inductive coupling between the sources and maintains the sources at the same direct current potential. This permits the voice coil of a loud speaker to be connected directly across the sources without causing excessive direct current to flow through the voice coil.
    Type: Grant
    Filed: February 16, 1977
    Date of Patent: June 20, 1978
    Inventor: Warren E. Gilson
  • Patent number: 4095189
    Abstract: The amplifier comprises at least two amplifier units or transistors T.sub.1 and T.sub.2 of complementary types. The base of the first transistor T.sub.1 is connected to a control current supply line. The emitter of the transistor T.sub.1 is connected on the one hand to one end of the load impedance and on the other hand to the base of the second transistor T.sub.2. The collector of the transistor T.sub.1 is connected to a voltage supply of suitable polarity. The emitter of the transistor T.sub.2 is connected to the current supply line and the collector of said transistor is connected to another end of the load impedance.
    Type: Grant
    Filed: February 7, 1977
    Date of Patent: June 13, 1978
    Inventor: Paul Nguyen-Tan Tai
  • Patent number: 4087761
    Abstract: An audio power amplifier can be operated in either class A, class B or class AB amplifier modes by selectively switching bias values set in a bias setting circuitry provided for a driver stage which drives the main power amplifier stage.
    Type: Grant
    Filed: June 24, 1976
    Date of Patent: May 2, 1978
    Assignee: Nippon Gakki Seizo Kabushiki Kaisha
    Inventors: Nobuo Fukumoto, Mitsugo Ohiwa, Teruyoshi Matsui, Hajime Ohta