Including Current Mirror Amplifier Patents (Class 330/288)
  • Patent number: 8729874
    Abstract: A voltage regulator for low power operation of digital circuits includes an output node for providing a regulated output voltage, a diode-connected P-channel transistor in series with a second diode-connected N-channel transistor coupled between the output node and ground, and a bias current having a value for biasing the first and second diode-connected transistors in a sub-threshold mode of operation. The low power voltage regulator further includes a buffer amplifier or emitter or source follower stage to provide a low impedance regulated voltage. The bias current may be generated by a bandgap circuit.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: May 20, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Agustin Ochoa
  • Patent number: 8723603
    Abstract: Amplifiers with voltage and current feedback error correction are provided. In one embodiment, an amplifier includes a first input terminal, a second input terminal, an output terminal, a first stage, and a voltage feedback amplification circuit. The first stage can be used to generate first and second output currents, which can be used to control a voltage level of the output terminal. The first and second output currents can change in response to a current feedback signal and a differential input signal received between the first and second input terminals. The first stage can also generate a voltage feedback signal, which can be used by the voltage feedback amplification circuit to control a voltage level of the second input terminal based on a voltage level of the first input terminal.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 13, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Derek Bowers
  • Publication number: 20140104003
    Abstract: The disclosure provides an operational amplifier circuit, in which a power supply of an amplifying circuit is coupled to a first voltage clamping circuit, and the first voltage clamping circuit clamps a supply voltage of the amplifying circuit when the supply voltage exceeds a normal-operation allowable voltage of the amplifying circuit. The disclosure also provides a method for implementing the operational amplifier circuit. According to the disclosure, the operational circuit may be avoided from subject to an excessive supply voltage, which may damage devices in the amplifying circuit of the operational amplifier.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 17, 2014
    Applicant: Fairchild Semiconductor Corporation
    Inventors: Lei Huang, Hongtao LV, Yangfang Li
  • Patent number: 8692617
    Abstract: A current-sensing differential amplifier has a balanced input. Thus, a balanced-input current-sensing differential amplifier has a first signal input terminal, a second signal input terminal, a first signal output terminal and a second signal output terminal. The balanced-input current-sensing differential amplifier includes a first current mirror, the input terminal of the first current mirror being coupled to the first signal input terminal, a second current mirror, the input terminal of the second current mirror being coupled to the second signal input terminal, a third current mirror, one of the output terminals of the third current mirror being coupled to the common terminal of the first current mirror and to the common terminal of the second current mirror, three current sources and an output circuit.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: April 8, 2014
    Assignee: Tekcem
    Inventors: Frederic Broyde, Evelyne Clavelier
  • Publication number: 20140085005
    Abstract: Apparatus and methods for reducing load-induced non-linearity in amplifiers are provided. In certain implementations, an amplifier includes a current mirror, a buffer circuit, and an output stage. The buffer circuit can have a relatively high current gain and a voltage gain about equal to 1. The buffer circuit can amplify a mirrored current generated by the current mirror and provide the amplified mirrored current to the output stage, thereby helping to balance or equalize currents in the current mirror and avoiding the impact of load-induced offset error.
    Type: Application
    Filed: September 24, 2012
    Publication date: March 27, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Moshe Gerstenhaber, Rayal Johnson
  • Patent number: 8644759
    Abstract: Offset voltages developed on floating nodes on inputs to high-performance amplifiers that are DC isolated from the data signals input to amplifiers are cancelled by connecting a highly resistive element between the input node and a predetermined potential, particularly useful in proximity communication systems in which two chips are connected through capacitive or inductive coupling circuits formed jointly in the two chips. The resistive element may be an off MOS transistor connected between the node and a desired bias voltage or a MOS transistor with its gate and drain connected to the potential. Multiple bias voltages may be distributed to all receivers and locally selected by a multiplexer for application to one or two input nodes of the receiver. The receiver output can also serve as a predetermined potential when the resistive element has a long time constant compared to the data rate or the resistive element is non-linear.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: February 4, 2014
    Assignee: Oracle America, Inc.
    Inventors: Justin M. Schauer, Robert David Hopkins, Robert J. Drost
  • Publication number: 20140015611
    Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tao Wen CHUNG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Yuwen SWEI
  • Patent number: 8610614
    Abstract: A CMOS current-mode folding amplifier circuit is provided that uses MOSFETs operating in relatively strong inversion. The CMOS current-mode folding amplifier circuit produces a saw-tooth shaped input-output characteristic which provides for relative precision in flash-type analog-to-digital converters. Furthermore, the CMOS current-mode folding amplifier circuit uses a plurality of simple current mirrors, in addition to biasing currents, for defining the switching levels. Accordingly, the current-mode amplifier requires less area on the chip and consumes less power relative to other analog preprocessing circuits. Moreover, the CMOS current-mode folding amplifier circuit is resilient to process, temperature and power supply variations. Tanner simulation tools using 0.35 ?m CMOS technology confirm the functionality of the current-mode folding amplifier.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: December 17, 2013
    Assignees: King Fahd University of Petroleum and Minerals, King Abdulaziz City for Science and Technology
    Inventors: Munir A. Al-Absi, Muhammad T. Abuela'Atti, Shaker A. Mahemood
  • Patent number: 8598953
    Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: December 3, 2013
    Assignee: Skyworks Solutions, Inc.
    Inventors: Robert Michael Fisher, Michael L. Hageman, David S. Ripley
  • Publication number: 20130300506
    Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.
    Type: Application
    Filed: July 17, 2013
    Publication date: November 14, 2013
    Applicant: Marvell World Trade Ltd.
    Inventors: Poh Boon Leong, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 8542065
    Abstract: A trans-impedance amplifier (TIA) for an optical receiver is disclosed, where the TIA stabilizes the cross point in the output thereof independent of the variation of the power supply. The TIA of the invention includes an amplifier section, a source follower, and a bias generator. A transistor in the source follower to define the current flowing in the source follower and another transistor in the bias generator constitute a current-mirror circuit. The operating point of the other transistor in the bias generator depends on the variation of the power supply. The output level of the amplifier section follows the variation of the power supply.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: September 24, 2013
    Assignee: Sumitomo Electric Industries Ltd.
    Inventor: Takashi Sawa
  • Patent number: 8519794
    Abstract: A current mirror circuit provided in an emitter follower configuration achieves linearly output over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: August 27, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Sandro Herrera
  • Patent number: 8514023
    Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: August 20, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Poh Boon Leong, Krishnasamy Maniam Nuntha Kumar
  • Patent number: 8502604
    Abstract: A differential amplifier layout includes a current mirror having a first transistor, a second transistor, and a third transistor. The current mirror receives a first power supply through the first transistor. The second transistor is part of a reference current branch and the third transistor is part of a mirror current branch. The first transistor comprises a first group of fingers disposed adjacent one side of the second transistor and a second group of fingers disposed adjacent one side of the third transistor.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: August 6, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young Geun Lee
  • Patent number: 8487701
    Abstract: A circuit for amplifying a signal representing a variation in resistance of a variable resistance comprising at least one first load linked to an output terminal of a first transistor whose other terminal is associated with a variable resistance, in such a way as to allow the recovery of the amplified signal at the terminals of the first load.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: July 16, 2013
    Assignee: Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: El Mehdi Boujamaa, Pascal Nouet, Frederick Mailly, Laurent Latorre
  • Patent number: 8487702
    Abstract: A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Realtek Semiconductor Corp.
    Inventor: Chia-Liang Lin
  • Patent number: 8471631
    Abstract: There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: June 25, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Tanaka, Fuminori Morisawa, Makoto Tabei
  • Publication number: 20130076445
    Abstract: There is provided a power amplifying apparatus with dual-current control mode, including: a transistor mirror circuit adjusting currents respectively flowing through a main path and a mirror path connected in parallel to a power source terminal; a resistor mirror circuit adjusting the respective currents of the main path and the mirror path; a current controlling unit controlling a control current flowing through the main path with a pre-set constant current; a voltage adjusting unit providing a bias adjustment signal that corresponds to a difference voltage between a first voltage of a first node on the main path to which a current is output from the resistor mirror circuit and a second voltage of a second node on the mirror path to which a current is output from the resistor mirror circuit; and a bias circuit unit adjusting a bias of a power amplifying unit.
    Type: Application
    Filed: December 13, 2011
    Publication date: March 28, 2013
    Inventors: Youn Suk KIM, Jun Kyung NA, Sang Hoon HA, Shinichi IIZUKA
  • Patent number: 8400219
    Abstract: Circuits are disclosed that may include a plurality of transistors having controllable current paths coupled between at least a first and second node, the transistors configured to generate an analog electrical output signal in response to an analog input value; wherein at least one of the transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: March 19, 2013
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson
  • Publication number: 20130063212
    Abstract: A transimpedance amplifier includes a first MOS transistor, a current mirror circuit, a second MOS transistor, a load and a first feed back resistor. The first MOS transistor has a gate terminal to which a photodiode is connected. An output current of the first MOS transistor is input to the current mirror. The second MOS transistor has a gate terminal to which a voltage of an output terminal of the current mirror circuit is input. A source of the second MOS transistor is grounded. A polarity of the second MOS transistor is same as a polarity of the first MOS transistor. A first feedback resistor is connected between the gate terminal of the first MOS transistor and a drain terminal of the second MOS transistor. The second MOS transistor outputs a voltage corresponding to the voltage of the output terminal from the drain terminal.
    Type: Application
    Filed: March 20, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukiko TAKIBA, Shigeyuki Sakura
  • Patent number: 8390491
    Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 5, 2013
    Assignee: Analog Devices, Inc.
    Inventor: Tsutomu Wakimoto
  • Publication number: 20130043952
    Abstract: A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device.
    Type: Application
    Filed: October 15, 2012
    Publication date: February 21, 2013
    Inventors: Armin Prohaska, Terje Saether, Holger Vogelmann
  • Patent number: 8380157
    Abstract: Systems and methods for implementing an up-conversion mixer with signal processing are disclosed.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Zisan Zhang, Dieter Draxelmayr
  • Publication number: 20130038394
    Abstract: The present invention relates to an operational amplifier comprising an input-stage circuit, a floating current mirror circuit, and an output-stage circuit. The input-stage circuit receives an input signal and produces a control signal. The floating current mirror circuit is coupled to the input-stage circuit, and produces a mirror current according to the control signal. The output-stage circuit is coupled to the floating current mirror circuit, and produces a driving signal according to the mirror current. When the operational amplifier is operating in the static mode, the output-stage circuit further produces a static current according to the mirror current. Thereby, by using the floating current mirror circuit, the purpose of low power consumption can be achieved while driving to the high-voltage mode or to the low-voltage mode.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 14, 2013
    Applicant: SITRONIX TECHNOLOGY CORP.
    Inventor: PING LIN LIU
  • Patent number: 8373491
    Abstract: A current mirror circuit exhibits improved current matching by applying a switching signal to ground path switches in series with transistors in both a reference path and an output path of the current mirror. The switching signal may comprise a high-frequency signal, which may be phase modulated. A plurality of matched, parallel-connected output transistors may be selectively enabled by qualifying the switching signal applied to each corresponding series-connected ground path switches by decoded digital modulation data. In one embodiment, the modulation data is decoded to thermometer-coded representation. In one embodiment, the switching signal path is identical to the reference and output circuits.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: February 12, 2013
    Assignee: ST-Ericsson SA
    Inventors: Norbert Van Den Bos, Roeland Heijna, Hendrik Visser
  • Publication number: 20130021103
    Abstract: An amplifier including a high supply voltage source and a low supply voltage source and two parallel signal paths. Each signal path is connected to the high and the low supply voltage sources and includes a first amplifier and a second amplifier. The two signal paths are connected to each other only at a common input node and a common output node, so that the respective first amplifiers operate independently of each other. The first amplifiers are configured to convert at least a part of an input voltage signal into a signal current. The signal paths are configured so that the signal current in use drives the respective second amplifier to provide an amplified output current to the common output node.
    Type: Application
    Filed: February 9, 2011
    Publication date: January 24, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Gavin Watkins
  • Patent number: 8351493
    Abstract: A folding adaptive equalizer is provided. The equalizer comprises an equalizer core and an automatic gain control loop. The equalizing transfer function of the equalizer core is modulated by one or more gain control signals generated by the automatic gain control loop and by a folding signal generated by the automatic gain control loop. When the folding signal is inactive, an increase in the gain control signals produces an increase in the high-frequency, high-bandwidth gain of the transfer function of the equalizer core. When the folding signal is active, further gain can be applied by decreasing the gain control signals, which produces a frequency-shift in the transfer function of the equalizer core toward lower bandwidth and an increase in the high-frequency, low-bandwidth gain of the transfer function of the equalizer core.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: January 8, 2013
    Assignee: Gennum Corporation
    Inventors: Hossein Shakiba, Mansour Shashaani
  • Patent number: 8334724
    Abstract: A microcontroller integrated circuit includes an open-loop transimpedance amplifier (OLTA). An input lead of the OLTA is a terminal of the microcontroller. The cathode of a photodiode is connected to VDD and the anode is connected to the terminal. The OLTA maintains the photodiode in a strongly reverse-biased condition, thereby keeping diode capacitance low and facilitating rapid circuit response. The input of the OLTA involves a diode-connected field effect transistor that provides a low impedance. This low impedance decreases as the diode current increases, thus providing effective clamping of the voltage on the terminal. By this clamping, the amount of photodiode capacitance discharging necessary when transitioning from a high input current condition to a low input current condition is reduced, thereby further improving amplifier response time. The OLTA is small and consumes less than thirty microamperes and functions to mirror photodiode current and compare to a predetermined level.
    Type: Grant
    Filed: August 12, 2012
    Date of Patent: December 18, 2012
    Assignee: IXYS CH GmbH
    Inventor: David R. Staab
  • Publication number: 20120306577
    Abstract: A microcontroller integrated circuit includes an open-loop transimpedance amplifier (OLTA). An input lead of the OLTA is a terminal of the microcontroller. The cathode of a photodiode is connected to VDD and the anode is connected to the terminal. The OLTA maintains the photodiode in a strongly reverse-biased condition, thereby keeping diode capacitance low and facilitating rapid circuit response. The input of the OLTA involves a diode-connected field effect transistor that provides a low impedance. This low impedance decreases as the diode current increases, thus providing effective clamping of the voltage on the terminal. By this clamping, the amount of photodiode capacitance discharging necessary when transitioning from a high input current condition to a low input current condition is reduced, thereby further improving amplifier response time. The OLTA is small and consumes less than thirty microamperes and functions to mirror photodiode current and compare to a predetermined level.
    Type: Application
    Filed: August 12, 2012
    Publication date: December 6, 2012
    Applicant: IXYS CH GmbH
    Inventor: David R. Staab
  • Patent number: 8289082
    Abstract: A circuit and a method for correcting an offset is provided that includes a current amplifier and an adjusting circuit for correcting an offset of an output current of the current amplifier. Wherein the adjusting circuit has a controlled current source, an output of the controlled current source is connected to the current amplifier for impressing an output current of the controlled current source in the current amplifier, an input of the controlled current source to form a regulation element of a control loop is connected by a first switching device of the adjusting circuit to an output of the current amplifier and to form a holding element is disconnected from the output of the current amplifier by the first switching device.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: October 16, 2012
    Assignee: Atmel Corporation
    Inventors: Armin Prohaska, Terje Saether, Holger Vogelmann
  • Publication number: 20120256690
    Abstract: A power amplifier circuit can be linked to an antenna arrangement of a communication system for transmission of ASK RF data signals. The power amplifier circuit includes an amplifier core with several cascode amplifier cells in parallel. Each cascode amplifier cell is composed of three NMOS transistors in triode mounting between an output terminal connected to the antenna arrangement, and an earth terminal. A first transistor of each cascode amplifier cell is controlled by a carrier frequency signal, whereas a second transistor of each cascode amplifier cell is controlled by a smoothing control loop in order to modulate data to be transmitted on carrier frequency by amplitude shift keying. The smoothing control loop is provided for generating an increasing gate voltage for the second transistors on the basis of an increasing current ramp from a first minimum current value to a second maximum current value during a “0” to “1” data transition.
    Type: Application
    Filed: April 5, 2011
    Publication date: October 11, 2012
    Applicant: EM MICROELECTRONIC-MARIN S.A.
    Inventors: Kevin Scott Buescher, Michal Prokes
  • Publication number: 20120242410
    Abstract: An amplifier for an integrated circuit has a plurality of ratioed current mirrors connected to each other in a stacked configuration. Each ratio mirror has at least two resistors and at least two bipolar transistors connected to each other via said at least two resistors. Each amplifying transistor, contains a capacitor, and potentially and inductor, to internally match the transistors that make up the amplifying stack. DC, harmonic and s-parameter simulations are performed to provide an optimal impedance for each of the stacked transistors to maximize the RF power output of each stacked layer and the amplifier.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 27, 2012
    Inventors: Ali DARWISH, Thomas J. FARM, Mona ZAGHLOUL
  • Patent number: 8269562
    Abstract: A microcontroller integrated circuit includes an open-loop transimpedance amplifier (OLTA). An input lead of the OLTA is a terminal of the microcontroller. The cathode of a photodiode is connected to VDD and the anode is connected to the terminal. The OLTA maintains the photodiode in a strongly reverse-biased condition, thereby keeping diode capacitance low and facilitating rapid circuit response. The input of the OLTA involves a diode-connected field effect transistor that provides a low impedance. This low impedance decreases as the diode current increases, thus providing effective clamping of the voltage on the terminal. By this clamping, the amount of photodiode capacitance discharging necessary when transitioning from a high input current condition to a low input current condition is reduced, thereby further improving amplifier response time. The OLTA is small and consumes less than thirty microamperes and functions to mirror photodiode current and compare to a predetermined level.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 18, 2012
    Assignee: IXYS CH GmbH
    Inventor: David R. Staab
  • Publication number: 20120188019
    Abstract: Provided is an output circuit capable of allowing a more sufficient output current to flow. When a drain current of a PMOS transistor (12) is large, a PMOS transistor (13) operates in the non-saturation region. At this time, gate voltages of NMOS transistors (14 and 17) have risen to around a power supply terminal voltage. Therefore, a gate-source voltage of an NMOS transistor (17) increases, and a sufficient output current flows.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 26, 2012
    Inventor: Tsutomu Tomioka
  • Publication number: 20120188428
    Abstract: A solid-state imaging device and a camera system are disclosed. The solid-state imaging device includes a pixel unit and a pixel signal readout circuit. The pixel signal readout circuit includes a plurality of comparators disposed to correspond to a pixel column array, and a plurality of counters. Each counter includes a first amplifier, a second amplifier, and a mirror circuit to from a current mirror in parallel with the second amplifier. The first amplifier includes differential transistors, initializing switches connected between gates and collectors of the differential transistors, and first and second capacitors connected to each of the gates of the differential transistors. The second amplifier includes an initializing switch and a third capacitor. The mirror circuit includes a gate input transistor whose gate is inputted with a voltage sampled by the first amplifier or a voltage sampled by the second amplifier.
    Type: Application
    Filed: April 2, 2012
    Publication date: July 26, 2012
    Applicant: SONY CORPORATION
    Inventor: Kenichi TANAKA
  • Publication number: 20120182073
    Abstract: An apparatus and method for programmable power management in a programmable analog circuit block. Specifically, the present invention describes an operational amplifier circuit that includes current sources that are coupled in parallel. Configuration bits are asserted to selectively enable or selectively disable one or more of the current sources in order to modulate the performance of the operational amplifier circuit block. Selective addition or removal of current sources increases or decreases the amount of current within the operational amplifier and, correspondingly, the speed and power consumption of the operational amplifier. Combinations of asserted configuration bits pass a bias voltage in order enable selected current sources. In one embodiment, the bias voltage can be increased in order to increase the current output of one of the current sources which, correspondingly, increases the speed of the operational amplifier circuit block.
    Type: Application
    Filed: December 16, 2011
    Publication date: July 19, 2012
    Applicant: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Monte Mar
  • Publication number: 20120182167
    Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventor: Tsutomu WAKIMOTO
  • Publication number: 20120176198
    Abstract: There is provided a bias circuit including a power amplifier in which influence of variation of a gate length L is reduced and variation of a gain among products is low. Two NPN- and PNP-type current mirror circuits 101 (NPN type) and 102 (PNP type) are inserted on an input side of a bias circuit 103. It is designed that a gate length of a transistor Q1 on an output side of the current mirror circuit 101 is longer than that of the other transistor. In this manner, even when an error is generated, influence of the error can be suppressed to be small.
    Type: Application
    Filed: September 30, 2009
    Publication date: July 12, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Tanaka, Fuminori Morisawa, Makoto Tabei
  • Publication number: 20120161876
    Abstract: A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 28, 2012
    Inventors: Poh Boon Leong, Nuntha Kumar Krishnasamy Maniam
  • Patent number: 8203383
    Abstract: A current mirroring circuit is provided. The circuit generally comprises a current source; a first drain extended (DE) MOS transistor, a second DE MOS transistor, a current mirror, and differential amplifier. The current source is generally coupled to the current source at its drain, while the current mirror that is coupled to the sources of the first and second DE MOS transistors and to the current source. The differential amplifier generally has a first input that is coupled to the source of the first DE MOS transistor, a second input that is coupled to the source of the second DE MOS transistor, a first output that is coupled to the gate of the second DE MOS transistor, and a second output that is coupled to the gate of the first DE MOS transistor.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: June 19, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Sandeep Oswal, Neetin Agrawal
  • Publication number: 20120139637
    Abstract: There is provided a linear amplifier capable of suppressing a reduction in bandwidth and reducing a ripple voltage by using a source follower and a local feedback loop. The linear amplifier includes an amplifier amplifying an input signal according to a difference in signal level between the input signal and a feedback signal, and a buffer buffering a signal amplified in the amplifier by a source follow method, suppressing a reduction in bandwidth of the signal, outputting the signal, and providing the buffered signal to the amplifier as the feedback signal.
    Type: Application
    Filed: December 6, 2011
    Publication date: June 7, 2012
    Inventors: Yu Sin KIM, Youn Suk Kim, Gyu Hyeong Cho, Chang Seok Chae, Young Sub Yuk
  • Patent number: 8183926
    Abstract: An electronic circuit including: a first branch, placed between two terminals of application of a D.C. voltage, including a series connection of a first constant current source, of a first diode-connected N-channel MOS transistor, of a first diode-connected P-channel MOS transistor, and of a second constant current source; a second branch, parallel to the first branch, comprising a series connection of a second N-channel MOS transistor connected as a current mirror on the first N-channel MOS transistor and of a second P-channel MOS transistor connected as a current mirror on the first P-channel transistor; and an input terminal connected between the first N-channel and P-channel transistors and an output terminal connected between the second N-channel and P-channel transistors.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: May 22, 2012
    Assignee: STMicroelectronics (Crolles2) SAS
    Inventor: Hubert Degoirat
  • Publication number: 20120112838
    Abstract: The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 10, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Masatoshi HASE, Masahiro ITO, Takashi SOGA, Satoshi TANAKA
  • Patent number: 8174320
    Abstract: A current switching system is described. This system includes first and second mirrored devices coupled to each other and a coupled terminal, and the first and second mirrored devices are coupled to an input terminal and an output terminal; a storage element in element in parallel with the first mirrored device and the first degeneration device; a variable impedance device coupled between the coupled terminal and a low voltage device; and a current mirroring accuracy enhancing circuit coupled between the coupled terminal and a high voltage device, wherein the variable impedance device dynamically changes a current at the coupled terminal to a second level depending when a threshold is met, and an impedance on the coupled terminal remains low both before switching and during switching.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: May 8, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Rajarshi Mukhopadhyay, Bryan E. Bloodworth, Reza Sharifi, Pankaj Pandey, Taras Dudar
  • Publication number: 20120092073
    Abstract: A trans-impedance amplifier (TIA) for an optical receiver is disclosed, where the TIA stabilizes the cross point in the output thereof independent of the variation of the power supply. The TIA of the invention includes an amplifier section, a source follower, and a bias generator. A transistor in the source follower to define the current flowing in the source follower and another transistor in the bias generator constitute a current-mirror circuit. The operating point of the other transistor in the bias generator depends on the variation of the power supply. The output level of the amplifier section follows the variation of the power supply.
    Type: Application
    Filed: November 2, 2011
    Publication date: April 19, 2012
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Takashi SAWA
  • Publication number: 20120086513
    Abstract: An input stage for an instrumentation system may include a resistor coupled between an input terminal and a summing node, and an amplifier arranged to maintain the voltage at the summing node. In anther embodiment, an instrumentation input system may include an input stage to receive a signal to be measured, and a variable gain amplifier having an input coupled to an output of the input stage, wherein the variable gain amplifier comprises two or more gain stages. A variable gain amplifier may include an attenuator having an input and a series of tap points and a series of low-inertia switches to steer outputs from the attenuator to an output terminal.
    Type: Application
    Filed: December 19, 2011
    Publication date: April 12, 2012
    Applicant: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 8154346
    Abstract: In one embodiment, a method includes: detecting one of a short-to-ground condition and a short-to-supply condition at an output node; selectively activating a feedback control transistor according to the detecting; detecting a first current passing through a first transistor using a second transistor sized to be smaller than the first transistor; mirroring the detected current using a plurality of transistors to form a feedback current; and providing the feedback current to a gate electrode of the first transistor according to the selectively activating the feedback control transistor.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: April 10, 2012
    Assignee: IML International Ltd
    Inventor: Chiayao S. Tung
  • Patent number: 8150073
    Abstract: A semiconductor circuit including an input terminal, an impedance converting portion configured to receive an input signal from the input terminal and to output an output signal corresponding to the input signal, an input impedance of the semiconductor circuit being higher than an output impedance of the semiconductor circuit, a detecting portion connected to a node between the input terminal and the impedance converting portion, and configured to detect whether the input signal is higher than a predetermined threshold, and a variable impedance connected to a reference voltage and the node, an impedance of the variable impedance configured to decrease after the input signal is detected as higher than the predetermined threshold.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: April 3, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Matsumoto, Hiroshi Suzunaga
  • Patent number: 8093952
    Abstract: Aspects of a method and system for precise current matching in deep sub-micron technology may include adjusting a current mirror to compensate for MOSFET gate leakage currents by using feedback circuits. The feedback circuits may be implemented from active components to create active feedback circuits. If the reference current to be mirrored is noisy, a smoothing effect may be achieved by introducing a low-pass filter coupled to the current mirror design. The active feedback may comprise amplifiers, which may comprise one or more amplifier stages. The amplifier may amplify either a bias voltage error or a bias current error. Furthermore, a transimpedance amplifier may be utilized in the feedback loop. The output bias current of the current mirror may be stabilized dynamically during adjusting. Multiple current sources may be utilized in the current mirrors.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: January 10, 2012
    Assignee: Broadcom Corporation
    Inventors: Arya Behzad, Stephen Chi-Wang Au, Dandan Li
  • Patent number: 8072270
    Abstract: Bias circuitry that may be used within a communications or other device includes a first current mirror having first and second transistors with sources coupled to ground and operable to receive a reference current at a drain of first transistor. A second current mirror has first and second transistors with drains coupled to a battery voltage supply. A third current mirror has first and second transistors with drains coupled to sources of the first and second transistors of the second current mirror, respectively. A biasing transistor couples between the second transistor of the first current mirror and the first transistor of the third current mirror and operable to receive a tuning input voltage at its gate. A resistive element coupled between the second transistor of the third current mirror and ground produces a bias voltage produced at a connection of the resistive element and the second transistor of the third current mirror.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: December 6, 2011
    Assignee: Broadcom Corporation
    Inventors: Ali Afsahi, Arya Reza Behzad, Vijay Ramachandra Reddy