Including Current Mirror Amplifier Patents (Class 330/288)
  • Patent number: 6992530
    Abstract: An amplifier having first and second enhancement-mode Field Effect Transistors (FETs) is disclosed. The input port receives an input signal that is to be amplified. The source of the first FET is connected to the input port such that the first FET provides an input impedance match for a signal source connected to the input port. The gate of the second FET is connected to the drain of the first FET such that the second FET amplifies the output signal from the drain of the first FET to provide an amplified input signal. The first and second FETs form a current mirror. An output circuit provides a predetermined output impedance at an output port for coupling the amplified input signal to a circuit that is external to the amplifier. In one embodiment of the invention, the output circuit includes a third FET connected as a source follower with the second FET.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: January 31, 2006
    Assignee: Agilent Technologies, Inc.
    Inventor: Yut Hoong Chow
  • Patent number: 6982602
    Abstract: A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.
    Type: Grant
    Filed: October 7, 2003
    Date of Patent: January 3, 2006
    Assignee: Broadcom Corporation
    Inventor: Lawrence M. Burns
  • Patent number: 6982601
    Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: January 3, 2006
    Assignee: Dialog Semiconductor GmbH
    Inventor: Andreas Sibrai
  • Patent number: 6977549
    Abstract: A differential circuit and an amplifier circuit for reducing an amplitude difference deviation, performing a full-range drive, and consuming less power are disclosed. The circuit includes a first pair of p-type transistors and a second pair of n-type transistors. A first current source and a first switch are connected in parallel between the sources of the first pair of transistors, which are tied together, and a power supply VDD. A second current source and a second switch are connected in parallel between the sources of the second pair of transistors, which are tied together, and a power supply VSS. The circuit further includes connection changeover means that performs the changeover of first and second pairs between a differential pair that receives differential input voltages and a current mirror pair that is the load of the differential pair. When one of the two pairs is the differential pair, the other is the current mirror pair.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: December 20, 2005
    Assignee: NEC Corporation
    Inventor: Hiroshi Tsuchi
  • Patent number: 6977553
    Abstract: An LNA comprising an input stage to amplify an input signal. The input stage has a high linear transconductance that has reduced gain variations in response to changes in process and environmental conditions.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: December 20, 2005
    Assignee: Marvell International Ltd.
    Inventors: Xiaodong Jin, Lawrence Tse, King Chun Tsai, George Chien
  • Patent number: 6967535
    Abstract: A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: November 22, 2005
    Assignees: Renesas Technology Corp., Hitachi Communication Systems, Inc.
    Inventors: Kouichi Matsushita, Tomio Furuya, Fuminori Morisawa, Takayuki Tsutsui, Nobuhiro Matsudaira
  • Patent number: 6954107
    Abstract: An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide additional signal boost at a specified input frequency. An additional input transistor may be added to provide a stepped amplification over the frequency range. The amplifier is further able to reject common mode signals by using regulating transistors.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: October 11, 2005
    Assignee: LSI Logic Corporation
    Inventor: Kenneth G. Richardson
  • Patent number: 6927609
    Abstract: A current-mode data receiving device with sufficient fidelity for a display system. The receiving device includes: a current mirror, where an input current signal and a feedback current signal is received at a first terminal thereof and an output current signal with a current magnitude proportional to (e.g., equal to) the sum of the magnitudes of the input current signal and of the feedback current signal is output through a second terminal thereof; and a feedback unit that uses the magnitude of the output current signal as feedback to determined the magnitude and direction of the feedback current to the first terminal, and causes a decreases in the magnitude of the output current signal by a predetermined amount if the output current signal is at a high level, and increases the current magnitude of the output current signal by the predetermined amount if the magnitude of the output current signal is at a low level.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: August 9, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Il-kwon Chang, Yong-weon Jeon, Ji-woon Jung
  • Patent number: 6922107
    Abstract: An RF amplifier comprises a power amplifier and a dual bias circuit. A dual bias circuit comprises a constant current source and a constant voltage source for biasing the power amplifier. The power may include a heterojunction bipolar transistor (HBT) or a bipolar junction transistor (BJT).
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 26, 2005
    Assignee: Dynalinear Technologies, Inc.
    Inventor: Ron Green
  • Patent number: 6911866
    Abstract: The invention provides a method for amplification of analog push-pull signals (101a, 101b) by means of a push-pull amplifier output stage (100) which has a first output stage transistor (102a) and a second output stage transistor (102b), with first and second analog push-pull signals (101a, 101b) being applied to the first and second output stage transistors (102a, 102b) and to first and second control transistors (103a, 103b), by which means first and second control currents (104a, 104b) are controlled, furthermore with the second control current (104b) which is controlled by the second control transistor (103b) being mirrored by means of a current mirror device (105) into a mirrored second control current (104c), with the first control current (104a) being compared with a first reference current, with the mirrored second control current (104c) being compared with a second reference current, with reference voltage levels (107a, 107b) which are produced by the comparison processes being logically linked in an
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: June 28, 2005
    Assignee: Infineon Technologies AG
    Inventor: Holger Wenske
  • Patent number: 6885247
    Abstract: A current amplifier comprising an amplifier circuit with overall negative feedback and an output current amplification circuit. In one embodiment, a photodiode provides a current to be amplified and the amplifier circuit and the output current amplification circuit are implemented using MOS technology.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 26, 2005
    Assignee: STMicroelectronics, Inc.
    Inventor: Michael J. Callahan, Jr.
  • Patent number: 6876233
    Abstract: Methods and apparatus are provided for separating DC and AC components of a composite signal Is=Idc+Iac from a current source, e.g., a photodiode current source. Four current mirrors CM-1 . . . CM-4 are used with common branches and overlap. CM-1 through CM-3 mirror Is and CM-4 mirrors Idc where lac has been removed by a frequency selective branch. Outputs of the Cm-3 and Cm-4 are combined at a node to provide a signal proportional substantially only to Iac. Complementary devices are used where Cm-1 and Cm-4 are of one type and Cm-2 and Cm-3 are of opposite type. The arrangement allows detection of AC signals (e.g., pulses) that are orders of magnitude smaller than the DC background. An I-to-V converter with a large feedback resistance is used at the output to produce a comparatively large voltage output proportional to lac.
    Type: Grant
    Filed: February 15, 2003
    Date of Patent: April 5, 2005
    Assignee: Medtronics, Inc.
    Inventor: Peter S. Bernardson
  • Patent number: 6867652
    Abstract: An amplifier (10?) has a first amplifier stage (14) for producing a control current (IX) in response to an input voltage. A second amplifier stage (16) has first (46) and second (38) transistors. The first transistor (46) is coupled to receive the control current (IX) and is operable to produce a control voltage. The second transistor (38) is coupled to receive the control voltage and operable to produce an output current. A nonlinear resistive element (50) is coupled to the first transistor (46) to add a nonlinear function of the control current (IX) to the control voltage. The nonlinear resistive element (50) may include a third transistor connected between the first transistor (46) and a reference potential, operable to receive the control current (IX) and to generate the nonlinear function thereof.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: March 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Roy Alan Hastings, Lemuel Herbert Thompson II
  • Patent number: 6864748
    Abstract: An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide additional signal boost at a specified input frequency. An additional input transistor may be added to provide a stepped amplification over the frequency range. The amplifier is further able to reject common mode signals by using regulating transistors.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: March 8, 2005
    Assignee: LSI Logic Corporation
    Inventor: Kenneth G. Richardson
  • Patent number: 6842075
    Abstract: A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains the mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit. In a preferred embodiment, the biased transistor is concurrently in both a Darlington and the current mirror configuration. Moreover, a feedback transistor in the feedback circuit is also concurrently in the Darlington configuration, thus providing an efficient biasing arrangement for an amplifier block based on the Darlington arrangement.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: January 11, 2005
    Assignee: Anadigics, Inc.
    Inventors: Douglas M. Johnson, Henry Z. Liwinski
  • Publication number: 20040263256
    Abstract: A high frequency power amplifier electronic component (RF power module) is so constituted as to apply bias to an amplifier FET in current mirror configuration. In this RF power module, deviation of a bias point due to the short channel effect of the FET is corrected, and variation in high frequency power amplifier characteristics reduced. The high frequency power amplifier circuit (RF power module) is so constituted that the bias voltage for the amplifier transistor in a high frequency power amplifier circuit is supplied from a bias transistor connected with the amplifier transistor in current mirror configuration. In addition to a pad (external terminal) connected with the control terminal of the amplifier transistor, a second pad is provided which is connected with the control terminal of the bias transistor connected with the amplifier transistor in current mirror configuration.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 30, 2004
    Inventors: Makoto Ishikawa, Hirokazu Tsurumaki, Masahiro Kikuchi, Hiroyuki Nagai
  • Patent number: 6831518
    Abstract: The present invention provides improved techniques for controlling current flow in an amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a full range of voltage output to drive an LCD display without necessitating a full range amplifier configuration. Further, many specific embodiments can be realized in smaller space on an IC chip than in conventional technologies.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: December 14, 2004
    Assignee: Winbond Electronics Corporation
    Inventors: Tim Blankenship, Stephen Bily
  • Patent number: 6831517
    Abstract: A system (100) and method (200) for adaptively managing bias of an RF power amplifier (102) is provided. The system (100) incorporates a controller (116) configured to select a radio operating mode. A current-mirror circuit (114) is coupled to the controller (116) and configured to produce a reference current (IRef) as a function of the radio operating mode. A bias regulator (104) is coupled to the controller (116) and the current-mirror circuit (114) and configured to produce a driver-stage bias current (Ib1) and an output-stage bias current (Ib2) for the power amplifier (102) in response to the reference current (IRef). The system (100) also incorporates a DC-to-DC converter (118) coupled to the controller (116) and configured to provide a supply voltage (Vcc) for the power amplifier (102) in response to the radio operating mode. The system (100) also incorporates an envelope detector (120) configured to produce an envelope current (IEnv) in response to an RF input signal (126).
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: December 14, 2004
    Assignee: Intersil Americas, Inc.
    Inventors: David J. Hedberg, James B. Turner
  • Patent number: 6819182
    Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: November 16, 2004
    Assignee: Dialog Semiconductor GmbH
    Inventor: Andreas Sibrai
  • Patent number: 6816014
    Abstract: A low quiescent power class AB current mirror circuit includes a first input transistor for receiving an input current and a second output transistor for providing an output current; the first and second transistors having bases connected together; and a first current supply for sinking current from the bases in response to a decrease in input current to lower the quiescent point of the transistors.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: November 9, 2004
    Assignee: Analog Devices, Inc.
    Inventors: David Hall Whitney, Chau Cuong Tran
  • Patent number: 6809590
    Abstract: An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP2 is mirrored by the output current source IOUT that is desired to be increased. Without positive feedback, the gate of MN2 would be fixed by MP1 and MN1, and when input voltage VIN decreases by an incremental voltage &Dgr;V, the resulting current increase would distribute an increased voltage not only across MP2's VGS but also in the VGS of another transistor MN2; therefore, undesirably, not all of the &Dgr;V voltage change is mirrored in IOUT. However, if positive feedback such as MP5 is provided, the feedback dynamically increases the voltage at the gate of MN2. The increased voltage of MN2's gate essentially provides more voltage “headroom” for MP2 and MN2, and allows current through MP2 to increase with any voltage decrease in VIN.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: October 26, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Kae Wong, Xiaoyu Xi
  • Patent number: 6809616
    Abstract: An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: October 26, 2004
    Assignee: Richtex Technology Corp.
    Inventors: Jing-Meng Liu, Kent Hwang, Chao-Hsuan Chuang, Cheng-Hsuan Fan
  • Patent number: 6803808
    Abstract: A current mirror circuit is provided. The circuit includes a resistor having a first terminal connected to a current source, a first transistor having a substrate electrode connected to a drain electrode thereof, a second transistor having a substrate electrode connected to the substrate electrode of the first transistor, a third transistor having a substrate electrode connected to the substrate electrode of the first transistor, and a fourth transistor having a drain electrode for providing an output current.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: October 12, 2004
    Assignee: Winbond Electronics Corp.
    Inventor: Li-Te Wu
  • Patent number: 6803821
    Abstract: A switchable amplifier circuit having a current mirror. The mirror includes: a first current source for producing a reference current; an output transistor having an input electrode and an output electrode; and a current gain device connected between an output of the first current source and the input electrode of the output transistor. A bias current is produced through the output electrode of the output transistor, such bias current being a function of the reference current produced by the first current source. A second current source has an output coupled to an input of the current gain device. The second current source provides a current which is a fraction of the reference current. A switching transistor has an output electrode coupled to: (1) an input of the current gain device; and, (2) an output of the second current source.
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: October 12, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John A. DeFalco, Mikhail S. Shirokov
  • Publication number: 20040196104
    Abstract: An amplifier having first and second enhancement-mode Field Effect Transistors (FETs) is disclosed. The input port receives an input signal that is to be amplified. The source of the first FET is connected to the input port such that the first FET provides an input impedance match for a signal source connected to the input port. The gate of the second FET is connected to the drain of the first FET such that the second FET amplifies the output signal from the drain of the first FET to provide an amplified input signal. The first and second FETs form a current mirror. An output circuit provides a predetermined output impedance at an output port for coupling the amplified input signal to a circuit that is external to the amplifier. In one embodiment of the invention, the output circuit includes a third FET connected as a source follower with the second FET.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventor: Yut Hoong Chow
  • Publication number: 20040196103
    Abstract: A switchable amplifier circuit having a current mirror. The mirror includes: a first current source for producing a reference current; an output transistor having an input electrode and an output electrode; and a current gain device connected between an output of the first current source and the input electrode of the output transistor. A bias current is produced through the output electrode of the output transistor, such bias current being a function of the reference current produced by the first current source. A second current source has an output coupled to an input of the current gain device. The second current source provides a current which is a fraction of the reference current. A switching transistor has an output electrode coupled to: (1) an input of the current gain device; and, (2) an output of the second current source.
    Type: Application
    Filed: April 3, 2003
    Publication date: October 7, 2004
    Inventors: John A. DeFalco, Mikhail S. Shirokov
  • Patent number: 6784745
    Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: August 31, 2004
    Assignee: LSI Logic Corporation
    Inventor: Kenneth G. Richardson
  • Patent number: 6778016
    Abstract: A self-biased cascade amplifier circuit includes first and second transistors connected in series and coupled between a dc voltage source terminal and a common terminal. An input signal terminal is coupled to a control electrode of the first transistor, and an output signal terminal is coupled to an output terminal of the second transistor. An integrated bias circuit is coupled between the dc voltage source terminal and the common terminal for internally biasing both the first and the second transistors without the use of an external bias supply or a direct bias connection to the dc voltage source. This arrangement provides a fully self-biased cascode amplifier circuit having improved performance and a simple and compact configuration.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: August 17, 2004
    Assignee: Koninklijke Philips Eletronics N.V.
    Inventor: Sifen Luo
  • Patent number: 6774882
    Abstract: There is provided a thin film transistor circuit used for a driver circuit for providing a semiconductor display device without a picture blur and with high fineness/high resolution. In the thin film transistor circuit, a TFT having a large size (channel width) is not used, but a plurality of TFTs each having a small size are connected in parallel to each other and are used. By this, while sufficient current capacity of the thin film transistors is secured, fluctuation in the characteristics can be decreased.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: August 10, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 6774723
    Abstract: A circuit for matching a first mirror transistor with a second mirror transistor in a current mirror includes a bias transistor and a diode connected transistor to match such mirror transistors. More particularly, the circuit is a part of an amplifier having an output with a quiescent voltage and at least one rail voltage. The first mirror transistor has a first terminal coupled to the output and a second terminal coupled to the at least one rail voltage. To effectuate its mirroring function, the bias transistor is coupled to a first terminal of the second mirror transistor, and the diode connected transistor is coupled to both a second terminal of the second mirror transistor and the at least one rail voltage. The bias transistor has a terminal with a quiescent voltage that is substantially equal to the quiescent voltage of the output.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 10, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Faramarz Sabouri
  • Patent number: 6774726
    Abstract: An amplifier including first, second, and third series-connected stages, the third stage including a MOS output transistor having its source or drain forming an output terminal of the amplifier, including means for detecting the transition from a first operating state of the output transistor in which the drain current varies little with the voltage between the drain and the source to a second state in which the drain current varies substantially proportionally to the voltage between the drain and the source; and means for, upon detection of such a transition, having the voltage gain of the amplifier and/or the product between the bandwidth of the amplifier and the voltage gain of the amplifier at the upper limit frequency of the bandwidth drop.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 10, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Frédéric Goutti, Vincent Rabary
  • Publication number: 20040150478
    Abstract: A current amplifier has a variable resistor or capacitor to provide a high frequency boost. Additionally, additional transistors may be switched in and out of the circuit to provide different gains at lower frequency. The combination of variable resistors or capacitors and the switchable transistors provides control over the low frequency gain of the amplifier and the transition region from low gain to higher gain.
    Type: Application
    Filed: January 31, 2003
    Publication date: August 5, 2004
    Inventor: Kenneth G. Richardson
  • Publication number: 20040130395
    Abstract: The present invention provides improved techniques for controlling current flow in an amplifier circuit. Specific embodiments provide steering of analog outputs of digital to analog converters in order to drive columns of an LCD display. Embodiments can provide a full range of voltage output to drive an LCD display without necessitating a full range amplifier configuration. Further, many specific embodiments can be realized in smaller space on an IC chip than in conventional technologies.
    Type: Application
    Filed: October 6, 2003
    Publication date: July 8, 2004
    Applicant: Winbond Electronics Corporation
    Inventors: Tim Blankenship, Stephen Bily
  • Patent number: 6756850
    Abstract: A module including a bias circuit that generates gate bias voltages by resistance dividers creates a problem in that the values of the resistances constituting the bias circuit must be finely adjusted, and accordingly extra trimming tasks are required. The present invention provides current generators that generate currents varying with desired characteristics responsive to a control voltage, independent of variations in transistor threshold voltages, connects output resistors to parallel transistors in respective stages to form current mirror circuits, and supplies currents from the current generators thereto to drive them, instead of supplying dividing voltages.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: June 29, 2004
    Assignees: Renesas Technology Corp., Hitachi Communication Systems, Inc.
    Inventors: Kouichi Matsushita, Tomio Furuya, Fuminori Morisawa, Takayuki Tsutsui, Nobuhiro Matsudaira
  • Patent number: 6753734
    Abstract: There is disclosed a bias circuit exhibiting good stability over variations in temperature and power supply voltage and capable of generating a plurality of discrete levels of output current for biasing RF power amplifier. In accordance with the invention, the bias circuit includes (1) a master transistor connected to the slave transistor in a current-mirror configuration and having two parallel-connected transistor elements, (2) a switch connected to at least one transistor element to control its operation, and (3) a feedback circuit by which the voltage at the collector of the master transistor may be fed back to control the voltages at the bases of the master transistor and the slave transistor. Moreover, the bias circuit can be operated from a power supply voltage that is just above twice the value of the base-emitter voltage of the transistor in the circuit.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: June 22, 2004
    Assignee: Anadigics, Inc.
    Inventors: Thomas W. Arell, Henry Z. Liwinski
  • Patent number: 6750720
    Abstract: Between resistors 13, 14 and an NPN bipolar transistor 12 are interposed PNP bipolar transistors 21, 22 forming a current mirror 20 that uses a collector current of the NPN bipolar transistor 12 as a reference current, and determines a collector current of an NPN bipolar transistor 11. This makes possible to design a size ratio A of the PNP bipolar transistors 21, 22 so as to approximate a voltage drop &Dgr;Vb to a value close to zero, and to suppress the voltage drop &Dgr;Vb of the base voltage Vb accordingly to achieve a high power output and high efficiency when a high frequency input signal Pin increases and generates a base rectified current.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: June 15, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazutomi Mori, Shintarou Shinjo, Hiroyuki Joba, Yoshinori Takahashi, Yukio Ikeda, Tadashi Takagi
  • Patent number: 6747516
    Abstract: A power controller circuit for a power amplifier stage includes an exponential power control circuit responsive to a power control signal for providing an exponential control current to control power amplifier stage and linear power control circuit responsive to the power control signal for supplementing the exponential control current to the power amplifier stage with a linear control current to produce a composite control current with a reduced and extended slope.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: June 8, 2004
    Assignee: Analog Devices, Inc.
    Inventors: Shuyun Zhang, Robert Jeffery McMorrow
  • Patent number: 6747510
    Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: June 8, 2004
    Assignee: Broadcom Corporation
    Inventors: Stephen A. Jantzi, Anilkumar V. Tammineedi, Jungwoo Song, Lawrence M. Burns, Donald G. McMullin, Agnes N. Woo
  • Publication number: 20040090272
    Abstract: A method and circuits of a high isolation and high-speed buffer amplifier capable to handle frequencies in the GHz range have been achieved. The output to input isolation is primary dependent on the gate-source capacitance of the active buffer transistor. Having two or more in series and by reducing the impedance between them a high isolation can be achieved. The input signals are split in several signal paths and are amplified in the push-pull mode using source follower amplifiers. Then the amplified signals are being combined again. The amplified output current is mirrored applying a multiplication factor. Said method and technology can be used for buffer amplifiers having differential input and differential output or having single input and single output or having differential input and single output. A high reversed biased (output to input) isolation and a reduced quiescent current have been achieved.
    Type: Application
    Filed: November 26, 2002
    Publication date: May 13, 2004
    Applicant: Dialog Semiconductor GmbH.
    Inventor: Andreas Sibrai
  • Patent number: 6734720
    Abstract: A high slew rate operational amplifier circuit of which the through current of its push-pull transistors is substantially zero is disclosed. The operational amplifier circuit preferably comprises an amplifier portion and a push-pull output amplifier including NPN and PNP output transistors. The output of the amplifier portion is transferred to the NPN output transistors base through a PNP driving transistor and to the PNP output transistors base through an NPN driving transistor. The emitters of the driving transistors are connected to respective power supply conductors through respective current sources. The through current reduction is achieved by resistors inserted between the current sources and the corresponding power supply conductors, an NPN transistor so connected with the NPN output transistor as to constitute a current mirror and a PNP transistor so connected with the PNP output transistor as to constitute another current mirror.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: May 11, 2004
    Assignee: Denso Corporation
    Inventors: Hiroshi Imai, Takeshi Miki
  • Publication number: 20040085130
    Abstract: A self-biased cascade amplifier circuit includes first and second transistors connected in series and coupled between a dc voltage source terminal and a common terminal. An input signal terminal is coupled to a control electrode of the first transistor, and an output signal terminal is coupled to an output terminal of the second transistor. An integrated bias circuit is coupled between the dc voltage source terminal and the common terminal for internally biasing both the first and the second transistors without the use of an external bias supply or a direct bias connection to the dc voltage source. This arrangement provides a fully self-biased cascode amplifier circuit having improved performance and a simple and compact configuration.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Sifen Luo
  • Patent number: 6731164
    Abstract: Various methods and apparatuses that multiply the effects of feedback current on an amplifier. In an embodiment, a buffer circuit controls the transition rate on an output pad of the buffer circuit. An amplifier has an input terminal and an output terminal. The output terminal couples to the output pad. A feedback component couples feedback current from the output pad to the input terminal. A current mirror multiplies the effects of the feedback current on the input terminal without increasing the feedback current through the feedback component.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventor: Robert James Johnston
  • Patent number: 6727758
    Abstract: A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 27, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Alok Govil
  • Patent number: 6728494
    Abstract: A digital electrical signal Vin for transmission is supplied to a transistor Q12, a current compensation circuit 11, and a signal current source 13 to be band-compensated for generating a signal current I0. A predetermined current Id for a constant-current source 14 is subtracted from the signal current I0, and the result is an injection current Iin that drives an LED 15. The current Id is adjusted so that the injection current Iin becomes 0 at the low level. Thus, a signal-to-noise (S/N) ratio in waveform of light outputted from the LED 15 can be improved. Accordingly, the S/N ratio of the transmitted signal can be improved with band compensation.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: April 27, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazunori Numata, Satoshi Furusawa, Susumu Morikura
  • Patent number: 6724260
    Abstract: A low power current feedback amplifier having a lower output impedance input stage is provided. To reduce the output impedance, an input stage comprises a closed-loop input buffer. An exemplary input buffer comprises a closed-loop current feedback amplifier configured within the overall current feedback amplifier, wherein the output of the input buffer corresponds to the inverting node of the overall current feedback amplifier. The closed-loop configuration of the input buffer is facilitated by the use of an internal feedback resistor coupled from an inverting input terminal of the input buffer to the output of the input buffer, which corresponds to the inverting input terminal of the overall current feedback amplifier. The closed-loop input buffer realizes a low output impedance since the loop gain reduces the output impedance of the input buffer. With a lower output impedance, the bandwidth of the current feedback amplifier becomes more independent of the gain, even at low current implementations.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: April 20, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Alan Lee Varner, Ahmad Dashtestani, Joel M. Halbert, Michael A. Steffes
  • Patent number: 6720817
    Abstract: Two variations of a continuous-time instantaneous companding filter are integrated in a 25 GHz bipolar process. Their −3 dB frequencies are tunable in the ranges of 1-30 MHz and 30-100 MHz. The dc gains are controllable up to 10 dB. The measured dynamic ranges for a 1% total harmonic distorsion are 62.5 dB and 50 dB, for the 30 MHz and 100 MHz filters respectively. At maximum cutoff frequencies, the filters dissipate 6.5 mW from a 1.2 V supply. The filters are simple, common-mode interference-resistant, class AB log-domain integrators, suitable for implementation in low-cost bipolar processes. They are suitable for realizing low-voltage filters with reasonable linearity and signal-to-noise ratio. ALL-NPN low distortion input and output interface stages can be added to the integrators. The filters can be used to realized high-frequency programmable filters.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: April 13, 2004
    Assignee: McGill University
    Inventor: Mourad N. El-Gamal
  • Patent number: 6713749
    Abstract: A Loss Of Signal (LOS) circuit in an opto-electronic receiver circuit. The LOS circuit includes a current to voltage converter and a comparator circuit. The current to voltage circuit receives a current signal including a DC current signal component from a photodetector circuit included in the opto-electronic receiver. The current to voltage receiver generates a voltage signal in response to the DC current signal. The comparator circuit receives the voltage signal from the current to voltage circuit and generates a LOS signal from the voltage signal by comparing the voltage signal to a reference voltage signal.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: March 30, 2004
    Assignee: Vitesse Semiconductor Corporation
    Inventors: Adam A. Wu, Balagopal Mayampurath
  • Patent number: 6714081
    Abstract: An active current bias network that compensates for Hot-Carrier Injection (HCI) induced bias drift, a common phenomenon existing in Metal-Oxide Semiconductor (MOS) transistors and especially in Laterally Diffused MOS (LDMOS) transistors. The active bias network of the present invention first senses the bias current flowing in the targeted transistor and then compares the bias current in the targeted transistor with a stable reference current. The difference between the bias current in the targeted transistor and the reference current is then utilized to adjust the bias of the targeted transistor via a current mirror feedback circuit. The bias current of the targeted transistor then is stable independent of any HCI induced bias changes and changes due to other adverse causes. The sensing MOS transistor used for monitoring bias current is operated in the triode region and has minimum effect on the performance of the targeted transistor.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: March 30, 2004
    Assignee: Motorola, Inc.
    Inventor: Jie Xu
  • Patent number: 6714080
    Abstract: A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: March 30, 2004
    Assignee: Broadcom Corporation
    Inventor: Lawrence M. Burns
  • Patent number: 6714076
    Abstract: An op amp includes a pair of buffer amplifiers interposed between the current switch and the output transistors in an output stage based on the Monticelli architecture. The buffer amps buffer the output transistors' gate capacitances, thereby allowing the output transistors to be nearly any desired size without adversely affecting the op amp's dynamic performance. This enables the op amp's compensation capacitors to set the amplifier's bandwidth, and allows the secondary pole to be at a higher frequency. The buffer amplifiers can also provide gain which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location. In addition, the buffer amplifiers can be used to provide voltage level translation between the current switch and output transistors, which can provide additional headroom for the op amp's gain stage.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: March 30, 2004
    Assignee: Analog Devices, Inc.
    Inventor: Arthur J. Kalb