Including Plural Amplifier Channels Patents (Class 330/295)
  • Patent number: 8860509
    Abstract: A clipping circuit includes: a first input terminal which receives a first signal, a second input terminal which receives a second signal, and a first variable resistive element which has a control terminal electrically connected to the second input terminal and which has a threshold, wherein first and second ends of the first variable resistive element are connected to first input terminal and a reference voltage, respectively. The clipping circuit also includes a second variable resistive element which has a control terminal electrically connected to the first input terminal and which has a threshold, wherein first and second ends of the second variable resistive element are connected to a second input terminal and the reference voltage, respectively.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kohei Onizuka
  • Patent number: 8861748
    Abstract: Disclosed is a class D amplifier comprising a modulation stage having a first input for receiving an input signal and an output for producing a modulated version of the input signal; a plurality of power stages, each power stage being responsive to said modulation stage and comprising a first switch and a second switch coupled in series between a first voltage source and a second voltage source, each power stage comprising an output node between the first switch and the second switch; and a power stage control circuit for measuring the input signal level and enabling a selected number of the power stages as a function of the measured input signal level. A method for controlling such a class D amplifier is also disclosed.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: October 14, 2014
    Assignee: NXP B.V.
    Inventors: Lutsen Ludgerus Albertus Hendrikus Dooper, Marco Berkhout, Wilfred Repko
  • Patent number: 8860510
    Abstract: An amplification stage comprising: a combiner to generate a sum input signal by combining a voltage signal with a DC bias voltage; a subtractor to generate a difference input signal by subtracting the voltage signal from the DC bias voltage; a first transistor for generating a first part of an amplifier output signal from the sum input signal; a second transistor for generating a second part of an amplifier output signal from the difference input signal; a combiner for combining the first and second parts of the amplifier output signal; a sensing circuit arranged to sense a current flowing in each of the first and second transistors; a control circuit arranged to determine the quiescent current of the first and second transistors in dependence on the sensed currents; and an adjustment circuit arranged to adjust the DC bias voltage in order to minimize variation in the quiescent current.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: October 14, 2014
    Assignee: Nujira Limited
    Inventor: Gerard Wimpenny
  • Publication number: 20140295781
    Abstract: A power amplifier, includes: a first and a second amplifier circuits that are controlled so that one of them do not amplify a signal when another one of them amplifies the signal; a first impedance conversion circuit, coupled between the first amplifier circuit and the output terminal, that converts an output impedance of the first amplifier circuit; a second impedance conversion circuit, coupled between the second amplifier circuit and a wiring coupling the first impedance conversion circuit and the output terminal, that converts an output impedance of the second amplifier circuit; and a connection circuit that, when the first amplifier circuit amplifies the signal, forms a path which bypasses the second impedance conversion circuit between a reference potential and the wiring coupling the first impedance conversion circuit and the output terminal, by coupling a wiring coupling the first amplifier circuit and the output terminal, with the reference potential.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Yoichi KAWANO
  • Publication number: 20140292414
    Abstract: A multipath power amplifier device, configured to operate in a high power mode and a low power mode, includes a high power path, a low power path and an output switch. The high power path includes a high power mode (HPM) amplifying circuit for amplifying an input signal in the high power mode. The low power path includes a low power mode (LPM) amplifying circuit for amplifying the input signal in the low power mode. The output switch is configured to isolate the low power path from the high power path in the high power mode.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 2, 2014
    Inventor: Avago Technologies General IP (Singapore) Pte. Ltd.
  • Patent number: 8847687
    Abstract: An amplifier device having an extended bandwidth includes a DC coupled amplifier and multiple low noise amplifiers connected in series with one another and connected in parallel with at least a portion of the DC coupled amplifier. The DC coupled amplifier has a broad bandwidth, and each of the low noise amplifiers has a narrow bandwidth and a center frequency higher than a high end frequency of the broad bandwidth of the DC coupled amplifier. The extended bandwidth of the amplifier device is a combination of the broad bandwidth and the first narrow bandwidth.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: September 30, 2014
    Assignee: Agilent Technologies, Inc.
    Inventor: Keith C. Griggs
  • Patent number: 8847680
    Abstract: Amplifier units and methods of use are described herein. A amplifier unit includes a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: September 30, 2014
    Assignee: Apple Inc.
    Inventors: Gregory Bowles, Martin O'Flaherty, Scott Widdowson, John Ilowski
  • Publication number: 20140285267
    Abstract: In a portable radio transceiver, a power amplifier system includes a saturation detector that detects power amplifier saturation in response to duty cycle of the amplifier transistor collector voltage waveform. The saturation detection output signal can be used by a power control circuit to back off or reduce the amplification level of the power amplifier to avoid power amplifier control loop saturation.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 25, 2014
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Paul Raymond Andrys, Michael Lynn Gerard, Terrence John Shie
  • Publication number: 20140266460
    Abstract: A scalable periphery tunable matching power amplifier is presented. Varying power levels can be accommodated by selectively activating or deactivating unit cells of which the scalable periphery tunable matching power amplifier is comprised. Tunable matching allows individual unit cells to see a constant output impedance, reducing need for transforming a low impedance up to a system impedance and attendant power loss. The scalable periphery tunable matching power amplifier can also be tuned for different operating conditions such as different frequencies of operation or different modes.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: PEREGRINE SEMICONDUCTOR CORPORATION
    Inventors: Dan William Nobbe, David Halchin, Jeffrey A. Dykstra, Michael P. Gaynor, David Kovac, Kelly Michael Mekechuk, Gary Frederick Kaatz, Chris Olson
  • Publication number: 20140266463
    Abstract: The invention relates to an amplifier arrangement for high-frequency signals. Said amplifier arrangement comprises a signal input (IN) for receiving high-frequency signals (RFin) that are to be amplified, a first amplifier device (Mn1, Mn2) that amplifies the high-frequency signals that are to be amplified, the first amplifier device having a drain circuit, a source follower circuit or a similar device, an additional amplifier device (GB; Mn3, Mn4, Mn5, M6) which is arranged in parallel to the first amplifier device (Mn1, Mn22) and amplifies the high-frequency signals that are to be amplified, and a signal output (OUT) for outputting the high-frequency signals (RFout) amplified by the first and the additional amplifier device (GB; Mn3, Mn4, Mn5, Mn6).
    Type: Application
    Filed: April 20, 2012
    Publication date: September 18, 2014
    Applicant: RWTH AACHEN
    Inventors: Ahmed Aref, Renato Negra
  • Publication number: 20140266462
    Abstract: An adaptive power amplifier that may be used in a wireless communication device is configured to adjust its load line or output impedance, the number of active amplifier cells in each amplification stage, the bias of the active amplifiers, and the supply voltage input capacitive load in accordance with a supply voltage modulation type provided to the power amplifier. The supply voltage modulation types include ET, APT, DC-DC, dual, multi-state or fixed voltage supply voltages. A supply voltage converter, signaled by a baseband processor, generates the selected type of supply voltage modulation for the adaptive power amplifier. The baseband processor may also provide a control interface signal to a controller within the adaptive power amplifier.
    Type: Application
    Filed: December 17, 2013
    Publication date: September 18, 2014
    Applicant: MOTOROLA MOBILITY LLC
    Inventors: Ernest Schirmann, Ryan J. Goedken, Armin W. Klomsdorf, Thomas D. Nagode
  • Publication number: 20140266464
    Abstract: Apparatus and method embodiments are provided for improving power efficiency in an outphasing amplifier with a non-isolating combiner. The embodiments include reducing the driving power to two power amplifiers (PAs) of the amplifier circuit in the low input signal power region in an asymmetric manner between the two PAs. An embodiment method includes receiving, at a signal decomposer, an input signal, detecting a power amplitude of the input signal, and determining whether the input signal corresponds to one of a plurality of operation modes according to the detected power amplitude of the input signal and a plurality of power thresholds corresponding to the operation modes. Upon determining that the power amplitude of the input signal corresponds to a first mode from the operation modes, the input signal is decomposed into two component signals including at least one signal that has a reduced and scaled amplitude proportional to the input signal.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 18, 2014
    Applicant: FutureWei Technologies, Inc.
    Inventors: Zhengxiang Ma, Ruikang Yang, Munawar Kermalli
  • Publication number: 20140266461
    Abstract: Split amplifiers with configurable gain and linearization circuitry are disclosed. In an exemplary design, an apparatus includes first and second amplifier circuits and a linearization circuit, which may be part of an amplifier. The first and second amplifier circuits are coupled in parallel and to an amplifier input. The linearization circuit is also coupled to the amplifier input. The first and second amplifier circuits are enabled in a high-gain mode. One of the first and second amplifier circuits is enabled in a low-gain mode. The linearization circuit is enabled in the second mode and disabled in the first mode. The amplifier is split into multiple sections. Each section includes an amplifier circuit and is a fraction of the amplifier. High linearly may be obtained using one amplifier circuit and the linearization circuit in the low-gain mode.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Ahmed A. Youssef, Li-Chung Chang
  • Publication number: 20140266465
    Abstract: System and method embodiments are provided for a multilevel outphasing amplifier architecture with a non-isolating or lossless combiner. The multilevel outphasing amplifier with lossless combiner improves power efficiency in comparison to outphasing amplifiers with lossless combiners. The multilevel outphasing amplifier applies different voltage levels to the power amplifiers (PAs) of the circuit according to the input signal power range. Additionally, tunable reactive compensation is applied to the compensation components (capacitor and inductor) of the lossless combiner as a function of the multilevel voltage setting of the PAs. The efficiency at the back-off region is improved by varying the compensation elements of the lossless combiner along with the drain voltage to the PAs as a function of the input signal power or amplitude.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: FutureWei Technologies, Inc.
    Inventor: Munawar Kermalli
  • Patent number: 8836421
    Abstract: An output network for use with a multi-transistor amplifier circuit comprises N transistors configured to provide a Chireix outphasing behavior. The N transistors coupled to receive different amplitude and/or phase signals relative to a source signal. The output network comprises: a plurality of branches arranged in a hierarchical structure between N input nodes and an output node; at least one branch connection arranged between the input nodes and the output node, wherein each branch connection is arranged to couple first and second branches from an input side to a single branch on an output side. The hierarchical structure is arranged asymmetrically such that at least one branch connection comprises a different number of input nodes ultimately connected to its first branch compared to the number of input nodes ultimately connected to its second branch.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: September 16, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Richard Hellberg
  • Patent number: 8836430
    Abstract: An improved distributed amplifier (200) includes an input transmission line (201) terminated with an input lead configured to accept an input signal and an output transmission line (202) terminated with an output lead configured to output an output signal. A number of parallel amplifier cells (204N) are connected to the input transmission line (201) and the output transmission line (202) that collectively amplify the input signal from the input lead to produce an amplified output signal at the output lead. A bypass switch (212, 300) is connected to the input and output transmission lines (201, 202). The bypass switch (212, 300) is operative to convert either the input transmission line (201, 301) or the output transmission line (202, 302) into a bypass line configured to bypass the parallel amplifier cells (204N) of the distributed amplifier (200) and provide a direct path between the input and output transmission lines (201, 202) to produce a bypassed output signal at the output lead.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: September 16, 2014
    Assignee: Harris Corporation
    Inventors: Daniel A. Robison, Ronald J. Hash
  • Patent number: 8836431
    Abstract: In a representative embodiment, a multiple mode power amplifier that is operable in a first power mode and a second power mode. The multiple mode power amplifier comprises a first amplifying unit; a second amplifying unit; a first impedance matching network connected to an output port of the first amplifying unit; a second impedance matching network connected to an output port of the second amplifying unit and to the first impedance matching network; and a third impedance matching network connected to the output ports of the first and the second amplifying units. The third impedance matching network reduces a phase difference between signals amplified by the first and the second amplifying units in the first mode.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: September 16, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Choong Soo Han, Jung Min Oh, Sang Hwa Jung
  • Patent number: 8837629
    Abstract: An extended bandwidth digital Doherty transmitter includes a baseband signal processing block including a digital predistortion unit. It also includes a digital signal distribution unit and a digital phase alignment unit, a signal up-conversion block, an RF power amplification block including the carrier amplifier and one or two peaking amplifiers; and an RF Doherty combining network. In another aspect, a digital Doherty transmitter includes a baseband signal block including a digital predistortion unit, a digital signal distribution unit and an adaptive digital phase alignment unit. In this aspect a signal up-conversion block includes three digital-to-analog converters (DACs) and a tri-channel up-converter or three single-channel up-converters. There is also an RF power amplification block including the carrier amplifier and two peaking amplifiers, and an RF Doherty combining network which includes quarter wavelength impedance transformers.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 16, 2014
    Inventors: Fadhel M Ghannouchi, Ramzi Darraji
  • Publication number: 20140253246
    Abstract: The present invention is directed to an amplifier system that includes a main amplifier configured to amplify and a peak amplifier that operates only in a high power mode. An impedance matching network is coupled to at least the peak power amplifier. An impedance transformation device is coupled to at least a portion of the impedance matching network. The impedance transformation device is configured as a balun in the high power mode. The balun includes a first input and second input coupled to the main amplifier and the peak amplifier respectively. The impedance transformation device is configured as an unbalanced line impedance transformer in the low power mode because the predetermined output impedance substantially grounds the second input. The Doherty device is characterized by an impedance transformation ratio of at least 4:1 and a relative bandwidth greater than or equal to 40%.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: Anaren, Inc
    Inventor: Chong Mei
  • Publication number: 20140253247
    Abstract: Certain embodiments provide a power amplifying device including: a distribution line which distributes power; a plurality of power amplifying elements; a connection line; an output line; a filter; a first directional coupler; and a second directional coupler. The power amplifying elements is provided at a stage subsequent to the distribution line. The connection line is provided at a stage subsequent to each of the power amplifying elements and combines outputs of the power amplifying elements. The output line is connected to the connection line. The filter is placed on the connection line or the output line. The first and second directional couplers are provided at a stage subsequent to the filter. The first directional coupler outputs the high frequency signal transmitted to the output line, to a RF monitor terminal. The second directional coupler outputs the high frequency signal transmitted to the output line, to a level detection detector.
    Type: Application
    Filed: November 26, 2013
    Publication date: September 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Akihiro Satomi
  • Publication number: 20140253245
    Abstract: A distributed RF amplifier includes filter circuits to band limit input signal components applied to corresponding amplifiers. Different amplifiers in the distributed amplifier may be band limited to different pass bands. The different pass bands may collectively cover an operational frequency range of the distributed amplifier.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 11, 2014
    Applicant: AURIGA MEASUREMENT SYSTEMS, LLC
    Inventor: Yusuke Tajima
  • Publication number: 20140253248
    Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first series circuit and a second series circuit in parallel with the first series circuit. The first series circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first adjustable attenuator series coupled between the first input and the first output. The second series circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter and a second adjustable attenuator series coupled between the second input and the second output.
    Type: Application
    Filed: May 26, 2014
    Publication date: September 11, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: ABDULRHMAN M.S. AHMED, MARIO M. BOKATIUS, PAUL R. HART, JOSEPH STAUDINGER, RICHARD E. SWEENEY
  • Patent number: 8829998
    Abstract: A Doherty power amplifier including a main amplifier, an auxiliary amplifier and a controller governing the operation of the auxiliary amplifier, the controller being operative to switch the operational state of the auxiliary amplifier between an operational state and a non-operational state as a function of input signal voltage supplied to the power amplifier such that the auxiliary amplifier is inoperative when the input voltage is below an input voltage threshold and is operative when the input voltage is above the input voltage threshold.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Airspan Networks Inc.
    Inventor: Nadav Yanay
  • Patent number: 8824991
    Abstract: A multi-mode power amplifier includes a high-power mode amplifier circuit, a mid-power mode amplifier circuit, and a low power amplifier circuit, where the low-power mode amplifier circuit comprises a plurality of independently selectable power cell/amplifier branches. The multi-mode power amplifiers selectively enable or disable amplifier branches to provide multiple levels of amplification. Selectively enabling certain of a plurality of split collector amplifier branches provides multiple low power and ultra-low power amplifier modes without the impedance mismatch or board layout problems associated with an RF switch.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: September 2, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Shiaw Wen Chang, Xuejun Chen, Guohao Zhang, Jing Sun, Piyou Zhang, Jinim Won
  • Publication number: 20140240047
    Abstract: A digitally-controlled power amplifier (DPA) includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.
    Type: Application
    Filed: May 13, 2014
    Publication date: August 28, 2014
    Applicant: MEDIATEK INC.
    Inventors: Jie-Wei Lai, Meng-Hsiung Hung, Robert Bogdan Staszewski
  • Patent number: 8816771
    Abstract: A signal amplifying circuit includes: an input stage circuit, arranged to receive an input signal; a first inductive device coupled between the input stage circuit and a first reference voltage; an output stage circuit arranged to generate an output signal according to the input signal; and a second inductive device coupled between the output stage circuit and a second reference voltage, wherein at least a part of a winding of the first inductive element is cross-coupled to at least a part of a winding of the second inductive element.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: August 26, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Hsien-Ku Chen, Chia-Jun Chang, Ka-Un Chan, Ying-Hsi Lin
  • Patent number: 8816767
    Abstract: A system and method of calibrating an amplifier are presented. The amplifier has a first amplification path and a second amplification path. A first state of the amplifier is identified defining a first phase shift of the first path and a second phase shift of the second path resulting in a maximum efficiency of the amplifier when an attenuation of the first path and an attenuation of the second path are set to first attenuation values. The attenuation of the first path and the attenuation of the second path is set to achieve a maximum efficiency of the amplifier when the phase shift of the first path and the phase shift of the second path are set according to the first state.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: August 26, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Abdulrhman M. S. Ahmed, Paul R. Hart, Ramanujam Shinidhi Embar
  • Publication number: 20140232469
    Abstract: In general, an RF power amplifier comprises a controller, a driver, a splitter, a final stage, and a combiner coupled together to function as the RF power amplifier. One or more of the above components are arranged on one or more motherboards, e.g., a printed circuit board (PCB). A heat sink defines a base of the RF power amplifier, and in some embodiments includes at least two grooves formed therein, wherein the electrical components of the splitter and electrical components of the controller fit within one or more of the grooves so that these components can substantially disposed within the heat sink. In some embodiments, a power rail is also provided, and is also disposed substantially within the heat sink. The power rail groove of the heat sink and the carrier of the final stage provide an EMI shield of the power rail.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Applicant: EMPOWER RF SYSTEMS, INC.
    Inventors: Paulo CORREA, Donald M. WIKE, Leonid MOGILEVSKY
  • Publication number: 20140232467
    Abstract: A high-frequency amplifier module includes a driver-stage amplifier 3 that amplifies an RF signal input thereto from an RF input terminal 1, and a final-stage amplifier 5 that amplifies the signal amplified by the driver-stage amplifier 3 and outputs the signal after the amplification to an RF output terminal 7. The driver-stage amplifier 3 is fabricated on a silicon substrate 11, while the final-stage amplifier 5 is fabricated on a gallium arsenide substrate. This configuration downsizes the cost while maintaining a high-frequency characteristic comparable to that in the case where all components of an entire module are fabricated on a gallium arsenide substrate 71.
    Type: Application
    Filed: August 24, 2012
    Publication date: August 21, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kenji Mukai, Kenichi Horiguchi, Morishige Hieda, Katsuya Kato, Yoshihito Hirano, Kazuya Yamamoto, Hiroyuki Joba, Teruyuki Shimura
  • Patent number: 8810285
    Abstract: In a semiconductor integrated circuit apparatus and a radio-frequency power amplifier module, a log detection portion including multiple-stage amplifier circuits, multiple level detection circuits, adder circuits, and a linear detection portion including a level detection circuit are provided. Output current from the log detection portion and output current from the linear detection portion are multiplied by different coefficients and the results of the multiplication are added to each other to realize the multiple detection methods. For example, current resulting from multiplication of the output current from the log detection portion by ×6/5 is added to the output current from the linear detection portion to realize a log detection method and, current resulting from multiplication of the output current from the log detection portion by ×? is added to current resulting from multiplication of the output current from the linear detection portion by ×3 to realize a log-linear detection method.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: August 19, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yusuke Shimamune, Yasunobu Yoshizaki, Norio Hayashi, Takayuki Tsutsui
  • Patent number: 8811531
    Abstract: Embodiments include but are not limited to apparatuses and systems including a quadrature lattice matching network including first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: August 19, 2014
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Peter V. Wright
  • Patent number: 8810312
    Abstract: An apparatus and an operating method of an asymmetric Doherty power amplifier. A Doherty power amplifier apparatus includes a power divider configured to provide a power signal to a carrier amplifier and a peaking amplifier. The apparatus also includes the carrier amplifier configured to amplify a power of the signal input from the power divider. The apparatus further includes the peaking amplifier configured to have a maximum output power magnitude different from the carrier amplifier and amplify the power of the signal input from the power divider. The apparatus still further includes at least two offset transmission lines disposed at ends of the carrier amplifier and the peaking amplifier and configured to regulate a load impedance. The apparatus also includes an output combiner configured to combine and output outputs of the carrier amplifier and the peaking amplifier of different sizes.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: August 19, 2014
    Assignees: Samsung Electronics Co., Ltd., Postech Academy-Industry Foundation Postech Univ. of Science and Technology
    Inventors: Il-Du Kim, Bumman Kim
  • Patent number: 8803604
    Abstract: A control circuit is for generating upper and lower voltages that define a range of a data voltage for controlling a driving transistor of an electroluminescent component coupled to a supply line through the driving transistor. The control circuit may include a first input terminal configured to have a common voltage, and a pair of amplifiers coupled together at the first input terminal and configured to generate the upper voltage and the lower voltage to correspond to a difference between the common voltage and, respectively, first and second analog intermediate voltages representing respective threshold values of the upper voltage and of the lower voltage. The control circuit may include an auxiliary amplifier configured to adjust the upper voltage and the lower voltage based upon fluctuations of an input voltage, and generate the common voltage to correspond to the difference between the input voltage and a reference voltage.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 12, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Giovanni Conti, Domenico Cristaudo, Stefano Corradi
  • Publication number: 20140218116
    Abstract: The present invention relates to a power amplifier apparatus and a power amplifier circuit thereof, the power amplifier circuit uses Doherty circuit structure, and the final stage power amplifier circuit uses high electron mobility transistor (HEMT) power amplifiers to achieve a Carrier amplifier with the Doherty circuit structure and a Peak amplifier with the Doherty circuit structure. The power amplifier apparatus and a power amplifier circuit thereof in the present invention improves the efficiency of the power amplifier.
    Type: Application
    Filed: October 28, 2011
    Publication date: August 7, 2014
    Applicant: ZTE CORPORATION
    Inventors: Xiaojun Cui, Huazhang Chen, Jianli Liu, Jinyuan An
  • Patent number: 8797099
    Abstract: The present invention relates to a power amplifier apparatus and power amplifier circuit, and the power amplifier circuit uses the Doherty circuit structure, and uses a high voltage heterojunction bipolor transistor (HVHBT) power amplifier to achieve a Carrier amplifier of the Doherty circuit structure, and uses lateral double-diffused metal oxide semiconductor (LDMOS) to achieve a Peak amplifier. The power amplifier apparatus and power amplifier circuit in the present invention improves the efficiency of the power amplifier.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: August 5, 2014
    Assignee: ZTE Corporation
    Inventors: Xiaojun Cui, Huazhang Chen, Jinyuan An, Jianli Liu
  • Patent number: 8798561
    Abstract: An RF circuit having a transcoupler, a multifunctional RF-circuit element that can operate both as an impedance inverter and as a signal coupler. When connected to a fixed load impedance, the transcoupler can also operate as an impedance transformer. The impedance-transformer/inverter functionality of the transcoupler can be used, e.g., to modulate the load of a power amplifier. The signal coupler functionality of the transcoupler can be used, e.g., to generate a corresponding feedback signal indicative of phase and/or amplitude distortions in the amplifier. The use of various embodiments of the transcoupler in an RF circuit can be advantageous, for example, because the transcoupler has a lower insertion loss than a cascade consisting of a prior-art impedance inverter and a prior-art directional coupler, occupies a relatively small area on the printed circuit board, and helps to reduce the per-unit fabrication and operating costs.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: August 5, 2014
    Assignee: Alcatel Lucent
    Inventor: Igor Acimovic
  • Patent number: 8797103
    Abstract: Apparatus and methods for capacitive load reduction are disclosed. In one embodiment, a power amplifier system includes an envelope tracker configured to provide a supply voltage to a plurality of power amplifiers. The power amplifiers include power supply inputs electrically connected in a star configuration so as to reduce a capacitive load of the envelope tracker. The distributed capacitance of the power amplifiers is used to provide RF grounding so as to reduce the size of or eliminated the use of bypass capacitors.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: August 5, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Daniel Lee Kaczman, James Phillip Young
  • Patent number: 8786369
    Abstract: According to one embodiment, a high frequency amplifier having a division circuit, FET cells, a stabilization circuit and a combination circuit is provided. The division circuit divides an input signal to produce a plurality of signals. The FET cells amplify the signals produced by the division circuit. The stabilization circuit provided with RC parallel-connected circuits which are respectively connected in series between the division circuit and gates of the FET cells. Each of the RC parallel-connected circuits has a capacitor and a resistor connected in parallel with each other. The combination circuit combines the signals amplified by the FET cells.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: July 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 8779856
    Abstract: A symmetric Doherty amplifier includes a main amplifier and a peaking amplifier of the same size as the main amplifier. The symmetric Doherty amplifier is configured to operate at peak output power when the main amplifier and the peaking amplifier are each in saturation, and at output-back-off (OBO) when the main amplifier is in saturation and the peaking amplifier is not in saturation. Phase shift circuitry is configured to shift the phase at an output of the peaking amplifier at OBO so that a load impedance seen by the main amplifier and efficiency of the symmetric Doherty amplifier both increase at OBO as a function of the phase shift at the peaking amplifier output.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Richard Wilson, Saurabh Goel
  • Publication number: 20140191805
    Abstract: A power amplifier using N-way Doherty structure with adaptive bias supply power tracking for extending the efficiency region over the high peak-to-average power:ratio of the multiplexing modulated signals such as wideband code division multiple access and orthogonal frequency division multiplexing is disclosed. In an embodiment, present invention uses a dual-feed distributed structure to an N-way Doherty amplifier to improve the isolation between at least one main amplifier and at least one peaking amplifier and, and also to improve both gain and efficiency performance at high output back-off power. Hybrid couplers can be used at either or both of the input and output. In at least some implementations, circuit space is also conserved due to the integration of amplification, power splitting and combining.
    Type: Application
    Filed: November 22, 2013
    Publication date: July 10, 2014
    Applicant: Dali Systems Co., Ltd.
    Inventors: Kyoung Joon Cho, Wan Jong Kim, Shawn Patrick Stapleton
  • Patent number: 8773206
    Abstract: The present invention relates to a power amplifier apparatus and a power amplifier circuit thereof, the power amplifier circuit uses Doherty circuit structure, and it uses a high voltage heterojunction bipolor transistor (HVHBT) power amplifier to achieve a Carrier amplifier with the Doherty circuit structure, and uses a high electron mobility transistor (HEMT) power amplifier to achieve a Peak amplifier with the Doherty circuit structure. The power amplifier apparatus and a power amplifier circuit thereof in the present invention improves the efficiency of the power amplifier.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 8, 2014
    Assignee: ZTE Corporation
    Inventors: Huazhang Chen, Xiaojun Cui, Jianli Liu
  • Patent number: 8773205
    Abstract: The present invention discloses a Doherty power amplifier and an implementation method thereof. A peak amplifying circuit of the Doherty power amplifier comprises a radio frequency switching circuit configured to control turn-on of the peak amplifying circuit; wherein a last stage carrier amplifier of a carrier amplifying circuit of the power amplifier uses a HVHBT device, and a last stage peak amplifier of the peak amplifying circuit of the power amplifier uses a GaN device. The present invention avoids the shortcoming when the peak branches in the Doherty power amplifier are turned on ahead of time, decreases power consumption of the peak amplifier and improves the batch efficiency of the whole Doherty power amplifier.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: July 8, 2014
    Assignee: ZTE Corporation
    Inventors: Huazhang Chen, Jianli Liu, Xiaojun Cui, Bin Duan
  • Publication number: 20140187175
    Abstract: Embodiments provide a radio frequency (RF) power amplifier (PA) circuit having a high-power mode and a low-power mode. The RF PA circuit may include a high-power amplifier to provide an amplified RF signal on a first path, and a low-power amplifier to provide an amplified RF signal on a second path. The first path and second path may intersect at a junction node. A switch may be coupled between the low-power amplifier and the junction node to switch the circuit between the high-power mode and the low-power mode. A matching circuit may be coupled on the second path to match an output impedance of the low-power amplifier to a junction impedance of the junction node at a fundamental frequency of the RF signal, and to present an open circuit at a third harmonic of the RF signal. The matching circuit may facilitate high efficiency for the RF PA circuit.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: TRIQUINT SEMICONDUCTOR, INC.
    Inventor: TRIQUINT SEMICONDUCTOR, INC.
  • Publication number: 20140184332
    Abstract: An amplifier circuit includes a digital amplifier configured to amplify an input signal to output a first output signal, an analog amplifier configured to amplify the input signal to output a second output signal, a check circuit configured to produce a check signal responsive to frequencies of the input signal, and a selector circuit configured to select and output one of the first output signal and the second output signal in response to the check signal.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Huan Shi, Hisanori Murata
  • Patent number: 8766427
    Abstract: An RF-power device includes a semiconductor substrate having a plurality of active regions arranged in an array. Each active region includes one or more RF-power transistors. The active regions are interspersed with inactive regions for reducing mutual heating of the RF-power transistors in separate active regions. The devices also includes at least one impedance matching component located in one of the inactive regions of the substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: July 1, 2014
    Assignee: NXP, B.V.
    Inventor: Marnix Bernard Willemsen
  • Publication number: 20140167857
    Abstract: A transconductance amplifier has a pair of input terminals and a pair of output terminals. A first pair of transconductors is connected to the input terminals and the output terminals. A second pair of transconductors has inputs connected to output terminals, and outputs connected to the opposing output terminals. A third pair of transconductors has both its inputs and its outputs connected to the output terminals. One or more of the transconductors have a control port for a control signal to adjust its transconductance. The control signal may switch the transconductance of this or these transconductors between two or more values. One or more of the transconductors in the transconductance amplifier may include a tri-state inverter, which may be enabled or disabled through a control port.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: NEWSOUTH INNOVATIONS PTY. LTD.
    Inventors: Julian Jenkins, Torsten Lehmann, James Paul Koeppe
  • Publication number: 20140167856
    Abstract: In a power amplifier, in response to a power mode signal at a predetermined level, a first switch circuit supplies a signal to first and second amplifier devices that perform parallel operations. In response to the power mode signal at another level, the first switch circuit supplies a signal to the first amplifier device and stops supplying the signal to the second amplifier device such that the first amplifier device performs a standalone operation. One end of an impedance adjusting circuit is connected to a connection node between the outputs of the first and second amplifier devices, the other end of the impedance adjusting circuit is connected to one end of a second switch circuit, and the other end of the second switch circuit is connected to a ground potential. The impedance adjusting circuit includes a reactance element.
    Type: Application
    Filed: September 17, 2013
    Publication date: June 19, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Wataru TAKAHASHI, Toshiki MATSUI, Jun SAKATSUME
  • Publication number: 20140167858
    Abstract: The disclosure relates to an amplifier device comprising an integrated circuit die (701a; 701b) having a first amplifier (702a; 702b) and a second amplifier. A Doherty amplifier may be implemented in accordance with the present invention. The amplifier device also comprises a first connector (706a; 706b) having a first end coupled to the first amplifier and a second end for coupling with a circuit board (718a; 718b), a second connector (708a; 708b) having a first end coupled to the second amplifier (704a; 704b) and a second end for coupling with a circuit board (718a; 718b), a shielding member (710a; 710b) having a first end coupled to the integrated circuit die (701a; 701b) and a second end for coupling with a circuit board (718a; 718b), the shielding member (710a; 710b) situated at least partially between the second connector and the first connector (706a; 706b) and a capacitor. The capacitor has a first plate and a second plate.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 19, 2014
    Applicant: NXP B.V.
    Inventors: Albert Gerardus Wilhelmus Philipus van Zuijlen, Vittorio Cuoco, Josephus Henricus Bartholomeus van der Zanden
  • Patent number: 8754709
    Abstract: The present invention discloses a Doherty power amplifier and a method for implementing the Doherty power amplifier. The Doherty power amplifier includes a peak amplifying branch and a carrier amplifying branch, wherein, the peak amplifying branch includes a radio frequency switch, and the radio frequency switch is configured to control on/off of a last stage peak power amplifier in the peak amplifying branch; wherein, a high voltage heterojunction bipolar transistor (HVHBT) device is adopted for a last stage carrier power amplifier of the carrier amplifying branch, and a laterally diffused metal oxide semiconductor (LDMOS) device is adopted for the last stage peak power amplifier of the peak amplifying branch of the power amplifier. By the present invention, it avoids that the peak power consumption is increased when the peak power amplifier is on ahead of time and enhances the efficiency of the whole power amplifier.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: June 17, 2014
    Assignee: ZTE Corporation
    Inventors: Huazhang Chen, Jianli Liu, Xiaojun Cui
  • Patent number: 8754710
    Abstract: Disclosed are low-noise amplifiers and SAW-less receivers. An exemplary amplifier includes at least two amplifier modules. The amplifier modules share a common output node and comprise a common input to which the amplifier modules are AC or DC coupled for receiving an inbound RF signal. The amplifier modules operate at different biases.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: June 17, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Qiang Li, Si-Ning Zhou, Chih-Ming Hung