Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.

Abstract: Radio frequency power amplifier circuitry includes an amplifier element, power supply modulation circuitry, and bias modulation circuitry. The amplifier element is configured to amplify an RF input signal using a modulated power supply signal and a modulated bias signal to produce an RF output signal. The power supply modulation circuitry is coupled to the amplifier element and configured to provide the modulated power supply signal. The bias modulation circuitry is coupled to the amplifier element and the power supply modulation circuitry and configured to receive the modulated power supply signal and provide the modulated bias signal. Notably, the modulated bias signal is a function of the modulated power supply signal such that the modulated bias signal is configured to maintain a small signal gain of the amplifier element and the phase of the RF input signal at a constant value as the modulated power supply signal changes.

Abstract: An amplifier circuit with at least one basic transistor, at least one load transistor, and at least one impedance element, the basic transistor being connected to the impedance element and the load transistor, an amplifier input and output, the amplifier input being connected to the gate contact of the basic transistor and the amplifier output being connected to a source contact of the load transistor. Here the amplifier circuit has at least two combined amplifying cells, with each combined amplifying cell respectively including a basic transistor, a load transistor, and an impedance element, with the basic transistor and the load transistor being non-complementary single-pin transistors, and arranged cooperating with the impedance element, and every combined amplifying cell has an input and an output, which cell input being connected to a gate contact of the basic transistor and which cell output being connected to a contact of the impedance element.

Abstract: A system linearization assembly generally includes a delay device that receives an input signal from a signal source and delays the input signal by a predetermined delay function. An attenuation device receives a modified output signal from a signal modifying device, wherein the output signal is based on the input signal and includes a time varying parameter representing a plurality of frequency components including at least one component caused by non-linear intermodulation distortion. The attenuation device attenuates the output signal by a factor that is equal to at least one parameter of the modifying device. A computing device compares the attenuated output signal with the delayed input signal to obtain a resultant signal that includes the component caused by non-linear intermodulation distortion. A detection device detects at least one parameter of the resultant signal. Based on the detected parameter, a controller facilitates a modification of the component.

Abstract: A polarity-switching amplifier circuit includes: a first amplifying transistor and a second amplifying transistor, a transformer which includes a primary winding and a secondary winding, and a polarity-switching controller. An unbalanced input signal is input to the first amplifying transistor and the second amplifying transistor. The transformer receives an output signal of the first amplifying transistor and an output signal of the second amplifying transistor as a balanced signal input to the primary winding, and outputs a signal from the secondary winding. The polarity-switching controller turns on one of the first amplifying transistor and the second amplifying transistor and turns off the other thereof.

Abstract: This disclosure relates generally to radio frequency (RF) amplification devices and methods of limiting an RF signal current. Embodiments of the RF amplification device include an RF amplification circuit and a feedback circuit. The RF amplification circuit is configured to amplify an RF input signal so as to generate an amplified RF signal that provides an RF signal current with a current magnitude. The feedback circuit is used to limit the RF signal current. In particular, a thermal sense element in the feedback circuit is configured to generate a sense current, and thermal conduction from the RF amplification circuit sets a sense current level of the sense current as being indicative of the current magnitude of the RF signal current. To limit the RF signal current, the feedback circuit decreases the current magnitude of the RF signal current in response to the sense current level reaching a trigger current level.

Abstract: Multimode power amplifier bias circuit with selectable bandwidth. In some embodiments, a bias circuit for a power amplifier can include a first bipolar junction transistor (BJT) configured to pass a reference current. The first BJT can be coupled with a second BJT that performs at least some amplification for the power amplifier. The first and second BJTs can be configured as a current mirror. The bias circuit can further include a coupling circuit that couples the collector and the base of the first BJT. The coupling circuit can include a switchable element to allow the coupling circuit to be in a first state or a second state. The first state can be configured to yield a first bandwidth for the bias circuit, and the second state can be configured to yield a second bandwidth for the bias circuit.

Abstract: There is disclosed a technique for controlling at least one amplification stage, comprising: selecting a linearity objective for the amplification stage; in dependence on an input signal to said amplification stage, determining a combination of supply input and bias input for the amplification stage in order to meet said linearity objective; and in dependence on there being more than one combination of supply input and bias input for meeting the linearity objective, selecting the combination that optimises a further system performance objective for the amplification stage. The further system performance objective may be one or more of: an efficiency objective; an envelope signal bandwidth objective; or a robustness to production tolerance objective.

Abstract: A radio frequency (RF) power amplifier is disclosed. The RF power amplifier includes a bias circuit, an output stage circuit and dynamic bias controlling circuit. The bias circuit receives a system voltage and the bias circuit provides a working voltage according to the system voltage. The output stage circuit receives the working voltage so as to work at an operation bias point. The dynamic bias controlling circuit receives the working voltage and outputs a compensation voltage to the bias circuit according to a variation of the working voltage. When the input power increases and makes the working voltage decreases so as to shift the operation bias point, the bias circuit adjusts the working voltage upward so as to recover the operation bias point according to the compensation voltage received.

Abstract: A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage.

Abstract: A power amplifier configured to boost an AC signal. The power amplifier includes a first transistor, a second transistor, a first inductor connected between the first transistor and a voltage source, and a second inductor connected between the second transistor and ground. A first phase conditioner arranged at an input of the first transistor is configured to condition a phase of the AC signal such that the AC signal as received by the first transistor is out of phase with respect to the AC signal as received by the first inductor. A second phase conditioner arranged at an input of the second transistor is configured to condition a phase of the AC signal such that the AC signal as received by the second transistor is out of phase with respect to the AC signal as received by the second inductor.

Abstract: A high voltage amplifier and a method of assembling and of operating a high voltage amplifier are described. The device includes a first metal-oxide-semiconductor field-effect transistor (MOSFET) driven by a first gate drive circuit. The device also includes a second MOSFET driven by a second gate drive circuit and a first optocoupler coupled to the second gate drive circuit. The first MOSFET and the second MOSFET of the high voltage amplifier drive a first output voltage.

Abstract: A bias generation method or apparatus defined by any one or any practical combination of numerous features that contribute to low noise and/or high efficiency biasing, including: having a charge pump control clock output with a waveform having limited harmonic content or distortion compared to a sine wave; having a ring oscillator to generating a charge pump clock that includes inverters current limited by cascode devices and achieves substantially rail-to-rail output amplitude; having a differential ring oscillator with optional startup and/or phase locking features to produce two phase outputs suitably matched and in adequate phase opposition; having a ring oscillator of less than five stages generating a charge pump clock; capacitively coupling the clock output(s) to some or all of the charge transfer capacitor switches; biasing an FET, which is capacitively coupled to a drive signal, to a bias voltage via an “active bias resistor” circuit that conducts between output terminals only during portions of a wa

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: Linearity and power efficiency in a power amplifier circuit are enhanced. The power amplifier circuit includes a first transistor that amplifies a signal input to the base and that outputs the amplified signal from the collector and a first capacitor that is disposed between the base and the collector of the first transistor and that has voltage dependency of a capacitance value lower than that of a base-collector parasitic capacitance value of the first transistor.

Abstract: An amplifier circuit, comprising: an input, for receiving an input signal to be amplified; a power amplifier, for amplifying the input signal; a switched power supply, having a switching frequency, for providing at least one supply voltage to the power amplifier; and a dither block, for dithering the switching frequency of the switched power supply. The dither block is controlled based on the input signal. Another aspect of the invention involves using first and second switches, each having different capacitances and resistances, and using the first or second switch depending on the input signal or volume signal. Another aspect of the invention involves controlling a bias signal provided to one or more components in the signal path based on the input signal or volume signal.

Abstract: A circuit for amplifying radio frequency signals comprising: a terminal for connection to an antenna; a common amplifier arranged in a common-gate configuration between a first node and said terminal; a transmit amplifier operable to amplify a radio frequency signal present at an input node and provide the amplified signal to said first node; and a receive amplifier operable to amplify a radio frequency signal present at said first node and provide the amplified signal to an output node; wherein the circuit is operable in two modes: in a receive mode, the common and receive amplifiers being configured so as to together form a receive cascode for amplifying radio frequency signals received at the terminal; and in a transmit mode, the common and transmit amplifiers being configured so as to together form a transmit cascode for amplifying radio frequency signals applied at the input node.

Abstract: Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.

Abstract: A power amplifier module includes a first amplification transistor that amplifies and outputs a radio frequency signal, a second amplification transistor that is connected in parallel to the first amplification transistor and that has a smaller size than the first amplification transistor, a bias circuit that supplies a bias voltage or a bias current to the first and second amplification transistors, a current detector circuit that detects a current flowing in the second amplification transistor, and a bias control circuit that controls the bias voltage or the bias current supplied from the bias circuit to the first and second amplification transistors depending on the detection result of the current detector circuit.

Abstract: The present disclosure includes circuits and methods for wideband biasing. In one embodiment, an amplifiers includes a cascode transistor between an input and an output of the amplifier. The cascode transistor receives a bias from a bias circuit comprising a resistor between the power supply and a first node, a resistor between the first node and a reference voltage, and a capacitor between the power supply and the first node. The power supply may be a modulated power supply, which is coupled through the bias circuit to a capacitance at the control terminal of the cascode transistor. An inductor is configured between a terminal of the cascode transistor and the power supply. The inductor may isolate the output from the modulated supply signal.

Abstract: A power amplifier is smaller in size and limits input noise having a differential frequency. A power amplifier has an input terminal, an amplifying transistor, a bias circuit, a filter circuit, and an impedance matching circuit. The bias circuit supplies a bias to the signal input side of the amplifying transistor. The filter circuit removes noise at the signal input side of the amplifying transistor. The filter circuit has a matching resistor, a chip inductor, and a chip capacitor. Each of the chip inductor and the chip capacitor is a surface mount device. The matching resistor is located on a semiconductor substrate, has a first end connected to a connection point of two MIM capacitors, and a second end connected to a connection point of one of the MIM capacitors and the signal input side of the amplifying transistor.

Abstract: A novel and useful configurable radio frequency (RF) power amplifier (PA) and related front end module (FEM) circuit that enables manipulation of the operating point of the power amplifier resulting in configurability, multimode and multiband operating capability. The configurable PA also provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configurable power amplifier is made up of one or more configurable sub-amplifiers having each constructed to have several orders of freedom (i.e. biasing points). Each sub-amplifier and its combiner path include active and passive elements. Manipulating one or more biasing points of each sub-amplifier, and therefore of the aggregate power amplifier as well, achieves multimode and multiband operation. Biasing points include, for example, the gain and saturation point, frequency response, linearity level and EVM.

Abstract: A circuit may include one or more transistors connected directly to an output, and a biasing network connected to at least one of a substrate, a well, and a back-gate of at least one of the transistors. The biasing network may biase the at least one of the substrate, the well, and the back-gate to a virtual floating bias, such that the virtual floating bias shifts in voltage level based upon an AC input signal of the circuit, to reduce the parasitic capacitance of the output node of the circuit.

Abstract: A circuit and technique are provided to control bias setting to an FET based common source RF amplifier that can operate with large signals present. The circuit and technique described herein use a second FET in an identical circuit having the gate circuits connected in parallel and being sourced by the same drain voltage that serves as a reference to a first circuit bias setting. The drain current in a first FET will include both the bias and RF amplification current, whereas the second FET only carries the bias current. Because the devices and circuits are matched, the gate voltage variations will appear in both FETs thereby providing regulation of the drain current.

Abstract: Low power low noise input bias current compensation for an amplifier input stage is provided by recycling the tail current of the differential pair transistors. A local amplifier regulates the tail current and buffers the base current of the tail current transistor, which is mirrored back to the input transistors to provide input bias current compensation.

Abstract: A bias circuit for biasing a field effect transistor (FET) to provide a transconductance (gm) that is substantially unaffected by power supply voltage variations. In one embodiment the circuit includes two parallel current paths, each including two amplifying elements such as FETs, the FETs in one of the paths both being diode-connected, and the FETs in the other path not being diode-connected. Variations in the power supply voltage result in comparable changes in the voltage drops across all four FETs, and drain-induced barrier lowering (DIBL) results in relatively small changes in gm with changes in power supply voltage.

Abstract: The present invention provides a power amplifier that can reduce irregularities in characteristics such as gains. A high-frequency power amplifier that is used for a mobile communication terminal includes: an amplifier element that includes a composite semiconductor bipolar transistor and that amplifies high-frequency power of a predetermined frequency band with a bias voltage and a bias current supplied thereto; a bias circuit that supplies the bias voltage and the bias current to the amplifier element on the basis of a bias reference voltage; a bias reference voltage supply circuit that generates and supplies the bias reference voltage to the bias circuit; and a bias reference voltage control unit that controls the bias reference voltage supply circuit so as to generate the bias reference voltage of a voltage corresponding to a given signal.

Abstract: A feedback gate bias circuit for use in radio frequency amplifiers to more effectively control operation of LDFET, GaNFET, GaAsFET, and JFET type transistors used in such circuits. A transistor gate bias circuit that senses drain current and automatically adjusts or biases the gate voltage to maintain drain current independently of temperature, time, input drive, frequency, as well as from device to device variations. Additional circuits to provide temperature compensation, RF power monitoring and drain current control, RF output power leveler, high power gain block, and optional digital control of various functions. A gate bias circuit including a bias sequencer and negative voltage deriver for operation of N-channel depletion mode devices.

Abstract: A method and apparatus for memory modeling in a pre-distortion architecture are disclosed. In one embodiment, a memory model has a plurality of branches. Each branch receives a different output basis function signal. Each branch includes at least one delay element. Each delay element causes a pre-determined delay of the output basis function signal received by the branch. The amount of a pre-determined delay is different for each of at least two branches.

Abstract: An amplifier including an input stage, an output stage, an adjustable bias current generator and a level detector. The input stage may receive and amplify or buffer an input signal. The input stage may be biased by a first bias current. The output stage may supply an output signal to an amplifier load. The output stage may be biased with a second bias current. The adjustable bias current generator may be operatively coupled to the input stage and the output stage to supply these with the first and second bias currents, respectively. The level detector may be operatively coupled to the input signal and the adjustable bias current generator to control the first and second bias currents depending upon the input signal. The adjustable bias current generator may adjust the respective levels of first and second bias currents in opposite directions. Disclosed is an electroacoustical transducer incorporating the amplifier.

Abstract: A radio frequency generator includes a power control module, a frequency control module and a pulse generating module. The power control module is configured to generate a power signal indicating power levels for target states of a power amplifier. The frequency control module is configured to generate a frequency signal indicating frequencies for the target states of the power amplifier. The pulse generating module is configured to (i) supply an output signal to the power amplifier, (ii) recall at least one of a latest power level or a latest frequency for one of the target states of the power amplifier, and (iii) adjust a current power level and a current frequency of the output signal from a first state to a second state based on the power signal, the frequency signal, and at least one of the latest power level and the latest frequency of the power amplifier.

Abstract: Apparatus and methods for biasing power amplifiers are disclosed herein. In certain implementations, a power amplifier system includes a power amplifier and a bias circuit that generates a bias voltage for biasing the power amplifier. The bias circuit includes an amplifier, a current source for generating a reference current, and a reference transistor having a current therethrough that changes in relation to the bias voltage. The amplifier can control the bias voltage based on an error current corresponding to a difference between the reference current and the current through the reference transistor. The amplifier can be used to control the bias voltage such that the reference current and the current through the reference transistor are substantially equal.

Abstract: A comparator circuit comprising an operational amplifier configured to compare a difference between a switching voltage and a reference voltage, and a dynamically adjustable bias current generator coupled to the operational amplifier. A method of conserving power in a comparator circuit includes estimating a switching regulator load current value, communicating the value to a current bias generator, enabling the bias generator with a signal from a switching regulator PFM logic circuit, and establishing a bias current at an operational amplifier of the comparator circuit on the basis of the enabling.

Abstract: A current source circuit includes a first transistor Q1, a second transistor Q2, a first resistor R1, and a second resistor R2. The first transistor Q1 has a first terminal (collector) coupled with the supply voltage (VCC), a second terminal (base) coupled with the first resistor R1, and a third terminal (emitter) coupled with the second resistor R2. The second transistor Q2 has a first terminal coupled with the second terminal of the first transistor Q1, a second terminal coupled with the third terminal of the first transistor Q1, and a third terminal coupled with the filtering circuit 39. The first resistor R1 is coupled between the supply voltage and a second terminal of the first transistor Q1. The second resistor R2 is coupled between a third terminal of the first transistor Q1 and the filtering circuit 39.

Abstract: The invention relates to a method of calibrating an envelope path and an input path of an amplification stage of an envelope tracking power supply, the method comprising matching the envelope path to at least one characteristic of at least one element of the input path.

Abstract: An output stage circuit is provided, which includes a power supply, a quiescent current control circuit, an output circuit, and a quiescent current equalization circuit. The quiescent current equalization circuit is configured to decrease or increase a quiescent current flowing through a quiescent current biasing circuit in the quiescent current control circuit when a change of a voltage of the power supply is detected, such that a quiescent current flowing through the output circuit remains constant. A quiescent current equalization method, a Class AB amplifier and an electronic device are also provided. When the voltage of the power supply is increased, the quiescent current of the output circuit of the output stage circuit can maintain constant. As such, the power supply rejection ratio (PSRR) of the output circuit can be efficiently increased and the power consumption of the device can be reduced.

Abstract: Power amplifier circuitry includes a power amplifier including an input node and an output node, biasing circuitry, a selectable impedance network, and an input capacitor. The input capacitor is coupled to the input node of the power amplifier. The biasing circuitry is coupled to the input node of the power amplifier through the selectable impedance network. The power amplifier is operable in a low power operating mode and a high power operating mode. In the low power operating mode, the biasing circuitry delivers a first biasing current to the input node of the power amplifier, and a first impedance level of the selectable impedance is selected. In the high power operating mode, the biasing circuitry delivers a second biasing current to the input node of the power amplifier, and a second impedance level of the selectable impedance is selected.

Abstract: A driver circuit includes a first sub-driver circuit having an input coupled to receive a first pulsed signal, the first sub-driver circuit being configured to generate a first driver signal at an output thereof in response to the first pulsed signal, the first driver signal having relatively fast edge transitions and a low current capability. Also included is a second sub-driver circuit having an input coupled to receive a second pulsed signal, the second sub-driver circuit being configured to generate a second driver signal at an output thereof in response to the second pulsed signal, the second driver signal having edge transitions that are slower than those of the first driver signal and a current capability that is higher than that of the first driver signal.

Abstract: A radio frequency (RF) circuit includes an amplifier circuit comprising at least one transistor amplifier having first, second, and third terminals. The RF circuit additionally includes a driver circuit comprising an enhancement-mode transistor and a depletion-mode transistor coupled in a cascade configuration having an upper portion and a lower portion, the driver circuit having an output coupled to an input of the amplifier circuit such that the driver circuit is capable of providing pulsed signals as well as a direct-current (DC) bias current to at least one terminal of a transistor amplifier of the amplifier circuit. A corresponding method is also provided.

Abstract: A class-AB amplifier has upper side and lower side transistors, a linear driver, upper side and lower side idlers, upper side and lower side detection current generators, and an off driver. The upper side and lower side idlers bias upper side and lower side gate voltages by generating upper side and lower side bias currents so as to turn on the upper side and the lower side transistors at the same time in the crossover region between an input voltage and a reference voltage respectively. The upper side detection current generator and the lower side detection current generator generates upper side and lower side detection currents in accordance with upper side and lower side bias currents respectively.

Abstract: A radio frequency (RF) amplifier is disclosed. The RF power amplifier includes a bias circuit, an output-stage circuit and a RF compensation circuit. When a first system voltage is larger than a first voltage threshold value, the bias circuit generates a first current rising slightly. When first system voltage is larger than second voltage threshold value, the RF compensation circuit receives a second circuit rising slightly transmitted from the bias circuit. When the first system voltage is in an operation voltage range, the first current is larger than the second circuit so as to a quiescent operating current of the RF power amplifier is independent of change of the first system voltage. When the first system voltage is larger than a third voltage threshold value, the first current is equal to the second current so as to have the bias current being a zero current to protect the RF power amplifier from over-voltage.

Abstract: A receiver is disclosed. The receiver includes an amplifier and a bias circuit configured to provide a bias current to the amplifier. The bias circuit is self biasing. The bias circuit is also configured to adjust the bias current using positive feedback from the amplifier.

Abstract: An apparatus for providing a linearity information associated with an amplifier includes an operating state determinator and an evaluator. The operating state determinator is configured to obtain information describing a gain of the amplifier for at least one bias condition of the amplifier. The evaluator is configured to obtain the linearity information based on both the information describing the gain of the amplifier and information about the at least one bias condition of the amplifier using a gain-bias characteristic of the amplifier. A bias circuit including the apparatus for providing the linearity information is also disclosed.

Abstract: A sense amplifier system and sensing method thereof are provided. The proposed sense amplifier system includes plural sense amplifiers, each of which includes a first switch having a first terminal, a second terminal, and a bulk terminal electrically connected to the first terminal, a second switch having a first terminal electrically connected to the second terminal of the first switch, a second terminal, and a bulk terminal, a third switch having a first terminal electrically connected to the first terminal of the second switch, a second terminal, and a bulk terminal electrically connected to the bulk terminal of the second switch, and a fourth switch having a first terminal electrically connected to the bulk terminal of the first switch and a second terminal electrically connected to the bulk terminal of the third switch.

Abstract: A current amplifier and a transmitter using the same. The current amplifier includes: a first transistor having a gate coupled to a former-stage circuit, a drain coupled to a current source, and a source biased at a constant voltage level; a second transistor having a gate coupled to the current source and having a source and a drain; a first impedance circuit coupled between the gate of the first transistor and the source of the second transistor; and a second impedance circuit coupled between the source of the second transistor and a ground terminal The current amplifier receives an input current from the former-stage circuit and generates an output current at the drain of the second transistor. Note that no current source is connected to the source of the first transistor.

Abstract: In one embodiment, saturation of the control system of a power amplifier is limited by comparing a control voltage at a first control node against a scaled battery voltage, and then drawing an error current away from the first control node when the control voltage exceeds the scaled battery voltage. The first control node may be located after a trans-conductance amplifier in a feedback control system.

Abstract: The present disclosure relates to a power amplifier, the power amplifier comprising a first amplifier including at least two first transistors whose sources are commonly connected to form a common source, a second amplifier including at least two second transistors whose gates are commonly connected to form a common gate, the at least two second transistors being connected to the at least two first transistors in a cascode structure; and a bias supplier configured to apply to the common gate of the second amplifier a bias voltage that changes in response to an input and output power.

Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.

Abstract: The invention provides a semiconductor integrated circuit device and a high-frequency power amplifier module capable of reducing variations in the transmission power characteristics. The semiconductor integrated circuit device and the high-frequency power amplifier module each include, for example, a bandgap reference circuit, a regulator circuit, and a reference-voltage correction circuit which is provided between the bandgap reference circuit and the regulator circuit and which includes a unity gain buffer. The reference-voltage correction circuit corrects variations in a bandgap voltage from the bandgap reference circuit. The reference-voltage correction circuit includes first to third resistance paths having mutually different resistance values, and corrects the variations by selectively supplying a current which reflects an output voltage of the unity gain buffer to any one of the first to third resistance paths.

Abstract: Apparatus and methods for radio frequency (RF) amplifiers are disclosed herein. In certain implementations, a packaged RF amplifier includes a first bipolar transistor including a base electrically connected to an RF input pin and a collector electrically connected to an RF output pin, and a second bipolar transistor including a base electrically connected to an emitter of the first bipolar transistor and a collector electrically connected to the RF output pin. The packaged RF amplifier further includes a first bias circuit electrically connected between the base of the first bipolar transistor and the RF output pin, a second bias circuit electrically connected between the base of the first bipolar transistor and a power low pin, an inductor implemented at least partly by a bond wire, and a third bias circuit electrically connected in series with the inductor between the base of the second bipolar transistor and the power low pin.